Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2357,13 +2357,6 @@
         MachineBasicBlock::reverse_iterator E = MI.getParent()->rend(), It = MI;
         It++;
         unsigned Reg = MI.getOperand(i).getReg();
-        // MachineInstr::readsRegister only returns true if the machine
-        // instruction reads the exact register or its super-register. It
-        // does not consider uses of sub-registers which seems like strange
-        // behaviour. Nonetheless, if we end up with a 64-bit register here,
-        // get the corresponding 32-bit register to check.
-        if (PPC::G8RCRegClass.contains(Reg))
-          Reg = Reg - PPC::X0 + PPC::R0;
 
         // Is this register defined by some form of add-immediate (including
         // load-immediate) within this basic block?
@@ -3183,14 +3176,7 @@
   if (MRI.isSSA())
     return false;
 
-  // MachineInstr::readsRegister only returns true if the machine
-  // instruction reads the exact register or its super-register. It
-  // does not consider uses of sub-registers which seems like strange
-  // behaviour. Nonetheless, if we end up with a 64-bit register here,
-  // get the corresponding 32-bit register to check.
   unsigned Reg = RegMO.getReg();
-  if (PPC::G8RCRegClass.contains(Reg))
-    Reg = Reg - PPC::X0 + PPC::R0;
 
   // Walking the inst in reverse(MI-->DefMI) to get the last DEF of the Reg.
   MachineBasicBlock::const_reverse_iterator It = MI;
Index: llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instr-add.mir
===================================================================
--- llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instr-add.mir
+++ llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instr-add.mir
@@ -15,3 +15,21 @@
     ; CHECK: STD killed $x3, killed $x5, 100
     BLR8 implicit $lr8, implicit $rm
 ...
+---
+# No workaround needed for 64-bit register when calling readsRegister()
+name: testReadsSubRegADDI
+# CHECK: name: testReadsSubRegADDI
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $x3, $f1, $x5
+    $x3 = ADDI8 $x5, 100
+    ; Following instruction $r3 also reads $x3, ADDI8 can not be erased
+    ; CHECK: $x3 = ADDI8 $x5, 100, implicit-def $r3
+    STW $r3, $x5, 100
+    ; CHECK: STW $r3, $x5, 100
+    STFSX killed $f1, $zero8, $x3
+    ; CHECK: STFS killed $f1, 100, $x5
+    STD $x5, $x5, 100
+    BLR8 implicit $lr8, implicit $rm
+...