Index: llvm/lib/Target/PowerPC/PPCFastISel.cpp =================================================================== --- llvm/lib/Target/PowerPC/PPCFastISel.cpp +++ llvm/lib/Target/PowerPC/PPCFastISel.cpp @@ -151,6 +151,14 @@ bool isVSSRCRegClass(const TargetRegisterClass *RC) const { return RC->getID() == PPC::VSSRCRegClassID; } + unsigned copyRegToRegClass(const TargetRegisterClass *ToRC, + unsigned SrcReg, unsigned Flag = 0, + unsigned SubReg = 0) { + unsigned TmpReg = createResultReg(ToRC); + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, + TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg, Flag, SubReg); + return TmpReg; + } bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value, bool isZExt, unsigned DestReg, const PPC::Predicate Pred); @@ -877,18 +885,10 @@ } } else { CmpOpc = PPC::FCMPUS; - if (isVSSRCRegClass(RC1)) { - unsigned TmpReg = createResultReg(&PPC::F4RCRegClass); - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, - TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg1); - SrcReg1 = TmpReg; - } - if (RC2 && isVSSRCRegClass(RC2)) { - unsigned TmpReg = createResultReg(&PPC::F4RCRegClass); - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, - TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg2); - SrcReg2 = TmpReg; - } + if (isVSSRCRegClass(RC1)) + SrcReg1 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg1); + if (RC2 && isVSSRCRegClass(RC2)) + SrcReg2 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg2); } break; case MVT::f64: @@ -1210,13 +1210,8 @@ // Convert f32 to f64 if necessary. This is just a meaningless copy // to get the register class right. const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg); - if (InRC == &PPC::F4RCRegClass) { - unsigned TmpReg = createResultReg(&PPC::F8RCRegClass); - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, - TII.get(TargetOpcode::COPY), TmpReg) - .addReg(SrcReg); - SrcReg = TmpReg; - } + if (InRC == &PPC::F4RCRegClass) + SrcReg = copyRegToRegClass(&PPC::F8RCRegClass, SrcReg); // Determine the opcode for the conversion, which takes place // entirely within FPRs. @@ -1510,11 +1505,7 @@ if (RetVT == CopyVT) { const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT); - ResultReg = createResultReg(CpyRC); - - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, - TII.get(TargetOpcode::COPY), ResultReg) - .addReg(SourcePhysReg); + ResultReg = copyRegToRegClass(CpyRC, SourcePhysReg); // If necessary, round the floating result to single precision. } else if (CopyVT == MVT::f64) { @@ -1527,12 +1518,9 @@ // used along the fast-isel path (not lowered), and downstream logic // also doesn't like a direct subreg copy on a physical reg.) } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) { - ResultReg = createResultReg(&PPC::GPRCRegClass); // Convert physical register from G8RC to GPRC. SourcePhysReg -= PPC::X0 - PPC::R0; - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, - TII.get(TargetOpcode::COPY), ResultReg) - .addReg(SourcePhysReg); + ResultReg = copyRegToRegClass(&PPC::GPRCRegClass, SourcePhysReg); } assert(ResultReg && "ResultReg unset!"); @@ -1884,13 +1872,8 @@ return false; // The only interesting case is when we need to switch register classes. - if (SrcVT == MVT::i64) { - unsigned ResultReg = createResultReg(&PPC::GPRCRegClass); - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, - TII.get(TargetOpcode::COPY), - ResultReg).addReg(SrcReg, 0, PPC::sub_32); - SrcReg = ResultReg; - } + if (SrcVT == MVT::i64) + SrcReg = copyRegToRegClass(&PPC::GPRCRegClass, SrcReg, 0, PPC::sub_32); updateValueMap(I, SrcReg); return true;