Index: llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -997,19 +997,24 @@
                                                    bool AllowParens) {
   SMLoc FirstS = getLoc();
   bool HadParens = false;
-  AsmToken Buf[2];
+  AsmToken LParen;
 
-  // If this a parenthesised register name is allowed, parse it atomically
+  // If this is an LParen and a parenthesised register name is allowed, parse it
+  // atomically.
   if (AllowParens && getLexer().is(AsmToken::LParen)) {
+    AsmToken Buf[2];
     size_t ReadCount = getLexer().peekTokens(Buf);
     if (ReadCount == 2 && Buf[1].getKind() == AsmToken::RParen) {
       HadParens = true;
+      LParen = getParser().getTok();
       getParser().Lex(); // Eat '('
     }
   }
 
   switch (getLexer().getKind()) {
   default:
+    if (HadParens)
+      getLexer().UnLex(LParen);
     return MatchOperand_NoMatch;
   case AsmToken::Identifier:
     StringRef Name = getLexer().getTok().getIdentifier();
@@ -1018,7 +1023,7 @@
 
     if (RegNo == 0) {
       if (HadParens)
-        getLexer().UnLex(Buf[0]);
+        getLexer().UnLex(LParen);
       return MatchOperand_NoMatch;
     }
     if (HadParens)
Index: llvm/trunk/test/MC/RISCV/rv32i-valid.s
===================================================================
--- llvm/trunk/test/MC/RISCV/rv32i-valid.s
+++ llvm/trunk/test/MC/RISCV/rv32i-valid.s
@@ -84,6 +84,12 @@
 # CHECK-ASM-AND-OBJ: jal a0, 30
 # CHECK-ASM: encoding: [0x6f,0x05,0xe0,0x01]
 jal a0, CONST
+# CHECK-ASM-AND-OBJ: jal s0, 0
+# CHECK-ASM: encoding: [0x6f,0x04,0x00,0x00]
+jal s0, (0)
+# CHECK-ASM-AND-OBJ: jal s0, 156
+# CHECK-ASM: encoding: [0x6f,0x04,0xc0,0x09]
+jal s0, (0xff-99)
 
 # CHECK-ASM-AND-OBJ: jalr a0, a1, -2048
 # CHECK-ASM: encoding: [0x67,0x85,0x05,0x80]
@@ -154,6 +160,12 @@
 # CHECK-ASM-AND-OBJ: lb t0, 30(t1)
 # CHECK-ASM: encoding: [0x83,0x02,0xe3,0x01]
 lb t0, CONST(t1)
+# CHECK-ASM-AND-OBJ: lb s0, 0(s1)
+# CHECK-ASM: encoding: [0x03,0x84,0x04,0x00]
+lb s0, (0)(s1)
+# CHECK-ASM-AND-OBJ: lb s0, 156(s1)
+# CHECK-ASM: encoding: [0x03,0x84,0xc4,0x09]
+lb s0, (0xff-99)(s1)
 
 # CHECK-ASM-AND-OBJ: sb a0, 2047(a2)
 # CHECK-ASM: encoding: [0xa3,0x0f,0xa6,0x7e]
@@ -170,6 +182,12 @@
 # CHECK-ASM-AND-OBJ: sw a0, 30(t0)
 # CHECK-ASM: encoding: [0x23,0xaf,0xa2,0x00]
 sw a0, CONST(t0)
+# CHECK-ASM-AND-OBJ: sw s0, 0(s1)
+# CHECK-ASM: encoding: [0x23,0xa0,0x84,0x00]
+sw s0, (0)(s1)
+# CHECK-ASM-AND-OBJ: sw s0, 156(s1)
+# CHECK-ASM: encoding: [0x23,0xae,0x84,0x08]
+sw s0, (0xff-99)(s1)
 
 # CHECK-ASM-AND-OBJ: addi ra, sp, 2
 # CHECK-ASM: encoding: [0x93,0x00,0x21,0x00]
@@ -182,6 +200,12 @@
 # CHECK-ASM-AND-OBJ: addi ra, sp, 30
 # CHECK-ASM: encoding: [0x93,0x00,0xe1,0x01]
 addi ra, sp, CONST
+# CHECK-ASM-AND-OBJ: addi ra, sp, 0
+# CHECK-ASM: encoding: [0x93,0x00,0x01,0x00]
+addi ra, sp, (0)
+# CHECK-ASM-AND-OBJ: addi ra, sp, 156
+# CHECK-ASM: encoding: [0x93,0x00,0xc1,0x09]
+addi ra, sp, (0xff-99)
 # CHECK-ASM-AND-OBJ: slti a0, a2, -20
 # CHECK-ASM: encoding: [0x13,0x25,0xc6,0xfe]
 slti a0, a2, -20