Index: lib/Target/ARM/ARM.td =================================================================== --- lib/Target/ARM/ARM.td +++ lib/Target/ARM/ARM.td @@ -228,6 +228,15 @@ FeatureAvoidPartialCPSR, FeatureTrustZone, FeatureVirtualization]>; +def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17", + "Cortex-A17 ARM processors", + [FeatureVMLxForwarding, + FeatureT2XtPk, FeatureVFP4, + FeatureHWDiv, FeatureHWDivARM, + FeatureAvoidPartialCPSR, + FeatureVirtualization, + FeatureTrustZone]>; + def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", "Cortex-A53 ARM processors", [FeatureHWDiv, FeatureHWDivARM, @@ -366,6 +375,12 @@ FeatureDSPThumb2, FeatureHasRAS, FeatureAClass]>; +// FIXME: A17 has currently the same Schedule model as A9 +def : ProcessorModel<"cortex-a17", CortexA9Model, + [ProcA17, HasV7Ops, FeatureNEON, FeatureDB, + FeatureDSPThumb2, FeatureMP, + FeatureHasRAS, FeatureAClass]>; + // FIXME: krait has currently the same Schedule model as A9 def : ProcessorModel<"krait", CortexA9Model, [ProcKrait, HasV7Ops, Index: lib/Target/ARM/ARMSubtarget.h =================================================================== --- lib/Target/ARM/ARMSubtarget.h +++ lib/Target/ARM/ARMSubtarget.h @@ -42,7 +42,7 @@ protected: enum ARMProcFamilyEnum { Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15, - CortexR5, Swift, CortexA53, CortexA57, Krait + CortexA17, CortexR5, Swift, CortexA53, CortexA57, Krait, }; enum ARMProcClassEnum { None, AClass, RClass, MClass Index: test/CodeGen/ARM/build-attributes.ll =================================================================== --- test/CodeGen/ARM/build-attributes.ll +++ test/CodeGen/ARM/build-attributes.ll @@ -22,6 +22,8 @@ ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-A12-NOFPU ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9-mp | FileCheck %s --check-prefix=CORTEX-A9-MP ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 | FileCheck %s --check-prefix=CORTEX-A15 +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 | FileCheck %s --check-prefix=CORTEX-A17-DEFAULT +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-A17-NOFPU ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=CORTEX-M0 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 | FileCheck %s --check-prefix=CORTEX-M3 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-M4-SOFT @@ -375,6 +377,36 @@ ; CORTEX-A15: .eabi_attribute 44, 2 ; CORTEX-A15: .eabi_attribute 68, 3 +; CORTEX-A17-DEFAULT: .cpu cortex-a17 +; CORTEX-A17-DEFAULT: .eabi_attribute 6, 10 +; CORTEX-A17-DEFAULT: .eabi_attribute 7, 65 +; CORTEX-A17-DEFAULT: .eabi_attribute 8, 1 +; CORTEX-A17-DEFAULT: .eabi_attribute 9, 2 +; CORTEX-A17-DEFAULT: .fpu neon-vfpv4 +; CORTEX-A17-DEFAULT: .eabi_attribute 20, 1 +; CORTEX-A17-DEFAULT: .eabi_attribute 21, 1 +; CORTEX-A17-DEFAULT: .eabi_attribute 23, 3 +; CORTEX-A17-DEFAULT: .eabi_attribute 24, 1 +; CORTEX-A17-DEFAULT: .eabi_attribute 25, 1 +; CORTEX-A17-DEFAULT: .eabi_attribute 42, 1 +; CORTEX-A17-DEFAULT: .eabi_attribute 44, 2 +; CORTEX-A17-DEFAULT: .eabi_attribute 68, 3 + +; CORTEX-A17-NOFPU: .cpu cortex-a17 +; CORTEX-A17-NOFPU: .eabi_attribute 6, 10 +; CORTEX-A17-NOFPU: .eabi_attribute 7, 65 +; CORTEX-A17-NOFPU: .eabi_attribute 8, 1 +; CORTEX-A17-NOFPU: .eabi_attribute 9, 2 +; CORTEX-A17-NOFPU-NOT: .fpu +; CORTEX-A17-NOFPU: .eabi_attribute 20, 1 +; CORTEX-A17-NOFPU: .eabi_attribute 21, 1 +; CORTEX-A17-NOFPU: .eabi_attribute 23, 3 +; CORTEX-A17-NOFPU: .eabi_attribute 24, 1 +; CORTEX-A17-NOFPU: .eabi_attribute 25, 1 +; CORTEX-A17-NOFPU: .eabi_attribute 42, 1 +; CORTEX-A17-NOFPU: .eabi_attribute 44, 2 +; CORTEX-A17-NOFPU: .eabi_attribute 68, 3 + ; CORTEX-M0: .cpu cortex-m0 ; CORTEX-M0: .eabi_attribute 6, 12 ; CORTEX-M0-NOT: .eabi_attribute 7