Index: docs/WritingAnLLVMBackend.rst =================================================================== --- docs/WritingAnLLVMBackend.rst +++ docs/WritingAnLLVMBackend.rst @@ -161,7 +161,7 @@ know about your target when parsing the ``--enable-targets`` option. Search the configure script for ``TARGETS_TO_BUILD``, add your target to the lists there (some creativity required), and then reconfigure. Alternatively, you can -change ``autoconf/configure.ac`` and regenerate configure by running +change ``autotools/configure.ac`` and regenerate configure by running ``./autoconf/AutoRegen.sh``. Target Machine Index: include/llvm/MC/MCDisassembler.h =================================================================== --- include/llvm/MC/MCDisassembler.h +++ include/llvm/MC/MCDisassembler.h @@ -22,8 +22,8 @@ class raw_ostream; class MCContext; -/// Superclass for all disassemblers. Consumes a memory region and provides an -/// array of assembly instructions. +/// MCDisassembler - Superclass for all disassemblers. Consumes a memory region +/// and provides an array of assembly instructions. class MCDisassembler { public: /// Ternary decode status. Most backends will just use Fail and @@ -54,32 +54,34 @@ Success = 3 }; + /// Constructor - Performs initial setup for the disassembler. MCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : Ctx(Ctx), STI(STI), Symbolizer(), CommentStream(nullptr) {} virtual ~MCDisassembler(); - /// Returns the disassembly of a single instruction. + /// getInstruction - Returns the disassembly of a single instruction. /// - /// @param Instr - An MCInst to populate with the contents of the + /// @param instr - An MCInst to populate with the contents of the /// instruction. - /// @param Size - A value to populate with the size of the instruction, or + /// @param size - A value to populate with the size of the instruction, or /// the number of bytes consumed while attempting to decode /// an invalid instruction. - /// @param Region - The memory object to use as a source for machine code. - /// @param Address - The address, in the memory space of region, of the first + /// @param region - The memory object to use as a source for machine code. + /// @param address - The address, in the memory space of region, of the first /// byte of the instruction. - /// @param VStream - The stream to print warnings and diagnostic messages on. - /// @param CStream - The stream to print comments and annotations on. + /// @param vStream - The stream to print warnings and diagnostic messages on. + /// @param cStream - The stream to print comments and annotations on. /// @return - MCDisassembler::Success if the instruction is valid, /// MCDisassembler::SoftFail if the instruction was /// disassemblable but invalid, /// MCDisassembler::Fail if the instruction was invalid. - virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, - const MemoryObject &Region, - uint64_t Address, raw_ostream &VStream, - raw_ostream &CStream) const = 0; - + virtual DecodeStatus getInstruction(MCInst& instr, + uint64_t& size, + const MemoryObject ®ion, + uint64_t address, + raw_ostream &vStream, + raw_ostream &cStream) const = 0; private: MCContext &Ctx; Index: include/llvm/MC/MCParser/MCAsmLexer.h =================================================================== --- include/llvm/MC/MCParser/MCAsmLexer.h +++ include/llvm/MC/MCParser/MCAsmLexer.h @@ -18,7 +18,7 @@ namespace llvm { -/// Target independent representation for an assembler token. +/// AsmToken - Target independent representation for an assembler token. class AsmToken { public: enum TokenKind { @@ -76,24 +76,24 @@ SMLoc getEndLoc() const; SMRange getLocRange() const; - /// Get the contents of a string token (without quotes). + /// getStringContents - Get the contents of a string token (without quotes). StringRef getStringContents() const { assert(Kind == String && "This token isn't a string!"); return Str.slice(1, Str.size() - 1); } - /// Get the identifier string for the current token, which should be an - /// identifier or a string. This gets the portion of the string which should - /// be used as the identifier, e.g., it does not include the quotes on - /// strings. + /// getIdentifier - Get the identifier string for the current token, which + /// should be an identifier or a string. This gets the portion of the string + /// which should be used as the identifier, e.g., it does not include the + /// quotes on strings. StringRef getIdentifier() const { if (Kind == Identifier) return getString(); return getStringContents(); } - /// Get the string for the current token, this includes all characters (for - /// example, the quotes on strings) in the token. + /// getString - Get the string for the current token, this includes all + /// characters (for example, the quotes on strings) in the token. /// /// The returned StringRef points into the source manager's memory buffer, and /// is safe to store across calls to Lex(). @@ -114,8 +114,8 @@ } }; -/// Generic assembler lexer interface, for use by target specific assembly -/// lexers. +/// MCAsmLexer - Generic assembler lexer interface, for use by target specific +/// assembly lexers. class MCAsmLexer { /// The current token, stored in the base class for faster access. AsmToken CurTok; @@ -143,7 +143,7 @@ public: virtual ~MCAsmLexer(); - /// Consume the next token from the input stream and return it. + /// Lex - Consume the next token from the input stream and return it. /// /// The lexer will continuosly return the end-of-file token once the end of /// the main input file has been reached. @@ -153,37 +153,37 @@ virtual StringRef LexUntilEndOfStatement() = 0; - /// Get the current source location. + /// getLoc - Get the current source location. SMLoc getLoc() const; - /// Get the current (last) lexed token. - const AsmToken &getTok() const { + /// getTok - Get the current (last) lexed token. + const AsmToken &getTok() { return CurTok; } - /// Look ahead at the next token to be lexed. + /// peekTok - Look ahead at the next token to be lexed. virtual const AsmToken peekTok(bool ShouldSkipSpace = true) = 0; - /// Get the current error location + /// getErrLoc - Get the current error location const SMLoc &getErrLoc() { return ErrLoc; } - /// Get the current error string + /// getErr - Get the current error string const std::string &getErr() { return Err; } - /// Get the kind of current token. + /// getKind - Get the kind of current token. AsmToken::TokenKind getKind() const { return CurTok.getKind(); } - /// Check if the current token has kind \p K. + /// is - Check if the current token has kind \p K. bool is(AsmToken::TokenKind K) const { return CurTok.is(K); } - /// Check if the current token has kind \p K. + /// isNot - Check if the current token has kind \p K. bool isNot(AsmToken::TokenKind K) const { return CurTok.isNot(K); } - /// Set whether spaces should be ignored by the lexer + /// setSkipSpace - Set whether spaces should be ignored by the lexer void setSkipSpace(bool val) { SkipSpace = val; } bool getAllowAtInIdentifier() { return AllowAtInIdentifier; } Index: include/llvm/MC/MCParser/MCAsmParser.h =================================================================== --- include/llvm/MC/MCParser/MCAsmParser.h +++ include/llvm/MC/MCParser/MCAsmParser.h @@ -45,7 +45,7 @@ } }; -/// Generic Sema callback for assembly parser. +/// MCAsmParserSemaCallback - Generic Sema callback for assembly parser. class MCAsmParserSemaCallback { public: virtual ~MCAsmParserSemaCallback(); @@ -59,8 +59,8 @@ unsigned &Offset) = 0; }; -/// Generic assembler parser interface, for use by target specific assembly -/// parsers. +/// MCAsmParser - Generic assembler parser interface, for use by target specific +/// assembly parsers. class MCAsmParser { public: typedef bool (*DirectiveHandler)(MCAsmParserExtension*, StringRef, SMLoc); @@ -87,13 +87,10 @@ virtual SourceMgr &getSourceManager() = 0; virtual MCAsmLexer &getLexer() = 0; - const MCAsmLexer &getLexer() const { - return const_cast(this)->getLexer(); - } virtual MCContext &getContext() = 0; - /// Return the output streamer for the assembler. + /// getStreamer - Return the output streamer for the assembler. virtual MCStreamer &getStreamer() = 0; MCTargetAsmParser &getTargetParser() const { return *TargetParser; } @@ -105,49 +102,51 @@ bool getShowParsedOperands() const { return ShowParsedOperands; } void setShowParsedOperands(bool Value) { ShowParsedOperands = Value; } - /// Run the parser on the input source buffer. + /// Run - Run the parser on the input source buffer. virtual bool Run(bool NoInitialTextSection, bool NoFinalize = false) = 0; virtual void setParsingInlineAsm(bool V) = 0; virtual bool isParsingInlineAsm() = 0; - /// Parse ms-style inline assembly. - virtual bool parseMSInlineAsm( - void *AsmLoc, std::string &AsmString, unsigned &NumOutputs, - unsigned &NumInputs, SmallVectorImpl> &OpDecls, - SmallVectorImpl &Constraints, - SmallVectorImpl &Clobbers, const MCInstrInfo *MII, - const MCInstPrinter *IP, MCAsmParserSemaCallback &SI) = 0; - - /// Emit a note at the location \p L, with the message \p Msg. + /// parseMSInlineAsm - Parse ms-style inline assembly. + virtual bool parseMSInlineAsm(void *AsmLoc, std::string &AsmString, + unsigned &NumOutputs, unsigned &NumInputs, + SmallVectorImpl > &OpDecls, + SmallVectorImpl &Constraints, + SmallVectorImpl &Clobbers, + const MCInstrInfo *MII, + const MCInstPrinter *IP, + MCAsmParserSemaCallback &SI) = 0; + + /// Note - Emit a note at the location \p L, with the message \p Msg. virtual void Note(SMLoc L, const Twine &Msg, ArrayRef Ranges = None) = 0; - /// Emit a warning at the location \p L, with the message \p Msg. + /// Warning - Emit a warning at the location \p L, with the message \p Msg. /// /// \return The return value is true, if warnings are fatal. virtual bool Warning(SMLoc L, const Twine &Msg, ArrayRef Ranges = None) = 0; - /// Emit an error at the location \p L, with the message \p Msg. + /// Error - Emit an error at the location \p L, with the message \p Msg. /// /// \return The return value is always true, as an idiomatic convenience to /// clients. virtual bool Error(SMLoc L, const Twine &Msg, ArrayRef Ranges = None) = 0; - /// Get the next AsmToken in the stream, possibly handling file inclusion - /// first. + /// Lex - Get the next AsmToken in the stream, possibly handling file + /// inclusion first. virtual const AsmToken &Lex() = 0; - /// Get the current AsmToken from the stream. - const AsmToken &getTok() const; + /// getTok - Get the current AsmToken from the stream. + const AsmToken &getTok(); /// \brief Report an error at the current lexer location. bool TokError(const Twine &Msg, ArrayRef Ranges = None); - /// Parse an identifier or string (as a quoted identifier) and set \p Res to - /// the identifier contents. + /// parseIdentifier - Parse an identifier or string (as a quoted identifier) + /// and set \p Res to the identifier contents. virtual bool parseIdentifier(StringRef &Res) = 0; /// \brief Parse up to the end of statement and return the contents from the @@ -155,14 +154,15 @@ /// will be either the EndOfStatement or EOF. virtual StringRef parseStringToEndOfStatement() = 0; - /// Parse the current token as a string which may include escaped characters - /// and return the string contents. + /// parseEscapedString - Parse the current token as a string which may include + /// escaped characters and return the string contents. virtual bool parseEscapedString(std::string &Data) = 0; - /// Skip to the end of the current statement, for error recovery. + /// eatToEndOfStatement - Skip to the end of the current statement, for error + /// recovery. virtual void eatToEndOfStatement() = 0; - /// Parse an arbitrary expression. + /// parseExpression - Parse an arbitrary expression. /// /// @param Res - The value of the expression. The result is undefined /// on error. @@ -170,30 +170,31 @@ virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc) = 0; bool parseExpression(const MCExpr *&Res); - /// Parse a primary expression. + /// parsePrimaryExpr - Parse a primary expression. /// /// @param Res - The value of the expression. The result is undefined /// on error. /// @result - False on success. virtual bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) = 0; - /// Parse an arbitrary expression, assuming that an initial '(' has already - /// been consumed. + /// parseParenExpression - Parse an arbitrary expression, assuming that an + /// initial '(' has already been consumed. /// /// @param Res - The value of the expression. The result is undefined /// on error. /// @result - False on success. virtual bool parseParenExpression(const MCExpr *&Res, SMLoc &EndLoc) = 0; - /// Parse an expression which must evaluate to an absolute value. + /// parseAbsoluteExpression - Parse an expression which must evaluate to an + /// absolute value. /// /// @param Res - The value of the absolute expression. The result is undefined /// on error. /// @result - False on success. virtual bool parseAbsoluteExpression(int64_t &Res) = 0; - /// Ensure that we have a valid section set in the streamer. Otherwise, report - /// an error and switch to .text. + /// checkForValidSection - Ensure that we have a valid section set in the + /// streamer. Otherwise, report an error and switch to .text. virtual void checkForValidSection() = 0; }; Index: include/llvm/MC/MCParser/MCAsmParserExtension.h =================================================================== --- include/llvm/MC/MCParser/MCAsmParserExtension.h +++ include/llvm/MC/MCParser/MCAsmParserExtension.h @@ -52,17 +52,8 @@ /// @{ MCContext &getContext() { return getParser().getContext(); } - MCAsmLexer &getLexer() { return getParser().getLexer(); } - const MCAsmLexer &getLexer() const { - return const_cast(this)->getLexer(); - } - MCAsmParser &getParser() { return *Parser; } - const MCAsmParser &getParser() const { - return const_cast(this)->getParser(); - } - SourceMgr &getSourceManager() { return getParser().getSourceManager(); } MCStreamer &getStreamer() { return getParser().getStreamer(); } bool Warning(SMLoc L, const Twine &Msg) { Index: lib/IR/Globals.cpp =================================================================== --- lib/IR/Globals.cpp +++ lib/IR/Globals.cpp @@ -246,7 +246,6 @@ GlobalObject::copyAttributesFrom(Src); const GlobalVariable *SrcVar = cast(Src); setThreadLocalMode(SrcVar->getThreadLocalMode()); - setExternallyInitialized(SrcVar->isExternallyInitialized()); } Index: lib/MC/MCParser/MCAsmParser.cpp =================================================================== --- lib/MC/MCParser/MCAsmParser.cpp +++ lib/MC/MCParser/MCAsmParser.cpp @@ -29,7 +29,7 @@ TargetParser->Initialize(*this); } -const AsmToken &MCAsmParser::getTok() const { +const AsmToken &MCAsmParser::getTok() { return getLexer().getTok(); } Index: lib/MC/WinCOFFObjectWriter.cpp =================================================================== --- lib/MC/WinCOFFObjectWriter.cpp +++ lib/MC/WinCOFFObjectWriter.cpp @@ -694,7 +694,7 @@ // Offset of the symbol in the section int64_t a = Layout.getSymbolOffset(&B_SD); - // Offset of the relocation in the section + // Ofeset of the relocation in the section int64_t b = Layout.getFragmentOffset(Fragment) + Fixup.getOffset(); FixedValue = b - a; Index: lib/Object/ELFYAML.cpp =================================================================== --- lib/Object/ELFYAML.cpp +++ lib/Object/ELFYAML.cpp @@ -672,92 +672,6 @@ ECase(R_386_IRELATIVE) ECase(R_386_NUM) break; - case ELF::EM_AARCH64: - ECase(R_AARCH64_NONE) - ECase(R_AARCH64_ABS64) - ECase(R_AARCH64_ABS32) - ECase(R_AARCH64_ABS16) - ECase(R_AARCH64_PREL64) - ECase(R_AARCH64_PREL32) - ECase(R_AARCH64_PREL16) - ECase(R_AARCH64_MOVW_UABS_G0) - ECase(R_AARCH64_MOVW_UABS_G0_NC) - ECase(R_AARCH64_MOVW_UABS_G1) - ECase(R_AARCH64_MOVW_UABS_G1_NC) - ECase(R_AARCH64_MOVW_UABS_G2) - ECase(R_AARCH64_MOVW_UABS_G2_NC) - ECase(R_AARCH64_MOVW_UABS_G3) - ECase(R_AARCH64_MOVW_SABS_G0) - ECase(R_AARCH64_MOVW_SABS_G1) - ECase(R_AARCH64_MOVW_SABS_G2) - ECase(R_AARCH64_LD_PREL_LO19) - ECase(R_AARCH64_ADR_PREL_LO21) - ECase(R_AARCH64_ADR_PREL_PG_HI21) - ECase(R_AARCH64_ADD_ABS_LO12_NC) - ECase(R_AARCH64_LDST8_ABS_LO12_NC) - ECase(R_AARCH64_TSTBR14) - ECase(R_AARCH64_CONDBR19) - ECase(R_AARCH64_JUMP26) - ECase(R_AARCH64_CALL26) - ECase(R_AARCH64_LDST16_ABS_LO12_NC) - ECase(R_AARCH64_LDST32_ABS_LO12_NC) - ECase(R_AARCH64_LDST64_ABS_LO12_NC) - ECase(R_AARCH64_LDST128_ABS_LO12_NC) - ECase(R_AARCH64_GOTREL64) - ECase(R_AARCH64_GOTREL32) - ECase(R_AARCH64_ADR_GOT_PAGE) - ECase(R_AARCH64_LD64_GOT_LO12_NC) - ECase(R_AARCH64_TLSLD_MOVW_DTPREL_G2) - ECase(R_AARCH64_TLSLD_MOVW_DTPREL_G1) - ECase(R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC) - ECase(R_AARCH64_TLSLD_MOVW_DTPREL_G0) - ECase(R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC) - ECase(R_AARCH64_TLSLD_ADD_DTPREL_HI12) - ECase(R_AARCH64_TLSLD_ADD_DTPREL_LO12) - ECase(R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC) - ECase(R_AARCH64_TLSLD_LDST8_DTPREL_LO12) - ECase(R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC) - ECase(R_AARCH64_TLSLD_LDST16_DTPREL_LO12) - ECase(R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC) - ECase(R_AARCH64_TLSLD_LDST32_DTPREL_LO12) - ECase(R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC) - ECase(R_AARCH64_TLSLD_LDST64_DTPREL_LO12) - ECase(R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC) - ECase(R_AARCH64_TLSIE_MOVW_GOTTPREL_G1) - ECase(R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC) - ECase(R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) - ECase(R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) - ECase(R_AARCH64_TLSIE_LD_GOTTPREL_PREL19) - ECase(R_AARCH64_TLSLE_MOVW_TPREL_G2) - ECase(R_AARCH64_TLSLE_MOVW_TPREL_G1) - ECase(R_AARCH64_TLSLE_MOVW_TPREL_G1_NC) - ECase(R_AARCH64_TLSLE_MOVW_TPREL_G0) - ECase(R_AARCH64_TLSLE_MOVW_TPREL_G0_NC) - ECase(R_AARCH64_TLSLE_ADD_TPREL_HI12) - ECase(R_AARCH64_TLSLE_ADD_TPREL_LO12) - ECase(R_AARCH64_TLSLE_ADD_TPREL_LO12_NC) - ECase(R_AARCH64_TLSLE_LDST8_TPREL_LO12) - ECase(R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC) - ECase(R_AARCH64_TLSLE_LDST16_TPREL_LO12) - ECase(R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC) - ECase(R_AARCH64_TLSLE_LDST32_TPREL_LO12) - ECase(R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC) - ECase(R_AARCH64_TLSLE_LDST64_TPREL_LO12) - ECase(R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC) - ECase(R_AARCH64_TLSDESC_ADR_PAGE) - ECase(R_AARCH64_TLSDESC_LD64_LO12_NC) - ECase(R_AARCH64_TLSDESC_ADD_LO12_NC) - ECase(R_AARCH64_TLSDESC_CALL) - ECase(R_AARCH64_COPY) - ECase(R_AARCH64_GLOB_DAT) - ECase(R_AARCH64_JUMP_SLOT) - ECase(R_AARCH64_RELATIVE) - ECase(R_AARCH64_TLS_DTPREL64) - ECase(R_AARCH64_TLS_DTPMOD64) - ECase(R_AARCH64_TLS_TPREL64) - ECase(R_AARCH64_TLSDESC) - ECase(R_AARCH64_IRELATIVE) - break; default: llvm_unreachable("Unsupported architecture"); } Index: lib/Target/AArch64/AArch64FastISel.cpp =================================================================== --- lib/Target/AArch64/AArch64FastISel.cpp +++ lib/Target/AArch64/AArch64FastISel.cpp @@ -4197,14 +4197,6 @@ .addImm(AArch64::sub_32); SrcReg = ResultReg; } - // Conservatively clear all kill flags from all uses, because we are - // replacing a sign-/zero-extend instruction at IR level with a nop at MI - // level. The result of the instruction at IR level might have been - // trivially dead, which is now not longer true. - unsigned UseReg = lookUpRegForValue(I); - if (UseReg) - MRI.clearKillFlags(UseReg); - updateValueMap(I, SrcReg); return true; } Index: lib/Target/AArch64/Disassembler/AArch64Disassembler.h =================================================================== --- lib/Target/AArch64/Disassembler/AArch64Disassembler.h +++ lib/Target/AArch64/Disassembler/AArch64Disassembler.h @@ -28,10 +28,11 @@ ~AArch64Disassembler() {} + /// getInstruction - See MCDisassembler. MCDisassembler::DecodeStatus - getInstruction(MCInst &Instr, uint64_t &Size, const MemoryObject &Segion, - uint64_t Address, raw_ostream &VStream, - raw_ostream &CStream) const override; + getInstruction(MCInst &instr, uint64_t &size, const MemoryObject ®ion, + uint64_t address, raw_ostream &vStream, + raw_ostream &cStream) const override; }; } // namespace llvm Index: lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp =================================================================== --- lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -200,26 +200,26 @@ } DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, - const MemoryObject &Region, - uint64_t Address, - raw_ostream &OS, - raw_ostream &CS) const { - CommentStream = &CS; + const MemoryObject &Region, + uint64_t Address, + raw_ostream &os, + raw_ostream &cs) const { + CommentStream = &cs; - uint8_t Bytes[4]; + uint8_t bytes[4]; Size = 0; // We want to read exactly 4 bytes of data. - if (Region.readBytes(Address, 4, Bytes) == -1) + if (Region.readBytes(Address, 4, (uint8_t *)bytes) == -1) return Fail; Size = 4; // Encoded as a small-endian 32-bit word in the stream. - uint32_t Insn = - (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); + uint32_t insn = + (bytes[3] << 24) | (bytes[2] << 16) | (bytes[1] << 8) | (bytes[0] << 0); // Calling the auto-generated decoder function. - return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); + return decodeInstruction(DecoderTable32, MI, insn, Address, this, STI); } static MCSymbolizer * Index: lib/Target/ARM/Disassembler/ARMDisassembler.cpp =================================================================== --- lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -85,34 +85,42 @@ } namespace { -/// ARM disassembler for all ARM platforms. +/// ARMDisassembler - ARM disassembler for all ARM platforms. class ARMDisassembler : public MCDisassembler { public: + /// Constructor - Initializes the disassembler. + /// ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : MCDisassembler(STI, Ctx) { } - ~ARMDisassembler() {} + ~ARMDisassembler() { + } - DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, - const MemoryObject &Region, uint64_t Address, - raw_ostream &VStream, - raw_ostream &CStream) const override; + /// getInstruction - See MCDisassembler. + DecodeStatus getInstruction(MCInst &instr, uint64_t &size, + const MemoryObject ®ion, uint64_t address, + raw_ostream &vStream, + raw_ostream &cStream) const override; }; -/// Thumb disassembler for all Thumb platforms. +/// ThumbDisassembler - Thumb disassembler for all Thumb platforms. class ThumbDisassembler : public MCDisassembler { public: + /// Constructor - Initializes the disassembler. + /// ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : MCDisassembler(STI, Ctx) { } - ~ThumbDisassembler() {} + ~ThumbDisassembler() { + } - DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, - const MemoryObject &Region, uint64_t Address, - raw_ostream &VStream, - raw_ostream &CStream) const override; + /// getInstruction - See MCDisassembler. + DecodeStatus getInstruction(MCInst &instr, uint64_t &size, + const MemoryObject ®ion, uint64_t address, + raw_ostream &vStream, + raw_ostream &cStream) const override; private: mutable ITStatus ITBlock; @@ -408,100 +416,102 @@ DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, const MemoryObject &Region, - uint64_t Address, raw_ostream &OS, - raw_ostream &CS) const { - CommentStream = &CS; + uint64_t Address, + raw_ostream &os, + raw_ostream &cs) const { + CommentStream = &cs; - uint8_t Bytes[4]; + uint8_t bytes[4]; assert(!(STI.getFeatureBits() & ARM::ModeThumb) && - "Asked to disassemble an ARM instruction but Subtarget is in Thumb " - "mode!"); + "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); // We want to read exactly 4 bytes of data. - if (Region.readBytes(Address, 4, Bytes) == -1) { + if (Region.readBytes(Address, 4, bytes) == -1) { Size = 0; return MCDisassembler::Fail; } // Encoded as a small-endian 32-bit word in the stream. - uint32_t Insn = - (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); + uint32_t insn = (bytes[3] << 24) | + (bytes[2] << 16) | + (bytes[1] << 8) | + (bytes[0] << 0); // Calling the auto-generated decoder function. - DecodeStatus Result = - decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); - if (Result != MCDisassembler::Fail) { + DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn, + Address, this, STI); + if (result != MCDisassembler::Fail) { Size = 4; - return Result; + return result; } // VFP and NEON instructions, similarly, are shared between ARM // and Thumb modes. MI.clear(); - Result = decodeInstruction(DecoderTableVFP32, MI, Insn, Address, this, STI); - if (Result != MCDisassembler::Fail) { + result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI); + if (result != MCDisassembler::Fail) { Size = 4; - return Result; + return result; } MI.clear(); - Result = decodeInstruction(DecoderTableVFPV832, MI, Insn, Address, this, STI); - if (Result != MCDisassembler::Fail) { + result = decodeInstruction(DecoderTableVFPV832, MI, insn, Address, this, STI); + if (result != MCDisassembler::Fail) { Size = 4; - return Result; + return result; } MI.clear(); - Result = - decodeInstruction(DecoderTableNEONData32, MI, Insn, Address, this, STI); - if (Result != MCDisassembler::Fail) { + result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address, + this, STI); + if (result != MCDisassembler::Fail) { Size = 4; // Add a fake predicate operand, because we share these instruction // definitions with Thumb2 where these instructions are predicable. if (!DecodePredicateOperand(MI, 0xE, Address, this)) return MCDisassembler::Fail; - return Result; + return result; } MI.clear(); - Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, Insn, Address, + result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address, this, STI); - if (Result != MCDisassembler::Fail) { + if (result != MCDisassembler::Fail) { Size = 4; // Add a fake predicate operand, because we share these instruction // definitions with Thumb2 where these instructions are predicable. if (!DecodePredicateOperand(MI, 0xE, Address, this)) return MCDisassembler::Fail; - return Result; + return result; } MI.clear(); - Result = - decodeInstruction(DecoderTableNEONDup32, MI, Insn, Address, this, STI); - if (Result != MCDisassembler::Fail) { + result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address, + this, STI); + if (result != MCDisassembler::Fail) { Size = 4; // Add a fake predicate operand, because we share these instruction // definitions with Thumb2 where these instructions are predicable. if (!DecodePredicateOperand(MI, 0xE, Address, this)) return MCDisassembler::Fail; - return Result; + return result; } MI.clear(); - Result = - decodeInstruction(DecoderTablev8NEON32, MI, Insn, Address, this, STI); - if (Result != MCDisassembler::Fail) { + result = decodeInstruction(DecoderTablev8NEON32, MI, insn, Address, + this, STI); + if (result != MCDisassembler::Fail) { Size = 4; - return Result; + return result; } MI.clear(); - Result = - decodeInstruction(DecoderTablev8Crypto32, MI, Insn, Address, this, STI); - if (Result != MCDisassembler::Fail) { + result = decodeInstruction(DecoderTablev8Crypto32, MI, insn, Address, + this, STI); + if (result != MCDisassembler::Fail) { Size = 4; - return Result; + return result; } MI.clear(); @@ -675,53 +685,53 @@ DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, const MemoryObject &Region, uint64_t Address, - raw_ostream &OS, - raw_ostream &CS) const { - CommentStream = &CS; + raw_ostream &os, + raw_ostream &cs) const { + CommentStream = &cs; - uint8_t Bytes[4]; + uint8_t bytes[4]; assert((STI.getFeatureBits() & ARM::ModeThumb) && "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); // We want to read exactly 2 bytes of data. - if (Region.readBytes(Address, 2, Bytes) == -1) { + if (Region.readBytes(Address, 2, bytes) == -1) { Size = 0; return MCDisassembler::Fail; } - uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; - DecodeStatus Result = - decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); - if (Result != MCDisassembler::Fail) { + uint16_t insn16 = (bytes[1] << 8) | bytes[0]; + DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16, + Address, this, STI); + if (result != MCDisassembler::Fail) { Size = 2; - Check(Result, AddThumbPredicate(MI)); - return Result; + Check(result, AddThumbPredicate(MI)); + return result; } MI.clear(); - Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, - STI); - if (Result) { + result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16, + Address, this, STI); + if (result) { Size = 2; bool InITBlock = ITBlock.instrInITBlock(); - Check(Result, AddThumbPredicate(MI)); + Check(result, AddThumbPredicate(MI)); AddThumb1SBit(MI, InITBlock); - return Result; + return result; } MI.clear(); - Result = - decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); - if (Result != MCDisassembler::Fail) { + result = decodeInstruction(DecoderTableThumb216, MI, insn16, + Address, this, STI); + if (result != MCDisassembler::Fail) { Size = 2; // Nested IT blocks are UNPREDICTABLE. Must be checked before we add // the Thumb predicate. if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) - Result = MCDisassembler::SoftFail; + result = MCDisassembler::SoftFail; - Check(Result, AddThumbPredicate(MI)); + Check(result, AddThumbPredicate(MI)); // If we find an IT instruction, we need to parse its condition // code and mask operands so that we can apply them correctly @@ -733,115 +743,115 @@ ITBlock.setITState(Firstcond, Mask); } - return Result; + return result; } // We want to read exactly 4 bytes of data. - if (Region.readBytes(Address, 4, Bytes) == -1) { + if (Region.readBytes(Address, 4, bytes) == -1) { Size = 0; return MCDisassembler::Fail; } - uint32_t Insn32 = - (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); + uint32_t insn32 = (bytes[3] << 8) | + (bytes[2] << 0) | + (bytes[1] << 24) | + (bytes[0] << 16); MI.clear(); - Result = - decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); - if (Result != MCDisassembler::Fail) { + result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address, + this, STI); + if (result != MCDisassembler::Fail) { Size = 4; bool InITBlock = ITBlock.instrInITBlock(); - Check(Result, AddThumbPredicate(MI)); + Check(result, AddThumbPredicate(MI)); AddThumb1SBit(MI, InITBlock); - return Result; + return result; } MI.clear(); - Result = - decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); - if (Result != MCDisassembler::Fail) { + result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address, + this, STI); + if (result != MCDisassembler::Fail) { Size = 4; - Check(Result, AddThumbPredicate(MI)); - return Result; + Check(result, AddThumbPredicate(MI)); + return result; } - if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { + if (fieldFromInstruction(insn32, 28, 4) == 0xE) { MI.clear(); - Result = - decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); - if (Result != MCDisassembler::Fail) { + result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); + if (result != MCDisassembler::Fail) { Size = 4; UpdateThumbVFPPredicate(MI); - return Result; + return result; } } MI.clear(); - Result = - decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); - if (Result != MCDisassembler::Fail) { + result = decodeInstruction(DecoderTableVFPV832, MI, insn32, Address, this, STI); + if (result != MCDisassembler::Fail) { Size = 4; - return Result; + return result; } - if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { + if (fieldFromInstruction(insn32, 28, 4) == 0xE) { MI.clear(); - Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, - STI); - if (Result != MCDisassembler::Fail) { + result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, + this, STI); + if (result != MCDisassembler::Fail) { Size = 4; - Check(Result, AddThumbPredicate(MI)); - return Result; + Check(result, AddThumbPredicate(MI)); + return result; } } - if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { + if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { MI.clear(); - uint32_t NEONLdStInsn = Insn32; + uint32_t NEONLdStInsn = insn32; NEONLdStInsn &= 0xF0FFFFFF; NEONLdStInsn |= 0x04000000; - Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, + result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, Address, this, STI); - if (Result != MCDisassembler::Fail) { + if (result != MCDisassembler::Fail) { Size = 4; - Check(Result, AddThumbPredicate(MI)); - return Result; + Check(result, AddThumbPredicate(MI)); + return result; } } - if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { + if (fieldFromInstruction(insn32, 24, 4) == 0xF) { MI.clear(); - uint32_t NEONDataInsn = Insn32; + uint32_t NEONDataInsn = insn32; NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 - Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, + result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, Address, this, STI); - if (Result != MCDisassembler::Fail) { + if (result != MCDisassembler::Fail) { Size = 4; - Check(Result, AddThumbPredicate(MI)); - return Result; + Check(result, AddThumbPredicate(MI)); + return result; } MI.clear(); - uint32_t NEONCryptoInsn = Insn32; + uint32_t NEONCryptoInsn = insn32; NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 - Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, + result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, Address, this, STI); - if (Result != MCDisassembler::Fail) { + if (result != MCDisassembler::Fail) { Size = 4; - return Result; + return result; } MI.clear(); - uint32_t NEONv8Insn = Insn32; + uint32_t NEONv8Insn = insn32; NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 - Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, + result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, this, STI); - if (Result != MCDisassembler::Fail) { + if (result != MCDisassembler::Fail) { Size = 4; - return Result; + return result; } } Index: lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp =================================================================== --- lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -42,10 +42,9 @@ HexagonDisassembler(MCSubtargetInfo const &STI, MCContext &Ctx) : MCDisassembler(STI, Ctx) {} - DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, - MemoryObject const &Region, uint64_t Address, - raw_ostream &VStream, - raw_ostream &CStream) const override; + DecodeStatus getInstruction(MCInst &instr, uint64_t &size, + MemoryObject const ®ion, uint64_t address, + raw_ostream &vStream, raw_ostream &cStream) const override; }; } @@ -69,9 +68,9 @@ raw_ostream &cs) const { std::array Bytes; Size = 4; - if (Region.readBytes(Address, Bytes.size(), Bytes.data()) == -1) + if (Region.readBytes(Address, Bytes.size(), Bytes.data()) == -1) { return MCDisassembler::Fail; - + } uint32_t insn = llvm::support::endian::read(Bytes.data()); Index: lib/Target/Mips/Disassembler/MipsDisassembler.cpp =================================================================== --- lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -31,14 +31,15 @@ namespace { -/// A disasembler class for Mips. +/// MipsDisassemblerBase - a disasembler class for Mips. class MipsDisassemblerBase : public MCDisassembler { public: + /// Constructor - Initializes the disassembler. + /// MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx, - bool IsBigEndian) - : MCDisassembler(STI, Ctx), - IsN64(STI.getFeatureBits() & Mips::FeatureN64), - IsBigEndian(IsBigEndian) {} + bool bigEndian) : + MCDisassembler(STI, Ctx), + IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {} virtual ~MipsDisassemblerBase() {} @@ -47,13 +48,15 @@ private: bool IsN64; protected: - bool IsBigEndian; + bool isBigEndian; }; -/// A disasembler class for Mips32. +/// MipsDisassembler - a disasembler class for Mips32. class MipsDisassembler : public MipsDisassemblerBase { bool IsMicroMips; public: + /// Constructor - Initializes the disassembler. + /// MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian) : MipsDisassemblerBase(STI, Ctx, bigEndian) { IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips; @@ -72,23 +75,32 @@ return !hasMips32() && !hasMips3(); } - DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, - const MemoryObject &Region, uint64_t Address, - raw_ostream &VStream, - raw_ostream &CStream) const override; + /// getInstruction - See MCDisassembler. + DecodeStatus getInstruction(MCInst &instr, + uint64_t &size, + const MemoryObject ®ion, + uint64_t address, + raw_ostream &vStream, + raw_ostream &cStream) const override; }; -/// A disasembler class for Mips64. + +/// Mips64Disassembler - a disasembler class for Mips64. class Mips64Disassembler : public MipsDisassemblerBase { public: + /// Constructor - Initializes the disassembler. + /// Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian) : MipsDisassemblerBase(STI, Ctx, bigEndian) {} - DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, - const MemoryObject &Region, uint64_t Address, - raw_ostream &VStream, - raw_ostream &CStream) const override; + /// getInstruction - See MCDisassembler. + DecodeStatus getInstruction(MCInst &instr, + uint64_t &size, + const MemoryObject ®ion, + uint64_t address, + raw_ostream &vStream, + raw_ostream &cStream) const override; }; } // end anonymous namespace @@ -697,34 +709,43 @@ return MCDisassembler::Success; } -/// Read four bytes from the MemoryObject and return 32 bit word sorted -/// according to the given endianess -static DecodeStatus readInstruction32(const MemoryObject &Region, - uint64_t Address, uint64_t &Size, - uint32_t &Insn, bool IsBigEndian, + /// readInstruction - read four bytes from the MemoryObject + /// and return 32 bit word sorted according to the given endianess +static DecodeStatus readInstruction32(const MemoryObject ®ion, + uint64_t address, + uint64_t &size, + uint32_t &insn, + bool isBigEndian, bool IsMicroMips) { uint8_t Bytes[4]; // We want to read exactly 4 Bytes of data. - if (Region.readBytes(Address, 4, Bytes) == -1) { - Size = 0; + if (region.readBytes(address, 4, Bytes) == -1) { + size = 0; return MCDisassembler::Fail; } - if (IsBigEndian) { + if (isBigEndian) { // Encoded as a big-endian 32-bit word in the stream. - Insn = - (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); - } else { + insn = (Bytes[3] << 0) | + (Bytes[2] << 8) | + (Bytes[1] << 16) | + (Bytes[0] << 24); + } + else { // Encoded as a small-endian 32-bit word in the stream. // Little-endian byte ordering: // mips32r2: 4 | 3 | 2 | 1 // microMIPS: 2 | 1 | 4 | 3 if (IsMicroMips) { - Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | + insn = (Bytes[2] << 0) | + (Bytes[3] << 8) | + (Bytes[0] << 16) | (Bytes[1] << 24); } else { - Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | + insn = (Bytes[0] << 0) | + (Bytes[1] << 8) | + (Bytes[2] << 16) | (Bytes[3] << 24); } } @@ -732,22 +753,24 @@ return MCDisassembler::Success; } -DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, - const MemoryObject &Region, - uint64_t Address, - raw_ostream &VStream, - raw_ostream &CStream) const { +DecodeStatus +MipsDisassembler::getInstruction(MCInst &instr, + uint64_t &Size, + const MemoryObject &Region, + uint64_t Address, + raw_ostream &vStream, + raw_ostream &cStream) const { uint32_t Insn; - DecodeStatus Result = - readInstruction32(Region, Address, Size, Insn, IsBigEndian, IsMicroMips); + DecodeStatus Result = readInstruction32(Region, Address, Size, + Insn, isBigEndian, IsMicroMips); if (Result == MCDisassembler::Fail) return MCDisassembler::Fail; if (IsMicroMips) { DEBUG(dbgs() << "Trying MicroMips32 table (32-bit opcodes):\n"); // Calling the auto-generated decoder function. - Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, + Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) { Size = 4; @@ -759,7 +782,7 @@ if (hasCOP3()) { DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); Result = - decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); + decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) { Size = 4; return Result; @@ -768,7 +791,7 @@ if (hasMips32r6() && isGP64()) { DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); - Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, + Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) { Size = 4; @@ -778,7 +801,7 @@ if (hasMips32r6()) { DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); - Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, + Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) { Size = 4; @@ -788,8 +811,8 @@ DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); // Calling the auto-generated decoder function. - Result = - decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); + Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, + this, STI); if (Result != MCDisassembler::Fail) { Size = 4; return Result; @@ -798,28 +821,30 @@ return MCDisassembler::Fail; } -DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size, - const MemoryObject &Region, - uint64_t Address, - raw_ostream &VStream, - raw_ostream &CStream) const { +DecodeStatus +Mips64Disassembler::getInstruction(MCInst &instr, + uint64_t &Size, + const MemoryObject &Region, + uint64_t Address, + raw_ostream &vStream, + raw_ostream &cStream) const { uint32_t Insn; - DecodeStatus Result = - readInstruction32(Region, Address, Size, Insn, IsBigEndian, false); + DecodeStatus Result = readInstruction32(Region, Address, Size, + Insn, isBigEndian, false); if (Result == MCDisassembler::Fail) return MCDisassembler::Fail; // Calling the auto-generated decoder function. - Result = - decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI); + Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address, + this, STI); if (Result != MCDisassembler::Fail) { Size = 4; return Result; } // If we fail to decode in Mips64 decoder space we can try in Mips32 - Result = - decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); + Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, + this, STI); if (Result != MCDisassembler::Fail) { Size = 4; return Result; Index: lib/Target/Mips/MipsCCState.cpp =================================================================== --- lib/Target/Mips/MipsCCState.cpp +++ lib/Target/Mips/MipsCCState.cpp @@ -128,7 +128,6 @@ // aren't mapped to an original argument. if (Ins[i].Flags.isSRet()) { OriginalArgWasF128.push_back(false); - OriginalArgWasFloat.push_back(false); continue; } Index: lib/Target/Mips/MipsDelaySlotFiller.cpp =================================================================== --- lib/Target/Mips/MipsDelaySlotFiller.cpp +++ lib/Target/Mips/MipsDelaySlotFiller.cpp @@ -497,32 +497,24 @@ /// We assume there is only one delay slot per delayed instruction. bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { bool Changed = false; - bool InMicroMipsMode = TM.getSubtarget().inMicroMipsMode(); for (Iter I = MBB.begin(); I != MBB.end(); ++I) { if (!hasUnoccupiedSlot(&*I)) continue; - // For microMIPS, at the moment, do not fill delay slots of call - // instructions. - // - // TODO: Support for replacing regular call instructions with corresponding - // short delay slot instructions should be implemented. - if (!InMicroMipsMode || !I->isCall()) { - ++FilledSlots; - Changed = true; - - // Delay slot filling is disabled at -O0. - if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) { - if (searchBackward(MBB, I)) - continue; + ++FilledSlots; + Changed = true; + + // Delay slot filling is disabled at -O0. + if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) { + if (searchBackward(MBB, I)) + continue; - if (I->isTerminator()) { - if (searchSuccBBs(MBB, I)) - continue; - } else if (searchForward(MBB, I)) { + if (I->isTerminator()) { + if (searchSuccBBs(MBB, I)) continue; - } + } else if (searchForward(MBB, I)) { + continue; } } Index: lib/Target/NVPTX/CMakeLists.txt =================================================================== --- lib/Target/NVPTX/CMakeLists.txt +++ lib/Target/NVPTX/CMakeLists.txt @@ -9,28 +9,27 @@ add_public_tablegen_target(NVPTXCommonTableGen) set(NVPTXCodeGen_sources - NVPTXAllocaHoisting.cpp - NVPTXAsmPrinter.cpp - NVPTXAssignValidGlobalNames.cpp NVPTXFavorNonGenericAddrSpaces.cpp NVPTXFrameLowering.cpp - NVPTXGenericToNVVM.cpp + NVPTXInstrInfo.cpp NVPTXISelDAGToDAG.cpp NVPTXISelLowering.cpp - NVPTXImageOptimizer.cpp - NVPTXInstrInfo.cpp - NVPTXLowerAggrCopies.cpp - NVPTXLowerStructArgs.cpp - NVPTXMCExpr.cpp - NVPTXPrologEpilogPass.cpp NVPTXRegisterInfo.cpp - NVPTXReplaceImageHandles.cpp NVPTXSubtarget.cpp NVPTXTargetMachine.cpp - NVPTXTargetTransformInfo.cpp - NVPTXUtilities.cpp + NVPTXLowerAggrCopies.cpp NVPTXutil.cpp + NVPTXAllocaHoisting.cpp + NVPTXAsmPrinter.cpp + NVPTXUtilities.cpp NVVMReflect.cpp + NVPTXGenericToNVVM.cpp + NVPTXAssignValidGlobalNames.cpp + NVPTXPrologEpilogPass.cpp + NVPTXMCExpr.cpp + NVPTXReplaceImageHandles.cpp + NVPTXImageOptimizer.cpp + NVPTXLowerStructArgs.cpp ) add_llvm_target(NVPTXCodeGen ${NVPTXCodeGen_sources}) Index: lib/Target/NVPTX/NVPTX.h =================================================================== --- lib/Target/NVPTX/NVPTX.h +++ lib/Target/NVPTX/NVPTX.h @@ -59,7 +59,6 @@ llvm_unreachable("Unknown condition code"); } -ImmutablePass *createNVPTXTargetTransformInfoPass(const NVPTXTargetMachine *TM); FunctionPass * createNVPTXISelDag(NVPTXTargetMachine &TM, llvm::CodeGenOpt::Level OptLevel); ModulePass *createNVPTXAssignValidGlobalNamesPass(); Index: lib/Target/NVPTX/NVPTXTargetMachine.h =================================================================== --- lib/Target/NVPTX/NVPTXTargetMachine.h +++ lib/Target/NVPTX/NVPTXTargetMachine.h @@ -49,9 +49,6 @@ return true; } - /// \brief Register NVPTX analysis passes with a pass manager. - void addAnalysisPasses(PassManagerBase &PM) override; - }; // NVPTXTargetMachine. class NVPTXTargetMachine32 : public NVPTXTargetMachine { Index: lib/Target/NVPTX/NVPTXTargetMachine.cpp =================================================================== --- lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -121,14 +121,6 @@ return PassConfig; } -void NVPTXTargetMachine::addAnalysisPasses(PassManagerBase &PM) { - // Add first the target-independent BasicTTI pass, then our NVPTX pass. This - // allows the NVPTX pass to delegate to the target independent layer when - // appropriate. - PM.add(createBasicTargetTransformInfoPass(this)); - PM.add(createNVPTXTargetTransformInfoPass(this)); -} - void NVPTXPassConfig::addIRPasses() { // The following passes are known to not play well with virtual regs hanging // around after register allocation (which in our case, is *all* registers). Index: lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp =================================================================== --- lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp +++ /dev/null @@ -1,90 +0,0 @@ -//===-- NVPTXTargetTransformInfo.cpp - NVPTX specific TTI pass ---------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// \file -// This file implements a TargetTransformInfo analysis pass specific to the -// NVPTX target machine. It uses the target's detailed information to provide -// more precise answers to certain TTI queries, while letting the target -// independent and default TTI implementations handle the rest. -// -//===----------------------------------------------------------------------===// - -#include "NVPTXTargetMachine.h" -#include "llvm/Analysis/LoopInfo.h" -#include "llvm/Analysis/TargetTransformInfo.h" -#include "llvm/Analysis/ValueTracking.h" -#include "llvm/Support/Debug.h" -#include "llvm/Target/CostTable.h" -#include "llvm/Target/TargetLowering.h" -using namespace llvm; - -#define DEBUG_TYPE "NVPTXtti" - -// Declare the pass initialization routine locally as target-specific passes -// don't have a target-wide initialization entry point, and so we rely on the -// pass constructor initialization. -namespace llvm { -void initializeNVPTXTTIPass(PassRegistry &); -} - -namespace { - -class NVPTXTTI final : public ImmutablePass, public TargetTransformInfo { - const NVPTXTargetMachine *TM; - const NVPTXSubtarget *ST; - const NVPTXTargetLowering *TLI; - - /// Estimate the overhead of scalarizing an instruction. Insert and Extract - /// are set if the result needs to be inserted and/or extracted from vectors. - unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const; - -public: - NVPTXTTI() : ImmutablePass(ID), TM(nullptr), ST(nullptr), TLI(nullptr) { - llvm_unreachable("This pass cannot be directly constructed"); - } - - NVPTXTTI(const NVPTXTargetMachine *TM) - : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()), - TLI(TM->getSubtargetImpl()->getTargetLowering()) { - initializeNVPTXTTIPass(*PassRegistry::getPassRegistry()); - } - - void initializePass() override { pushTTIStack(this); } - - void getAnalysisUsage(AnalysisUsage &AU) const override { - TargetTransformInfo::getAnalysisUsage(AU); - } - - /// Pass identification. - static char ID; - - /// Provide necessary pointer adjustments for the two base classes. - void *getAdjustedAnalysisPointer(const void *ID) override { - if (ID == &TargetTransformInfo::ID) - return (TargetTransformInfo *)this; - return this; - } - - bool hasBranchDivergence() const override; - - /// @} -}; - -} // end anonymous namespace - -INITIALIZE_AG_PASS(NVPTXTTI, TargetTransformInfo, "NVPTXtti", - "NVPTX Target Transform Info", true, true, false) -char NVPTXTTI::ID = 0; - -ImmutablePass * -llvm::createNVPTXTargetTransformInfoPass(const NVPTXTargetMachine *TM) { - return new NVPTXTTI(TM); -} - -bool NVPTXTTI::hasBranchDivergence() const { return true; } Index: lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp =================================================================== --- lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp +++ lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp @@ -28,10 +28,11 @@ : MCDisassembler(STI, Ctx) {} virtual ~PPCDisassembler() {} - DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, - const MemoryObject &Region, uint64_t Address, - raw_ostream &VStream, - raw_ostream &CStream) const override; + // Override MCDisassembler. + DecodeStatus getInstruction(MCInst &instr, uint64_t &size, + const MemoryObject ®ion, uint64_t address, + raw_ostream &vStream, + raw_ostream &cStream) const override; }; } // end anonymous namespace @@ -322,9 +323,10 @@ #include "PPCGenDisassemblerTables.inc" DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size, - const MemoryObject &Region, - uint64_t Address, raw_ostream &OS, - raw_ostream &CS) const { + const MemoryObject &Region, + uint64_t Address, + raw_ostream &os, + raw_ostream &cs) const { // Get the four bytes of the instruction. uint8_t Bytes[4]; Size = 4; @@ -334,8 +336,10 @@ } // The instruction is big-endian encoded. - uint32_t Inst = - (Bytes[0] << 24) | (Bytes[1] << 16) | (Bytes[2] << 8) | (Bytes[3] << 0); + uint32_t Inst = (Bytes[0] << 24) | + (Bytes[1] << 16) | + (Bytes[2] << 8) | + (Bytes[3] << 0); return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI); } Index: lib/Target/Sparc/Disassembler/SparcDisassembler.cpp =================================================================== --- lib/Target/Sparc/Disassembler/SparcDisassembler.cpp +++ lib/Target/Sparc/Disassembler/SparcDisassembler.cpp @@ -27,17 +27,23 @@ namespace { -/// A disassembler class for Sparc. +/// SparcDisassembler - a disassembler class for Sparc. class SparcDisassembler : public MCDisassembler { public: - SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) - : MCDisassembler(STI, Ctx) {} + /// Constructor - Initializes the disassembler. + /// + SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : + MCDisassembler(STI, Ctx) + {} virtual ~SparcDisassembler() {} - DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, - const MemoryObject &Region, uint64_t Address, - raw_ostream &VStream, - raw_ostream &CStream) const override; + /// getInstruction - See MCDisassembler. + DecodeStatus getInstruction(MCInst &instr, + uint64_t &size, + const MemoryObject ®ion, + uint64_t address, + raw_ostream &vStream, + raw_ostream &cStream) const override; }; } @@ -207,30 +213,37 @@ #include "SparcGenDisassemblerTables.inc" -/// Read four bytes from the MemoryObject and return 32 bit word. -static DecodeStatus readInstruction32(const MemoryObject &Region, - uint64_t Address, uint64_t &Size, - uint32_t &Insn) { +/// readInstruction - read four bytes from the MemoryObject +/// and return 32 bit word. +static DecodeStatus readInstruction32(const MemoryObject ®ion, + uint64_t address, + uint64_t &size, + uint32_t &insn) { uint8_t Bytes[4]; // We want to read exactly 4 Bytes of data. - if (Region.readBytes(Address, 4, Bytes) == -1) { - Size = 0; + if (region.readBytes(address, 4, Bytes) == -1) { + size = 0; return MCDisassembler::Fail; } // Encoded as a big-endian 32-bit word in the stream. - Insn = - (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); + insn = (Bytes[3] << 0) | + (Bytes[2] << 8) | + (Bytes[1] << 16) | + (Bytes[0] << 24); return MCDisassembler::Success; } -DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, - const MemoryObject &Region, - uint64_t Address, - raw_ostream &VStream, - raw_ostream &CStream) const { + +DecodeStatus +SparcDisassembler::getInstruction(MCInst &instr, + uint64_t &Size, + const MemoryObject &Region, + uint64_t Address, + raw_ostream &vStream, + raw_ostream &cStream) const { uint32_t Insn; DecodeStatus Result = readInstruction32(Region, Address, Size, Insn); @@ -239,8 +252,8 @@ // Calling the auto-generated decoder function. - Result = - decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI); + Result = decodeInstruction(DecoderTableSparc32, instr, Insn, Address, + this, STI); if (Result != MCDisassembler::Fail) { Size = 4; Index: lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp =================================================================== --- lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp +++ lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp @@ -28,10 +28,11 @@ : MCDisassembler(STI, Ctx) {} virtual ~SystemZDisassembler() {} - DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, - const MemoryObject &Region, uint64_t Address, - raw_ostream &VStream, - raw_ostream &CStream) const override; + // Override MCDisassembler. + DecodeStatus getInstruction(MCInst &instr, uint64_t &size, + const MemoryObject ®ion, uint64_t address, + raw_ostream &vStream, + raw_ostream &cStream) const override; }; } // end anonymous namespace @@ -289,8 +290,8 @@ DecodeStatus SystemZDisassembler::getInstruction(MCInst &MI, uint64_t &Size, const MemoryObject &Region, uint64_t Address, - raw_ostream &OS, - raw_ostream &CS) const { + raw_ostream &os, + raw_ostream &cs) const { // Get the first two bytes of the instruction. uint8_t Bytes[6]; Size = 0; Index: lib/Target/X86/Disassembler/X86Disassembler.h =================================================================== --- lib/Target/X86/Disassembler/X86Disassembler.h +++ lib/Target/X86/Disassembler/X86Disassembler.h @@ -87,15 +87,19 @@ namespace X86Disassembler { -/// Generic disassembler for all X86 platforms. All each platform class should -/// have to do is subclass the constructor, and provide a different -/// disassemblerMode value. +/// X86GenericDisassembler - Generic disassembler for all X86 platforms. +/// All each platform class should have to do is subclass the constructor, and +/// provide a different disassemblerMode value. class X86GenericDisassembler : public MCDisassembler { std::unique_ptr MII; public: + /// Constructor - Initializes the disassembler. + /// X86GenericDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, std::unique_ptr MII); public: + + /// getInstruction - See MCDisassembler. DecodeStatus getInstruction(MCInst &instr, uint64_t &size, const MemoryObject ®ion, uint64_t address, raw_ostream &vStream, Index: lib/Target/X86/Disassembler/X86Disassembler.cpp =================================================================== --- lib/Target/X86/Disassembler/X86Disassembler.cpp +++ lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -97,15 +97,16 @@ } } -/// A callback function that wraps the readByte method from MemoryObject. +/// regionReader - a callback function that wraps the readByte method from +/// MemoryObject. /// -/// @param Arg - The generic callback parameter. In this case, this should +/// @param arg - The generic callback parameter. In this case, this should /// be a pointer to a MemoryObject. -/// @param Byte - A pointer to the byte to be read. -/// @param Address - The address to be read. -static int regionReader(const void *Arg, uint8_t *Byte, uint64_t Address) { - const MemoryObject *Region = static_cast(Arg); - return Region->readByte(Address, Byte); +/// @param byte - A pointer to the byte to be read. +/// @param address - The address to be read. +static int regionReader(const void* arg, uint8_t* byte, uint64_t address) { + const MemoryObject* region = static_cast(arg); + return region->readByte(address, byte); } /// logger - a callback function that wraps the operator<< method from @@ -126,27 +127,38 @@ // Public interface for the disassembler // -MCDisassembler::DecodeStatus X86GenericDisassembler::getInstruction( - MCInst &Instr, uint64_t &Size, const MemoryObject &Region, uint64_t Address, - raw_ostream &VStream, raw_ostream &CStream) const { - CommentStream = &CStream; +MCDisassembler::DecodeStatus +X86GenericDisassembler::getInstruction(MCInst &instr, + uint64_t &size, + const MemoryObject ®ion, + uint64_t address, + raw_ostream &vStream, + raw_ostream &cStream) const { + CommentStream = &cStream; - InternalInstruction InternalInstr; + InternalInstruction internalInstr; - dlog_t LoggerFn = logger; - if (&VStream == &nulls()) - LoggerFn = nullptr; // Disable logging completely if it's going to nulls(). - - int Ret = decodeInstruction(&InternalInstr, regionReader, - (const void *)&Region, LoggerFn, (void *)&VStream, - (const void *)MII.get(), Address, fMode); - - if (Ret) { - Size = InternalInstr.readerCursor - Address; + dlog_t loggerFn = logger; + if (&vStream == &nulls()) + loggerFn = nullptr; // Disable logging completely if it's going to nulls(). + + int ret = decodeInstruction(&internalInstr, + regionReader, + (const void*)®ion, + loggerFn, + (void*)&vStream, + (const void*)MII.get(), + address, + fMode); + + if (ret) { + size = internalInstr.readerCursor - address; return Fail; - } else { - Size = InternalInstr.length; - return (!translateInstruction(Instr, InternalInstr, this)) ? Success : Fail; + } + else { + size = internalInstr.length; + return (!translateInstruction(instr, internalInstr, this)) ? + Success : Fail; } } Index: lib/Target/X86/X86ISelLowering.cpp =================================================================== --- lib/Target/X86/X86ISelLowering.cpp +++ lib/Target/X86/X86ISelLowering.cpp @@ -956,7 +956,6 @@ setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); setOperationAction(ISD::SELECT, MVT::v4f32, Custom); - setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom); } if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) { @@ -1294,10 +1293,6 @@ setOperationAction(ISD::VSELECT, MVT::v16i16, Custom); setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); - - // The custom lowering for UINT_TO_FP for v8i32 becomes interesting - // when we have a 256bit-wide blend with immediate. - setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom); } else { setOperationAction(ISD::ADD, MVT::v4i64, Custom); setOperationAction(ISD::ADD, MVT::v8i32, Custom); @@ -13312,130 +13307,19 @@ return Sub; } -static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG, - const X86Subtarget &Subtarget) { - // The algorithm is the following: - // #ifdef __SSE4_1__ - // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa); - // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16), - // (uint4) 0x53000000, 0xaa); - // #else - // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000; - // uint4 hi = (v >> 16) | (uint4) 0x53000000; - // #endif - // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f); - // return (float4) lo + fhi; - - SDLoc DL(Op); - SDValue V = Op->getOperand(0); - EVT VecIntVT = V.getValueType(); - bool Is128 = VecIntVT == MVT::v4i32; - EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32; - unsigned NumElts = VecIntVT.getVectorNumElements(); - assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) && - "Unsupported custom type"); - assert(NumElts <= 8 && "The size of the constant array must be fixed"); - - // In the #idef/#else code, we have in common: - // - The vector of constants: - // -- 0x4b000000 - // -- 0x53000000 - // - A shift: - // -- v >> 16 - - // Create the splat vector for 0x4b000000. - SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32); - SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow, - CstLow, CstLow, CstLow, CstLow}; - SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, - makeArrayRef(&CstLowArray[0], NumElts)); - // Create the splat vector for 0x53000000. - SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32); - SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh, - CstHigh, CstHigh, CstHigh, CstHigh}; - SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, - makeArrayRef(&CstHighArray[0], NumElts)); - - // Create the right shift. - SDValue CstShift = DAG.getConstant(16, MVT::i32); - SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift, - CstShift, CstShift, CstShift, CstShift}; - SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, - makeArrayRef(&CstShiftArray[0], NumElts)); - SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift); - - SDValue Low, High; - if (Subtarget.hasSSE41()) { - EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16; - // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa); - SDValue VecCstLowBitcast = - DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow); - SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V); - // Low will be bitcasted right away, so do not bother bitcasting back to its - // original type. - Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast, - VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32)); - // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16), - // (uint4) 0x53000000, 0xaa); - SDValue VecCstHighBitcast = - DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh); - SDValue VecShiftBitcast = - DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift); - // High will be bitcasted right away, so do not bother bitcasting back to - // its original type. - High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast, - VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32)); - } else { - SDValue CstMask = DAG.getConstant(0xffff, MVT::i32); - SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask, - CstMask, CstMask, CstMask); - // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000; - SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask); - Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow); - - // uint4 hi = (v >> 16) | (uint4) 0x53000000; - High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh); - } - - // Create the vector constant for -(0x1.0p39f + 0x1.0p23f). - SDValue CstFAdd = DAG.getConstantFP( - APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32); - SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd, - CstFAdd, CstFAdd, CstFAdd, CstFAdd}; - SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT, - makeArrayRef(&CstFAddArray[0], NumElts)); - - // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f); - SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High); - SDValue FHigh = - DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd); - // return (float4) lo + fhi; - SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low); - return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh); -} - SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const { SDValue N0 = Op.getOperand(0); MVT SVT = N0.getSimpleValueType(); SDLoc dl(Op); - switch (SVT.SimpleTy) { - default: - llvm_unreachable("Custom UINT_TO_FP is not supported!"); - case MVT::v4i8: - case MVT::v4i16: - case MVT::v8i8: - case MVT::v8i16: { - MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements()); - return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), - DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0)); - } - case MVT::v4i32: - case MVT::v8i32: - return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget); - } - llvm_unreachable(nullptr); + assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 || + SVT == MVT::v8i8 || SVT == MVT::v8i16) && + "Custom UINT_TO_FP is not supported!"); + + MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements()); + return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), + DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0)); } SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, Index: lib/Target/X86/X86TargetTransformInfo.cpp =================================================================== --- lib/Target/X86/X86TargetTransformInfo.cpp +++ lib/Target/X86/X86TargetTransformInfo.cpp @@ -578,7 +578,7 @@ { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, // There are faster sequences for float conversions. { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, - { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 }, + { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 }, { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, @@ -661,8 +661,6 @@ { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 }, { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, - - { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 }, }; static const TypeConversionCostTblEntry Index: lib/Target/XCore/Disassembler/XCoreDisassembler.cpp =================================================================== --- lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -36,39 +36,44 @@ XCoreDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : MCDisassembler(STI, Ctx) {} - DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, - const MemoryObject &Region, uint64_t Address, - raw_ostream &VStream, - raw_ostream &CStream) const override; + /// \brief See MCDisassembler. + DecodeStatus getInstruction(MCInst &instr, uint64_t &size, + const MemoryObject ®ion, uint64_t address, + raw_ostream &vStream, + raw_ostream &cStream) const override; }; } -static bool readInstruction16(const MemoryObject &Region, uint64_t Address, - uint64_t &Size, uint16_t &Insn) { +static bool readInstruction16(const MemoryObject ®ion, + uint64_t address, + uint64_t &size, + uint16_t &insn) { uint8_t Bytes[4]; // We want to read exactly 2 Bytes of data. - if (Region.readBytes(Address, 2, Bytes) == -1) { - Size = 0; + if (region.readBytes(address, 2, Bytes) == -1) { + size = 0; return false; } // Encoded as a little-endian 16-bit word in the stream. - Insn = (Bytes[0] << 0) | (Bytes[1] << 8); + insn = (Bytes[0] << 0) | (Bytes[1] << 8); return true; } -static bool readInstruction32(const MemoryObject &Region, uint64_t Address, - uint64_t &Size, uint32_t &Insn) { +static bool readInstruction32(const MemoryObject ®ion, + uint64_t address, + uint64_t &size, + uint32_t &insn) { uint8_t Bytes[4]; // We want to read exactly 4 Bytes of data. - if (Region.readBytes(Address, 4, Bytes) == -1) { - Size = 0; + if (region.readBytes(address, 4, Bytes) == -1) { + size = 0; return false; } // Encoded as a little-endian 32-bit word in the stream. - Insn = - (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | (Bytes[3] << 24); + insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | + (Bytes[3] << 24); return true; } @@ -740,9 +745,13 @@ return S; } -MCDisassembler::DecodeStatus XCoreDisassembler::getInstruction( - MCInst &instr, uint64_t &Size, const MemoryObject &Region, uint64_t Address, - raw_ostream &vStream, raw_ostream &cStream) const { +MCDisassembler::DecodeStatus +XCoreDisassembler::getInstruction(MCInst &instr, + uint64_t &Size, + const MemoryObject &Region, + uint64_t Address, + raw_ostream &vStream, + raw_ostream &cStream) const { uint16_t insn16; if (!readInstruction16(Region, Address, Size, insn16)) { Index: lib/Transforms/Utils/LowerSwitch.cpp =================================================================== --- lib/Transforms/Utils/LowerSwitch.cpp +++ lib/Transforms/Utils/LowerSwitch.cpp @@ -131,24 +131,17 @@ return O << "]"; } -/// \brief Update the first occurrence of the "switch statement" BB in the PHI -/// node with the "new" BB. The other occurrences will be updated by subsequent -/// calls to this function. -/// -/// Switch statements may have more than one incoming edge into the same BB if -/// they all have the same value. When the switch statement is converted these -/// incoming edges are now coming from multiple BBs. -static void fixPhis(BasicBlock *SuccBB, BasicBlock *OrigBB, BasicBlock *NewBB) { - for (BasicBlock::iterator I = SuccBB->begin(), E = SuccBB->getFirstNonPHI(); +static void fixPhis(BasicBlock *Succ, + BasicBlock *OrigBlock, + BasicBlock *NewNode) { + for (BasicBlock::iterator I = Succ->begin(), + E = Succ->getFirstNonPHI(); I != E; ++I) { PHINode *PN = cast(I); - // Only update the first occurence. - for (unsigned Idx = 0, E = PN->getNumIncomingValues(); Idx != E; ++Idx) { - if (PN->getIncomingBlock(Idx) == OrigBB) { - PN->setIncomingBlock(Idx, NewBB); - break; - } + for (unsigned I = 0, E = PN->getNumIncomingValues(); I != E; ++I) { + if (PN->getIncomingBlock(I) == OrigBlock) + PN->setIncomingBlock(I, NewNode); } } } Index: lib/Transforms/Utils/SymbolRewriter.cpp =================================================================== --- lib/Transforms/Utils/SymbolRewriter.cpp +++ lib/Transforms/Utils/SymbolRewriter.cpp @@ -515,7 +515,7 @@ } INITIALIZE_PASS(RewriteSymbols, "rewrite-symbols", "Rewrite Symbols", false, - false) + false); ModulePass *llvm::createRewriteSymbolsPass() { return new RewriteSymbols(); } Index: test/Analysis/CostModel/X86/cast.ll =================================================================== --- test/Analysis/CostModel/X86/cast.ll +++ test/Analysis/CostModel/X86/cast.ll @@ -225,9 +225,7 @@ ; CHECK: cost of 5 {{.*}} uitofp %C1 = uitofp <8 x i16> %c to <8 x float> - ; CHECK-AVX2: cost of 8 {{.*}} uitofp - ; CHECK-AVX512: cost of 8 {{.*}} uitofp - ; CHECK-AVX: cost of 9 {{.*}} uitofp + ; CHECK: cost of 9 {{.*}} uitofp %D1 = uitofp <8 x i32> %d to <8 x float> ret void } Index: test/Analysis/CostModel/X86/uitofp.ll =================================================================== --- test/Analysis/CostModel/X86/uitofp.ll +++ test/Analysis/CostModel/X86/uitofp.ll @@ -235,7 +235,7 @@ define <4 x float> @uitofpv4i8v4float(<4 x i8> %a) { ; SSE2: uitofpv4i8v4float - ; SSE2: cost of 8 {{.*}} uitofp + ; SSE2: cost of 15 {{.*}} uitofp %1 = uitofp <4 x i8> %a to <4 x float> ret <4 x float> %1 } @@ -270,7 +270,7 @@ define <4 x float> @uitofpv4i16v4float(<4 x i16> %a) { ; SSE2: uitofpv4i16v4float - ; SSE2: cost of 8 {{.*}} uitofp + ; SSE2: cost of 15 {{.*}} uitofp %1 = uitofp <4 x i16> %a to <4 x float> ret <4 x float> %1 } @@ -305,28 +305,28 @@ define <4 x float> @uitofpv4i32v4float(<4 x i32> %a) { ; SSE2: uitofpv4i32v4float - ; SSE2: cost of 8 {{.*}} uitofp + ; SSE2: cost of 15 {{.*}} uitofp %1 = uitofp <4 x i32> %a to <4 x float> ret <4 x float> %1 } define <8 x float> @uitofpv8i32v8float(<8 x i32> %a) { ; SSE2: uitofpv8i32v8float - ; SSE2: cost of 16 {{.*}} uitofp + ; SSE2: cost of 30 {{.*}} uitofp %1 = uitofp <8 x i32> %a to <8 x float> ret <8 x float> %1 } define <16 x float> @uitofpv16i32v16float(<16 x i32> %a) { ; SSE2: uitofpv16i32v16float - ; SSE2: cost of 32 {{.*}} uitofp + ; SSE2: cost of 60 {{.*}} uitofp %1 = uitofp <16 x i32> %a to <16 x float> ret <16 x float> %1 } define <32 x float> @uitofpv32i32v32float(<32 x i32> %a) { ; SSE2: uitofpv32i32v32float - ; SSE2: cost of 64 {{.*}} uitofp + ; SSE2: cost of 120 {{.*}} uitofp %1 = uitofp <32 x i32> %a to <32 x float> ret <32 x float> %1 } Index: test/CodeGen/AArch64/fast-isel-int-ext4.ll =================================================================== --- test/CodeGen/AArch64/fast-isel-int-ext4.ll +++ /dev/null @@ -1,20 +0,0 @@ -; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s - -define i32 @kill_flag(i16 signext %a) { -; CHECK-LABEL: kill_flag -entry: - %0 = sext i16 %a to i32 - br label %bb1 - -bb1: - %1 = icmp slt i32 undef, %0 - br i1 %1, label %loop, label %exit - -loop: - %2 = sext i16 %a to i32 - %3 = icmp slt i32 undef, %2 - br i1 %3, label %bb1, label %exit - -exit: - ret i32 0 -} Index: test/CodeGen/Mips/cconv/return-struct.ll =================================================================== --- test/CodeGen/Mips/cconv/return-struct.ll +++ test/CodeGen/Mips/cconv/return-struct.ll @@ -15,8 +15,6 @@ @struct_byte = global {i8} zeroinitializer @struct_2byte = global {i8,i8} zeroinitializer @struct_3xi16 = global {[3 x i16]} zeroinitializer -@struct_6xi32 = global {[6 x i32]} zeroinitializer -@struct_128xi16 = global {[128 x i16]} zeroinitializer declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) @@ -138,95 +136,3 @@ ; N64-BE-DAG: lhu [[R3:\$[0-9]+]], 4([[PTR]]) ; N64-BE-DAG: or [[R4:\$[0-9]+]], [[R3]], [[R2]] ; N32-BE-DAG: dsll $2, [[R4]], 16 - -; Ensure that large structures (>128-bit) are returned indirectly. -; We pick an extremely large structure so we don't have to match inlined memcpy's. -define void @ret_struct_128xi16({[128 x i16]}* sret %returnval) { -entry: - %0 = bitcast {[128 x i16]}* %returnval to i8* - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast ({[128 x i16]}* @struct_128xi16 to i8*), i64 256, i32 2, i1 false) - ret void -} - -; ALL-LABEL: ret_struct_128xi16: - -; sret pointer is already in $4 -; O32-DAG: lui [[PTR:\$[0-9]+]], %hi(struct_128xi16) -; O32-DAG: addiu $5, [[PTR]], %lo(struct_128xi16) -; O32: jal memcpy - -; sret pointer is already in $4 -; N32-DAG: lui [[PTR_HI:\$[0-9]+]], %hi(struct_128xi16) -; N32-DAG: addiu [[PTR:\$[0-9]+]], [[PTR_HI]], %lo(struct_128xi16) -; FIXME: This signext isn't necessary. Like integers, pointers are -; but unlike integers, pointers cannot have the signext attribute. -; N32-DAG: sll $5, [[PTR]], 0 -; N32: jal memcpy - -; sret pointer is already in $4 -; N64-DAG: ld $5, %got_disp(struct_128xi16)( -; N64-DAG: ld $25, %call16(memcpy)( -; N64: jalr $25 - -; Ensure that large structures (>128-bit) are returned indirectly. -; This will generate inlined memcpy's anyway so pick the smallest large -; structure -; This time we let the backend lower the sret argument. -define {[6 x i32]} @ret_struct_6xi32() { -entry: - %0 = load volatile {[6 x i32]}* @struct_6xi32, align 2 - ret {[6 x i32]} %0 -} - -; ALL-LABEL: ret_struct_6xi32: - -; sret pointer is already in $4 -; O32-DAG: lui [[PTR_HI:\$[0-9]+]], %hi(struct_6xi32) -; O32-DAG: addiu [[PTR:\$[0-9]+]], [[PTR_HI]], %lo(struct_6xi32) -; O32-DAG: lw [[T0:\$[0-9]+]], %lo(struct_6xi32)([[PTR]]) -; O32-DAG: lw [[T1:\$[0-9]+]], 4([[PTR]]) -; O32-DAG: lw [[T2:\$[0-9]+]], 8([[PTR]]) -; O32-DAG: lw [[T3:\$[0-9]+]], 12([[PTR]]) -; O32-DAG: lw [[T4:\$[0-9]+]], 16([[PTR]]) -; O32-DAG: lw [[T5:\$[0-9]+]], 20([[PTR]]) -; O32-DAG: sw [[T0]], 0($4) -; O32-DAG: sw [[T1]], 4($4) -; O32-DAG: sw [[T2]], 8($4) -; O32-DAG: sw [[T3]], 12($4) -; O32-DAG: sw [[T4]], 16($4) -; O32-DAG: sw [[T5]], 20($4) - -; FIXME: This signext isn't necessary. Like integers, pointers are -; but unlike integers, pointers cannot have the signext attribute. -; In this case we don't have anywhere to put the signext either since -; the sret argument is invented by the backend. -; N32-DAG: sll [[RET_PTR:\$[0-9]+]], $4, 0 -; N32-DAG: lui [[PTR_HI:\$[0-9]+]], %hi(struct_6xi32) -; N32-DAG: addiu [[PTR:\$[0-9]+]], [[PTR_HI]], %lo(struct_6xi32) -; N32-DAG: lw [[T0:\$[0-9]+]], %lo(struct_6xi32)([[PTR]]) -; N32-DAG: lw [[T1:\$[0-9]+]], 4([[PTR]]) -; N32-DAG: lw [[T2:\$[0-9]+]], 8([[PTR]]) -; N32-DAG: lw [[T3:\$[0-9]+]], 12([[PTR]]) -; N32-DAG: lw [[T4:\$[0-9]+]], 16([[PTR]]) -; N32-DAG: lw [[T5:\$[0-9]+]], 20([[PTR]]) -; N32-DAG: sw [[T0]], 0([[RET_PTR]]) -; N32-DAG: sw [[T1]], 4([[RET_PTR]]) -; N32-DAG: sw [[T2]], 8([[RET_PTR]]) -; N32-DAG: sw [[T3]], 12([[RET_PTR]]) -; N32-DAG: sw [[T4]], 16([[RET_PTR]]) -; N32-DAG: sw [[T5]], 20([[RET_PTR]]) - -; sret pointer is already in $4 -; N64-DAG: ld [[PTR:\$[0-9]+]], %got_disp(struct_6xi32)( -; N64-DAG: lw [[T0:\$[0-9]+]], 0([[PTR]]) -; N64-DAG: lw [[T1:\$[0-9]+]], 4([[PTR]]) -; N64-DAG: lw [[T2:\$[0-9]+]], 8([[PTR]]) -; N64-DAG: lw [[T3:\$[0-9]+]], 12([[PTR]]) -; N64-DAG: lw [[T4:\$[0-9]+]], 16([[PTR]]) -; N64-DAG: lw [[T5:\$[0-9]+]], 20([[PTR]]) -; N64-DAG: sw [[T0]], 0($4) -; N64-DAG: sw [[T1]], 4($4) -; N64-DAG: sw [[T2]], 8($4) -; N64-DAG: sw [[T3]], 12($4) -; N64-DAG: sw [[T4]], 16($4) -; N64-DAG: sw [[T5]], 20($4) Index: test/CodeGen/Mips/micromips-delay-slot.ll =================================================================== --- test/CodeGen/Mips/micromips-delay-slot.ll +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ -; RUN: -relocation-model=pic -O3 < %s | FileCheck %s - -; Function Attrs: nounwind uwtable -define i32 @foo(i32 %a) #0 { -entry: - %a.addr = alloca i32, align 4 - store i32 %a, i32* %a.addr, align 4 - %0 = load i32* %a.addr, align 4 - %shl = shl i32 %0, 2 - %call = call i32 @bar(i32 %shl) - ret i32 %call -} - -declare i32 @bar(i32) #1 - -; CHECK: nop - Index: test/CodeGen/X86/2009-02-26-MachineLICMBug.ll =================================================================== --- test/CodeGen/X86/2009-02-26-MachineLICMBug.ll +++ test/CodeGen/X86/2009-02-26-MachineLICMBug.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse4.1 -mcpu=penryn -stats 2>&1 | grep "7 machine-licm" +; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse4.1 -mcpu=penryn -stats 2>&1 | grep "4 machine-licm" ; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse4.1 -mcpu=penryn | FileCheck %s ; rdar://6627786 ; rdar://7792037 Index: test/CodeGen/X86/vec_uint_to_fp.ll =================================================================== --- test/CodeGen/X86/vec_uint_to_fp.ll +++ test/CodeGen/X86/vec_uint_to_fp.ll @@ -1,156 +1,11 @@ -; RUN: llc < %s -mtriple=x86_64-apple-macosx | FileCheck --check-prefix=CHECK --check-prefix=SSE --check-prefix=CST %s -; RUN: llc < %s -mtriple=x86_64-apple-macosx -mattr=+sse4.1 | FileCheck --check-prefix=CHECK --check-prefix=SSE41 --check-prefix=CST %s -; RUN: llc < %s -mtriple=x86_64-apple-macosx -mattr=+avx | FileCheck --check-prefix=CHECK --check-prefix=AVX --check-prefix=CST %s -; RUN: llc < %s -mtriple=x86_64-apple-macosx -mattr=+avx2 | FileCheck --check-prefix=CHECK --check-prefix=AVX2 %s - -; Check that the constant used in the vectors are the right ones. -; SSE: [[MASKCSTADDR:LCPI0_[0-9]+]]: -; SSE-NEXT: .long 65535 ## 0xffff -; SSE-NEXT: .long 65535 ## 0xffff -; SSE-NEXT: .long 65535 ## 0xffff -; SSE-NEXT: .long 65535 ## 0xffff - -; CST: [[LOWCSTADDR:LCPI0_[0-9]+]]: -; CST-NEXT: .long 1258291200 ## 0x4b000000 -; CST-NEXT: .long 1258291200 ## 0x4b000000 -; CST-NEXT: .long 1258291200 ## 0x4b000000 -; CST-NEXT: .long 1258291200 ## 0x4b000000 - -; CST: [[HIGHCSTADDR:LCPI0_[0-9]+]]: -; CST-NEXT: .long 1392508928 ## 0x53000000 -; CST-NEXT: .long 1392508928 ## 0x53000000 -; CST-NEXT: .long 1392508928 ## 0x53000000 -; CST-NEXT: .long 1392508928 ## 0x53000000 - -; CST: [[MAGICCSTADDR:LCPI0_[0-9]+]]: -; CST-NEXT: .long 3539992704 ## float -5.497642e+11 -; CST-NEXT: .long 3539992704 ## float -5.497642e+11 -; CST-NEXT: .long 3539992704 ## float -5.497642e+11 -; CST-NEXT: .long 3539992704 ## float -5.497642e+11 - -; AVX2: [[LOWCSTADDR:LCPI0_[0-9]+]]: -; AVX2-NEXT: .long 1258291200 ## 0x4b000000 - -; AVX2: [[HIGHCSTADDR:LCPI0_[0-9]+]]: -; AVX2-NEXT: .long 1392508928 ## 0x53000000 - -; AVX2: [[MAGICCSTADDR:LCPI0_[0-9]+]]: -; AVX2-NEXT: .long 3539992704 ## float -5.49764202E+11 +; RUN: llc < %s -march=x86 -mcpu=corei7-avx | FileCheck %s +; Test that we are not lowering uinttofp to scalars define <4 x float> @test1(<4 x i32> %A) nounwind { ; CHECK-LABEL: test1: -; -; SSE: movdqa [[MASKCSTADDR]](%rip), [[MASK:%xmm[0-9]+]] -; SSE-NEXT: pand %xmm0, [[MASK]] -; After this instruction, MASK will have the value of the low parts -; of the vector. -; SSE-NEXT: por [[LOWCSTADDR]](%rip), [[MASK]] -; SSE-NEXT: psrld $16, %xmm0 -; SSE-NEXT: por [[HIGHCSTADDR]](%rip), %xmm0 -; SSE-NEXT: addps [[MAGICCSTADDR]](%rip), %xmm0 -; SSE-NEXT: addps [[MASK]], %xmm0 -; SSE-NEXT: retq -; -; Currently we commute the arguments of the first blend, but this could be -; improved to match the lowering of the second blend. -; SSE41: movdqa [[LOWCSTADDR]](%rip), [[LOWVEC:%xmm[0-9]+]] -; SSE41-NEXT: pblendw $85, %xmm0, [[LOWVEC]] -; SSE41-NEXT: psrld $16, %xmm0 -; SSE41-NEXT: pblendw $170, [[HIGHCSTADDR]](%rip), %xmm0 -; SSE41-NEXT: addps [[MAGICCSTADDR]](%rip), %xmm0 -; SSE41-NEXT: addps [[LOWVEC]], %xmm0 -; SSE41-NEXT: retq -; -; AVX: vpblendw $170, [[LOWCSTADDR]](%rip), %xmm0, [[LOWVEC:%xmm[0-9]+]] -; AVX-NEXT: vpsrld $16, %xmm0, [[SHIFTVEC:%xmm[0-9]+]] -; AVX-NEXT: vpblendw $170, [[HIGHCSTADDR]](%rip), [[SHIFTVEC]], [[HIGHVEC:%xmm[0-9]+]] -; AVX-NEXT: vaddps [[MAGICCSTADDR]](%rip), [[HIGHVEC]], [[TMP:%xmm[0-9]+]] -; AVX-NEXT: vaddps [[TMP]], [[LOWVEC]], %xmm0 -; AVX-NEXT: retq -; -; The lowering for AVX2 is a bit messy, because we select broadcast -; instructions, instead of folding the constant loads. -; AVX2: vpbroadcastd [[LOWCSTADDR]](%rip), [[LOWCST:%xmm[0-9]+]] -; AVX2-NEXT: vpblendw $170, [[LOWCST]], %xmm0, [[LOWVEC:%xmm[0-9]+]] -; AVX2-NEXT: vpsrld $16, %xmm0, [[SHIFTVEC:%xmm[0-9]+]] -; AVX2-NEXT: vpbroadcastd [[HIGHCSTADDR]](%rip), [[HIGHCST:%xmm[0-9]+]] -; AVX2-NEXT: vpblendw $170, [[HIGHCST]], [[SHIFTVEC]], [[HIGHVEC:%xmm[0-9]+]] -; AVX2-NEXT: vbroadcastss [[MAGICCSTADDR]](%rip), [[MAGICCST:%xmm[0-9]+]] -; AVX2-NEXT: vaddps [[MAGICCST]], [[HIGHVEC]], [[TMP:%xmm[0-9]+]] -; AVX2-NEXT: vaddps [[TMP]], [[LOWVEC]], %xmm0 -; AVX2-NEXT: retq +; CHECK-NOT: cvtsd2ss +; CHECK: ret %C = uitofp <4 x i32> %A to <4 x float> ret <4 x float> %C } -; Match the AVX2 constants used in the next function -; AVX2: [[LOWCSTADDR:LCPI1_[0-9]+]]: -; AVX2-NEXT: .long 1258291200 ## 0x4b000000 - -; AVX2: [[HIGHCSTADDR:LCPI1_[0-9]+]]: -; AVX2-NEXT: .long 1392508928 ## 0x53000000 - -; AVX2: [[MAGICCSTADDR:LCPI1_[0-9]+]]: -; AVX2-NEXT: .long 3539992704 ## float -5.49764202E+11 - -define <8 x float> @test2(<8 x i32> %A) nounwind { -; CHECK-LABEL: test2: -; Legalization will break the thing is 2 x <4 x i32> on anthing prior AVX. -; The constant used for in the vector instruction are shared between the -; two sequences of instructions. -; -; SSE: movdqa {{.*#+}} [[MASK:xmm[0-9]+]] = [65535,65535,65535,65535] -; SSE-NEXT: movdqa %xmm0, [[VECLOW:%xmm[0-9]+]] -; SSE-NEXT: pand %[[MASK]], [[VECLOW]] -; SSE-NEXT: movdqa {{.*#+}} [[LOWCST:xmm[0-9]+]] = [1258291200,1258291200,1258291200,1258291200] -; SSE-NEXT: por %[[LOWCST]], [[VECLOW]] -; SSE-NEXT: psrld $16, %xmm0 -; SSE-NEXT: movdqa {{.*#+}} [[HIGHCST:xmm[0-9]+]] = [1392508928,1392508928,1392508928,1392508928] -; SSE-NEXT: por %[[HIGHCST]], %xmm0 -; SSE-NEXT: movaps {{.*#+}} [[MAGICCST:xmm[0-9]+]] = [-5.497642e+11,-5.497642e+11,-5.497642e+11,-5.497642e+11] -; SSE-NEXT: addps %[[MAGICCST]], %xmm0 -; SSE-NEXT: addps [[VECLOW]], %xmm0 -; MASK is the low vector of the second part after this point. -; SSE-NEXT: pand %xmm1, %[[MASK]] -; SSE-NEXT: por %[[LOWCST]], %[[MASK]] -; SSE-NEXT: psrld $16, %xmm1 -; SSE-NEXT: por %[[HIGHCST]], %xmm1 -; SSE-NEXT: addps %[[MAGICCST]], %xmm1 -; SSE-NEXT: addps %[[MASK]], %xmm1 -; SSE-NEXT: retq -; -; SSE41: movdqa {{.*#+}} [[LOWCST:xmm[0-9]+]] = [1258291200,1258291200,1258291200,1258291200] -; SSE41-NEXT: movdqa %xmm0, [[VECLOW:%xmm[0-9]+]] -; SSE41-NEXT: pblendw $170, %[[LOWCST]], [[VECLOW]] -; SSE41-NEXT: psrld $16, %xmm0 -; SSE41-NEXT: movdqa {{.*#+}} [[HIGHCST:xmm[0-9]+]] = [1392508928,1392508928,1392508928,1392508928] -; SSE41-NEXT: pblendw $170, %[[HIGHCST]], %xmm0 -; SSE41-NEXT: movaps {{.*#+}} [[MAGICCST:xmm[0-9]+]] = [-5.497642e+11,-5.497642e+11,-5.497642e+11,-5.497642e+11] -; SSE41-NEXT: addps %[[MAGICCST]], %xmm0 -; SSE41-NEXT: addps [[VECLOW]], %xmm0 -; LOWCST is the low vector of the second part after this point. -; The operands of the blend are inverted because we reuse xmm1 -; in the next shift. -; SSE41-NEXT: pblendw $85, %xmm1, %[[LOWCST]] -; SSE41-NEXT: psrld $16, %xmm1 -; SSE41-NEXT: pblendw $170, %[[HIGHCST]], %xmm1 -; SSE41-NEXT: addps %[[MAGICCST]], %xmm1 -; SSE41-NEXT: addps %[[LOWCST]], %xmm1 -; SSE41-NEXT: retq -; -; Test that we are not lowering uinttofp to scalars -; AVX-NOT: cvtsd2ss -; AVX: retq -; -; AVX2: vpbroadcastd [[LOWCSTADDR]](%rip), [[LOWCST:%ymm[0-9]+]] -; AVX2-NEXT: vpblendw $170, [[LOWCST]], %ymm0, [[LOWVEC:%ymm[0-9]+]] -; AVX2-NEXT: vpsrld $16, %ymm0, [[SHIFTVEC:%ymm[0-9]+]] -; AVX2-NEXT: vpbroadcastd [[HIGHCSTADDR]](%rip), [[HIGHCST:%ymm[0-9]+]] -; AVX2-NEXT: vpblendw $170, [[HIGHCST]], [[SHIFTVEC]], [[HIGHVEC:%ymm[0-9]+]] -; AVX2-NEXT: vbroadcastss [[MAGICCSTADDR]](%rip), [[MAGICCST:%ymm[0-9]+]] -; AVX2-NEXT: vaddps [[MAGICCST]], [[HIGHVEC]], [[TMP:%ymm[0-9]+]] -; AVX2-NEXT: vaddps [[TMP]], [[LOWVEC]], %ymm0 -; AVX2-NEXT: retq - %C = uitofp <8 x i32> %A to <8 x float> - ret <8 x float> %C -} Index: test/Linker/lto-attributes.ll =================================================================== --- test/Linker/lto-attributes.ll +++ /dev/null @@ -1,7 +0,0 @@ -; RUN: llvm-link -S %s -o - | FileCheck %s - -; CHECK: @foo = private externally_initialized global i8* null -@foo = private externally_initialized global i8* null -; CHECK: @array = appending global [7 x i8] c"abcdefg", align 1 -@array = appending global [7 x i8] c"abcdefg", align 1 - Index: test/Object/AArch64/yaml2obj-elf-aarch64-rel.yaml =================================================================== --- test/Object/AArch64/yaml2obj-elf-aarch64-rel.yaml +++ /dev/null @@ -1,47 +0,0 @@ -# RUN: yaml2obj -format=elf %s > %t -# RUN: obj2yaml %t | FileCheck %s - -# CHECK: - Name: .rela.text -# CHECK-NEXT: Type: SHT_RELA -# CHECK-NEXT: Link: .symtab -# CHECK-NEXT: AddressAlign: 0x0000000000000008 -# CHECK-NEXT: Info: .text -# CHECK-NEXT: Relocations: -# CHECK-NEXT: - Offset: 0x0000000000000000 -# CHECK-NEXT: Symbol: main -# CHECK-NEXT: Type: R_AARCH64_ABS64 -# CHECK-NEXT: Addend: 0 - -FileHeader: - Class: ELFCLASS64 - Data: ELFDATA2LSB - Type: ET_REL - Machine: EM_AARCH64 -Sections: - - Type: SHT_PROGBITS - Name: .text - Flags: [ SHF_ALLOC, SHF_EXECINSTR ] - AddressAlign: 0x04 - Content: 0000000000000000 - - Type: SHT_RELA - Name: .rela.text - Link: .symtab - Info: .text - AddressAlign: 0x08 - Relocations: - - Offset: 0 - Symbol: main - Type: R_AARCH64_ABS64 - Addend: 0 - -Symbols: - Local: - - Name: .text - Type: STT_SECTION - Section: .text - - Global: - - Name: main - Type: STT_FUNC - Section: .text - Size: 0x08 Index: test/Transforms/Util/lowerswitch.ll =================================================================== --- test/Transforms/Util/lowerswitch.ll +++ /dev/null @@ -1,22 +0,0 @@ -; RUN: opt -lowerswitch -S < %s | FileCheck %s - -; Test that we don't crash and have a different basic block for each incoming edge. -define void @test_lower_switch() { -; CHECK-LABEL: @test_lower_switch -; CHECK: %merge = phi i64 [ 1, %BB3 ], [ 0, %NewDefault ], [ 0, %NodeBlock5 ], [ 0, %LeafBlock1 ] -BB1: - switch i32 undef, label %BB2 [ - i32 3, label %BB2 - i32 5, label %BB2 - i32 0, label %BB3 - i32 2, label %BB3 - i32 4, label %BB3 - ] - -BB2: - %merge = phi i64 [ 1, %BB3 ], [ 0, %BB1 ], [ 0, %BB1 ], [ 0, %BB1 ] - ret void - -BB3: - br label %BB2 -} Index: test/tools/llvm-symbolizer/ppc64.test =================================================================== --- test/tools/llvm-symbolizer/ppc64.test +++ test/tools/llvm-symbolizer/ppc64.test @@ -1,4 +1,3 @@ -// REQUIRES: python27 // ppc64 was compiled from this source on a big-endian 64-bit PowerPC box // with just "clang -nostdlib": int foo() { return 0; } Index: tools/CMakeLists.txt =================================================================== --- tools/CMakeLists.txt +++ tools/CMakeLists.txt @@ -8,12 +8,6 @@ list(APPEND LLVM_IMPLICIT_PROJECT_IGNORE "${LLVM_MAIN_SRC_DIR}/tools/polly") endif(WITH_POLLY) -if( LLVM_BUILD_LLVM_DYLIB ) - add_llvm_tool_subdirectory(llvm-shlib) -else() - ignore_llvm_tool_subdirectory(llvm-shlib) -endif() - add_llvm_tool_subdirectory(opt) add_llvm_tool_subdirectory(llvm-as) add_llvm_tool_subdirectory(llvm-dis) @@ -80,6 +74,12 @@ ignore_llvm_tool_subdirectory(gold) endif() +if( LLVM_BUILD_LLVM_DYLIB ) + add_llvm_tool_subdirectory(llvm-shlib) +else() + ignore_llvm_tool_subdirectory(llvm-shlib) +endif() + add_llvm_external_project(clang) if( NOT LLVM_INCLUDE_TOOLS STREQUAL "bootstrap-only" ) Index: tools/llvm-c-test/CMakeLists.txt =================================================================== --- tools/llvm-c-test/CMakeLists.txt +++ tools/llvm-c-test/CMakeLists.txt @@ -7,10 +7,6 @@ Target ) -if(TARGET LLVM) - set(LLVM_LINK_COMPONENTS) -endif() - if (LLVM_COMPILER_IS_GCC_COMPATIBLE) set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -std=gnu99 -Wstrict-prototypes") endif () @@ -25,8 +21,3 @@ object.c targets.c ) - -# Use libLLVM.so if it is available. -if(TARGET LLVM) - target_link_libraries(llvm-c-test LLVM) -endif() Index: tools/llvm-shlib/CMakeLists.txt =================================================================== --- tools/llvm-shlib/CMakeLists.txt +++ tools/llvm-shlib/CMakeLists.txt @@ -8,11 +8,10 @@ # LLVM components. All compoenent names handled by llvm-config are valid. if(NOT DEFINED LLVM_DYLIB_COMPONENTS) - set(LLVM_DYLIB_COMPONENTS + set(LLVM_LINK_COMPONENTS ${LLVM_TARGETS_TO_BUILD} Analysis AsmPrinter - BitReader BitWriter CodeGen Core @@ -25,7 +24,6 @@ Interpreter Linker MC - MCDisassembler MCJIT ObjCARCOpts Object @@ -37,6 +35,8 @@ Vectorize native ) +else() + set(LLVM_LINK_COMPONENTS ${LLVM_DYLIB_COMPONENTS}) endif() add_definitions( -DLLVM_VERSION_INFO=\"${PACKAGE_VERSION}\" ) @@ -56,7 +56,7 @@ set(LLVM_EXPORTED_SYMBOL_FILE ${CMAKE_BINARY_DIR}/libllvm.exports) - llvm_map_components_to_libnames(LIB_NAMES ${LLVM_DYLIB_COMPONENTS}) + llvm_map_components_to_libnames(LIB_NAMES ${LLVM_LINK_COMPONENTS}) foreach (lib ${LIB_NAMES}) @@ -85,14 +85,6 @@ add_llvm_library(LLVM SHARED ${SOURCES}) -if("${CMAKE_SYSTEM_NAME}" STREQUAL "Linux") # FIXME: It should be "GNU ld for elf" - # GNU ld doesn't resolve symbols in the version script. - list(REMOVE_DUPLICATES LIB_NAMES) - set(LIB_NAMES -Wl,--whole-archive ${LIB_NAMES} -Wl,--no-whole-archive) -endif() - -target_link_libraries(LLVM ${cmake_2_8_12_PRIVATE} ${LIB_NAMES}) - add_dependencies(LLVM ${LLVM_EXPORTED_SYMBOL_FILE}) if (APPLE)