Index: llvm/lib/Target/AArch64/AArch64CallingConvention.h =================================================================== --- llvm/lib/Target/AArch64/AArch64CallingConvention.h +++ llvm/lib/Target/AArch64/AArch64CallingConvention.h @@ -1,4 +1,4 @@ -//=== AArch64CallingConv.h - Custom Calling Convention Routines -*- C++ -*-===// +//=== AArch64CallingConvention.h - AArch64 CC entry points ------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,133 +6,40 @@ // //===----------------------------------------------------------------------===// // -// This file contains the custom routines for the AArch64 Calling Convention -// that aren't done by tablegen. +// This file declares the entry points for AArch64 calling convention analysis. // //===----------------------------------------------------------------------===// #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64CALLINGCONVENTION_H #define LLVM_LIB_TARGET_AARCH64_AARCH64CALLINGCONVENTION_H -#include "AArch64.h" -#include "AArch64InstrInfo.h" -#include "AArch64Subtarget.h" #include "llvm/CodeGen/CallingConvLower.h" -#include "llvm/CodeGen/TargetInstrInfo.h" -#include "llvm/IR/CallingConv.h" -namespace { -using namespace llvm; - -static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2, - AArch64::X3, AArch64::X4, AArch64::X5, - AArch64::X6, AArch64::X7}; -static const MCPhysReg HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2, - AArch64::H3, AArch64::H4, AArch64::H5, - AArch64::H6, AArch64::H7}; -static const MCPhysReg SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2, - AArch64::S3, AArch64::S4, AArch64::S5, - AArch64::S6, AArch64::S7}; -static const MCPhysReg DRegList[] = {AArch64::D0, AArch64::D1, AArch64::D2, - AArch64::D3, AArch64::D4, AArch64::D5, - AArch64::D6, AArch64::D7}; -static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2, - AArch64::Q3, AArch64::Q4, AArch64::Q5, - AArch64::Q6, AArch64::Q7}; - -static bool finishStackBlock(SmallVectorImpl &PendingMembers, - MVT LocVT, ISD::ArgFlagsTy &ArgFlags, - CCState &State, unsigned SlotAlign) { - unsigned Size = LocVT.getSizeInBits() / 8; - unsigned StackAlign = - State.getMachineFunction().getDataLayout().getStackAlignment(); - unsigned Align = std::min(ArgFlags.getOrigAlign(), StackAlign); - - for (auto &It : PendingMembers) { - It.convertToMem(State.AllocateStack(Size, std::max(Align, SlotAlign))); - State.addLoc(It); - SlotAlign = 1; - } - - // All pending members have now been allocated - PendingMembers.clear(); - return true; -} - -/// The Darwin variadic PCS places anonymous arguments in 8-byte stack slots. An -/// [N x Ty] type must still be contiguous in memory though. -static bool CC_AArch64_Custom_Stack_Block( - unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, - ISD::ArgFlagsTy &ArgFlags, CCState &State) { - SmallVectorImpl &PendingMembers = State.getPendingLocs(); - - // Add the argument to the list to be allocated once we know the size of the - // block. - PendingMembers.push_back( - CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo)); - - if (!ArgFlags.isInConsecutiveRegsLast()) - return true; - - return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, 8); -} - -/// Given an [N x Ty] block, it should be passed in a consecutive sequence of -/// registers. If no such sequence is available, mark the rest of the registers -/// of that type as used and place the argument on the stack. -static bool CC_AArch64_Custom_Block(unsigned &ValNo, MVT &ValVT, MVT &LocVT, - CCValAssign::LocInfo &LocInfo, - ISD::ArgFlagsTy &ArgFlags, CCState &State) { - // Try to allocate a contiguous block of registers, each of the correct - // size to hold one member. - ArrayRef RegList; - if (LocVT.SimpleTy == MVT::i64) - RegList = XRegList; - else if (LocVT.SimpleTy == MVT::f16) - RegList = HRegList; - else if (LocVT.SimpleTy == MVT::f32 || LocVT.is32BitVector()) - RegList = SRegList; - else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector()) - RegList = DRegList; - else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector()) - RegList = QRegList; - else { - // Not an array we want to split up after all. - return false; - } - - SmallVectorImpl &PendingMembers = State.getPendingLocs(); - - // Add the argument to the list to be allocated once we know the size of the - // block. - PendingMembers.push_back( - CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo)); - - if (!ArgFlags.isInConsecutiveRegsLast()) - return true; - - unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size()); - if (RegResult) { - for (auto &It : PendingMembers) { - It.convertToReg(RegResult); - State.addLoc(It); - ++RegResult; - } - PendingMembers.clear(); - return true; - } - - // Mark all regs in the class as unavailable - for (auto Reg : RegList) - State.AllocateReg(Reg); - - const AArch64Subtarget &Subtarget = static_cast( - State.getMachineFunction().getSubtarget()); - unsigned SlotAlign = Subtarget.isTargetDarwin() ? 1 : 8; - - return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, SlotAlign); -} - -} +namespace llvm { +bool CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, + CCState &State); +bool CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, + ISD::ArgFlagsTy ArgFlags, CCState &State); +bool CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, + ISD::ArgFlagsTy ArgFlags, CCState &State); +bool CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, + ISD::ArgFlagsTy ArgFlags, CCState &State); +bool CC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, + ISD::ArgFlagsTy ArgFlags, CCState &State); +bool CC_AArch64_GHC(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, + CCState &State); +bool RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, + CCState &State); +bool RetCC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, + ISD::ArgFlagsTy ArgFlags, CCState &State); +} // namespace llvm #endif Index: llvm/lib/Target/AArch64/AArch64CallingConvention.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64CallingConvention.cpp +++ llvm/lib/Target/AArch64/AArch64CallingConvention.cpp @@ -1,4 +1,4 @@ -//=== AArch64CallingConv.h - Custom Calling Convention Routines -*- C++ -*-===// +//=== AArch64CallingConvention.cpp - AArch64 CC impl ------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,22 +6,18 @@ // //===----------------------------------------------------------------------===// // -// This file contains the custom routines for the AArch64 Calling Convention -// that aren't done by tablegen. +// This file contains the table-generated and custom routines for the AArch64 +// Calling Convention. // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64CALLINGCONVENTION_H -#define LLVM_LIB_TARGET_AARCH64_AARCH64CALLINGCONVENTION_H - +#include "AArch64CallingConvention.h" #include "AArch64.h" #include "AArch64InstrInfo.h" #include "AArch64Subtarget.h" #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/TargetInstrInfo.h" #include "llvm/IR/CallingConv.h" - -namespace { using namespace llvm; static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2, @@ -133,6 +129,6 @@ return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, SlotAlign); } -} - -#endif +// TableGen provides definitions of the calling convention analysis entry +// points. +#include "AArch64GenCallingConv.inc" Index: llvm/lib/Target/AArch64/AArch64CallingConvention.td =================================================================== --- llvm/lib/Target/AArch64/AArch64CallingConvention.td +++ llvm/lib/Target/AArch64/AArch64CallingConvention.td @@ -21,6 +21,7 @@ // ARM AAPCS64 Calling Convention //===----------------------------------------------------------------------===// +let Entry = 1 in def CC_AArch64_AAPCS : CallingConv<[ CCIfType<[iPTR], CCBitConvertToType>, CCIfType<[v2f32], CCBitConvertToType>, @@ -88,6 +89,7 @@ CCAssignToStack<16, 16>> ]>; +let Entry = 1 in def RetCC_AArch64_AAPCS : CallingConv<[ CCIfType<[iPTR], CCBitConvertToType>, CCIfType<[v2f32], CCBitConvertToType>, @@ -121,6 +123,7 @@ ]>; // Vararg functions on windows pass floats in integer registers +let Entry = 1 in def CC_AArch64_Win64_VarArg : CallingConv<[ CCIfType<[f16, f32], CCPromoteToType>, CCIfType<[f64], CCBitConvertToType>, @@ -132,6 +135,7 @@ // from the standard one at this level: // + i128s (i.e. split i64s) don't need even registers. // + Stack slots are sized as needed rather than being at least 64-bit. +let Entry = 1 in def CC_AArch64_DarwinPCS : CallingConv<[ CCIfType<[iPTR], CCBitConvertToType>, CCIfType<[v2f32], CCBitConvertToType>, @@ -188,6 +192,7 @@ CCAssignToStack<16, 16>> ]>; +let Entry = 1 in def CC_AArch64_DarwinPCS_VarArg : CallingConv<[ CCIfType<[iPTR], CCBitConvertToType>, CCIfType<[v2f32], CCBitConvertToType>, @@ -212,6 +217,7 @@ // in register and the remaining arguments on stack. We allow 32bit stack slots, // so that WebKit can write partial values in the stack and define the other // 32bit quantity as undef. +let Entry = 1 in def CC_AArch64_WebKit_JS : CallingConv<[ // Handle i1, i8, i16, i32, and i64 passing in register X0 (W0). CCIfType<[i1, i8, i16], CCPromoteToType>, @@ -223,6 +229,7 @@ CCIfType<[i64, f64], CCAssignToStack<8, 8>> ]>; +let Entry = 1 in def RetCC_AArch64_WebKit_JS : CallingConv<[ CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7], [X0, X1, X2, X3, X4, X5, X6, X7]>>, @@ -256,6 +263,7 @@ // The AArch64 register mapping is under the heading "The ARMv8/AArch64 ABI // register mapping". +let Entry = 1 in def CC_AArch64_GHC : CallingConv<[ CCIfType<[iPTR], CCBitConvertToType>, Index: llvm/lib/Target/AArch64/AArch64FastISel.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64FastISel.cpp +++ llvm/lib/Target/AArch64/AArch64FastISel.cpp @@ -304,8 +304,6 @@ } // end anonymous namespace -#include "AArch64GenCallingConv.inc" - /// Check if the sign-/zero-extend will be a noop. static bool isIntExtFree(const Instruction *I) { assert((isa(I) || isa(I)) && @@ -5171,10 +5169,6 @@ return selectAtomicCmpXchg(cast(I)); } - // Silence warnings. - (void)&CC_AArch64_DarwinPCS_VarArg; - (void)&CC_AArch64_Win64_VarArg; - // fall-back to target-independent instruction selection. return selectOperator(I, I->getOpcode()); } Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -2972,8 +2972,6 @@ // Calling Convention Implementation //===----------------------------------------------------------------------===// -#include "AArch64GenCallingConv.inc" - /// Selects the correct CCAssignFn for a given CallingConvention value. CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const { Index: llvm/lib/Target/AArch64/CMakeLists.txt =================================================================== --- llvm/lib/Target/AArch64/CMakeLists.txt +++ llvm/lib/Target/AArch64/CMakeLists.txt @@ -24,6 +24,7 @@ AArch64AdvSIMDScalarPass.cpp AArch64AsmPrinter.cpp AArch64BranchTargets.cpp + AArch64CallingConvention.cpp AArch64CallLowering.cpp AArch64CleanupLocalDynamicTLSPass.cpp AArch64CollectLOH.cpp Index: llvm/lib/Target/ARM/ARMCallingConv.h =================================================================== --- llvm/lib/Target/ARM/ARMCallingConv.h +++ llvm/lib/Target/ARM/ARMCallingConv.h @@ -6,286 +6,45 @@ // //===----------------------------------------------------------------------===// // -// This file contains the custom routines for the ARM Calling Convention that -// aren't done by tablegen. +// This file declares the entry points for ARM calling convention analysis. // //===----------------------------------------------------------------------===// #ifndef LLVM_LIB_TARGET_ARM_ARMCALLINGCONV_H #define LLVM_LIB_TARGET_ARM_ARMCALLINGCONV_H -#include "ARM.h" -#include "ARMBaseInstrInfo.h" -#include "ARMSubtarget.h" #include "llvm/CodeGen/CallingConvLower.h" -#include "llvm/CodeGen/TargetInstrInfo.h" -#include "llvm/IR/CallingConv.h" namespace llvm { -// APCS f64 is in register pairs, possibly split to stack -static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, - CCValAssign::LocInfo &LocInfo, - CCState &State, bool CanFail) { - static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; - - // Try to get the first register. - if (unsigned Reg = State.AllocateReg(RegList)) - State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); - else { - // For the 2nd half of a v2f64, do not fail. - if (CanFail) - return false; - - // Put the whole thing on the stack. - State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, - State.AllocateStack(8, 4), - LocVT, LocInfo)); - return true; - } - - // Try to get the second register. - if (unsigned Reg = State.AllocateReg(RegList)) - State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); - else - State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, - State.AllocateStack(4, 4), - LocVT, LocInfo)); - return true; -} - -static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, - CCValAssign::LocInfo &LocInfo, - ISD::ArgFlagsTy &ArgFlags, - CCState &State) { - if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true)) - return false; - if (LocVT == MVT::v2f64 && - !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false)) - return false; - return true; // we handled it -} - -// AAPCS f64 is in aligned register pairs -static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, - CCValAssign::LocInfo &LocInfo, - CCState &State, bool CanFail) { - static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; - static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; - static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 }; - static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; - - unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList); - if (Reg == 0) { - - // If we had R3 unallocated only, now we still must to waste it. - Reg = State.AllocateReg(GPRArgRegs); - assert((!Reg || Reg == ARM::R3) && "Wrong GPRs usage for f64"); - - // For the 2nd half of a v2f64, do not just fail. - if (CanFail) - return false; - - // Put the whole thing on the stack. - State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, - State.AllocateStack(8, 8), - LocVT, LocInfo)); - return true; - } - - unsigned i; - for (i = 0; i < 2; ++i) - if (HiRegList[i] == Reg) - break; - - unsigned T = State.AllocateReg(LoRegList[i]); - (void)T; - assert(T == LoRegList[i] && "Could not allocate register"); - - State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); - State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], - LocVT, LocInfo)); - return true; -} - -static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, - CCValAssign::LocInfo &LocInfo, - ISD::ArgFlagsTy &ArgFlags, - CCState &State) { - if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true)) - return false; - if (LocVT == MVT::v2f64 && - !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false)) - return false; - return true; // we handled it -} - -static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT, - CCValAssign::LocInfo &LocInfo, CCState &State) { - static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; - static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; - - unsigned Reg = State.AllocateReg(HiRegList, LoRegList); - if (Reg == 0) - return false; // we didn't handle it - - unsigned i; - for (i = 0; i < 2; ++i) - if (HiRegList[i] == Reg) - break; - - State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); - State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], - LocVT, LocInfo)); - return true; -} - -static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, - CCValAssign::LocInfo &LocInfo, - ISD::ArgFlagsTy &ArgFlags, - CCState &State) { - if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) - return false; - if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) - return false; - return true; // we handled it -} - -static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, - CCValAssign::LocInfo &LocInfo, - ISD::ArgFlagsTy &ArgFlags, - CCState &State) { - return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, - State); -} - -static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; - -static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3, - ARM::S4, ARM::S5, ARM::S6, ARM::S7, - ARM::S8, ARM::S9, ARM::S10, ARM::S11, - ARM::S12, ARM::S13, ARM::S14, ARM::S15 }; -static const MCPhysReg DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, - ARM::D4, ARM::D5, ARM::D6, ARM::D7 }; -static const MCPhysReg QRegList[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3 }; - - -// Allocate part of an AAPCS HFA or HVA. We assume that each member of the HA -// has InConsecutiveRegs set, and that the last member also has -// InConsecutiveRegsLast set. We must process all members of the HA before -// we can allocate it, as we need to know the total number of registers that -// will be needed in order to (attempt to) allocate a contiguous block. -static bool CC_ARM_AAPCS_Custom_Aggregate(unsigned &ValNo, MVT &ValVT, - MVT &LocVT, - CCValAssign::LocInfo &LocInfo, - ISD::ArgFlagsTy &ArgFlags, - CCState &State) { - SmallVectorImpl &PendingMembers = State.getPendingLocs(); - - // AAPCS HFAs must have 1-4 elements, all of the same type - if (PendingMembers.size() > 0) - assert(PendingMembers[0].getLocVT() == LocVT); - - // Add the argument to the list to be allocated once we know the size of the - // aggregate. Store the type's required alignmnent as extra info for later: in - // the [N x i64] case all trace has been removed by the time we actually get - // to do allocation. - PendingMembers.push_back(CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo, - ArgFlags.getOrigAlign())); - - if (!ArgFlags.isInConsecutiveRegsLast()) - return true; - - // Try to allocate a contiguous block of registers, each of the correct - // size to hold one member. - auto &DL = State.getMachineFunction().getDataLayout(); - unsigned StackAlign = DL.getStackAlignment(); - unsigned Align = std::min(PendingMembers[0].getExtraInfo(), StackAlign); - - ArrayRef RegList; - switch (LocVT.SimpleTy) { - case MVT::i32: { - RegList = RRegList; - unsigned RegIdx = State.getFirstUnallocated(RegList); - - // First consume all registers that would give an unaligned object. Whether - // we go on stack or in regs, no-one will be using them in future. - unsigned RegAlign = alignTo(Align, 4) / 4; - while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) - State.AllocateReg(RegList[RegIdx++]); - - break; - } - case MVT::f16: - case MVT::f32: - RegList = SRegList; - break; - case MVT::v4f16: - case MVT::f64: - RegList = DRegList; - break; - case MVT::v8f16: - case MVT::v2f64: - RegList = QRegList; - break; - default: - llvm_unreachable("Unexpected member type for block aggregate"); - break; - } - - unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size()); - if (RegResult) { - for (SmallVectorImpl::iterator It = PendingMembers.begin(); - It != PendingMembers.end(); ++It) { - It->convertToReg(RegResult); - State.addLoc(*It); - ++RegResult; - } - PendingMembers.clear(); - return true; - } - - // Register allocation failed, we'll be needing the stack - unsigned Size = LocVT.getSizeInBits() / 8; - if (LocVT == MVT::i32 && State.getNextStackOffset() == 0) { - // If nothing else has used the stack until this point, a non-HFA aggregate - // can be split between regs and stack. - unsigned RegIdx = State.getFirstUnallocated(RegList); - for (auto &It : PendingMembers) { - if (RegIdx >= RegList.size()) - It.convertToMem(State.AllocateStack(Size, Size)); - else - It.convertToReg(State.AllocateReg(RegList[RegIdx++])); - - State.addLoc(It); - } - PendingMembers.clear(); - return true; - } else if (LocVT != MVT::i32) - RegList = SRegList; - - // Mark all regs as unavailable (AAPCS rule C.2.vfp for VFP, C.6 for core) - for (auto Reg : RegList) - State.AllocateReg(Reg); - - // After the first item has been allocated, the rest are packed as tightly as - // possible. (E.g. an incoming i64 would have starting Align of 8, but we'll - // be allocating a bunch of i32 slots). - unsigned RestAlign = std::min(Align, Size); - - for (auto &It : PendingMembers) { - It.convertToMem(State.AllocateStack(Size, Align)); - State.addLoc(It); - Align = RestAlign; - } - - // All pending members have now been allocated - PendingMembers.clear(); - - // This will be allocated by the last member of the aggregate - return true; -} - -} // End llvm namespace +bool CC_ARM_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, + CCState &State); +bool CC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, + CCState &State); +bool CC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, + CCState &State); +bool CC_ARM_APCS_GHC(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, + CCState &State); +bool FastCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, + CCState &State); +bool RetCC_ARM_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, + CCState &State); +bool RetCC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, + CCState &State); +bool RetCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, + CCState &State); +bool RetFastCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, + CCState &State); + +} // namespace llvm #endif Index: llvm/lib/Target/ARM/ARMCallingConv.cpp =================================================================== --- llvm/lib/Target/ARM/ARMCallingConv.cpp +++ llvm/lib/Target/ARM/ARMCallingConv.cpp @@ -1,4 +1,4 @@ -//=== ARMCallingConv.h - ARM Custom Calling Convention Routines -*- C++ -*-===// +//=== ARMCallingConv.cpp - ARM Custom CC Routines ---------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -7,21 +7,15 @@ //===----------------------------------------------------------------------===// // // This file contains the custom routines for the ARM Calling Convention that -// aren't done by tablegen. +// aren't done by tablegen, and includes the table generated implementations. // //===----------------------------------------------------------------------===// -#ifndef LLVM_LIB_TARGET_ARM_ARMCALLINGCONV_H -#define LLVM_LIB_TARGET_ARM_ARMCALLINGCONV_H - #include "ARM.h" -#include "ARMBaseInstrInfo.h" +#include "ARMCallingConv.h" #include "ARMSubtarget.h" -#include "llvm/CodeGen/CallingConvLower.h" -#include "llvm/CodeGen/TargetInstrInfo.h" -#include "llvm/IR/CallingConv.h" - -namespace llvm { +#include "ARMRegisterInfo.h" +using namespace llvm; // APCS f64 is in register pairs, possibly split to stack static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, @@ -286,6 +280,5 @@ return true; } -} // End llvm namespace - -#endif +// Include the table generated calling convention implementations. +#include "ARMGenCallingConv.inc" Index: llvm/lib/Target/ARM/ARMCallingConv.td =================================================================== --- llvm/lib/Target/ARM/ARMCallingConv.td +++ llvm/lib/Target/ARM/ARMCallingConv.td @@ -15,6 +15,7 @@ //===----------------------------------------------------------------------===// // ARM APCS Calling Convention //===----------------------------------------------------------------------===// +let Entry = 1 in def CC_ARM_APCS : CallingConv<[ // Handles byval parameters. @@ -43,6 +44,7 @@ CCIfType<[v2f64], CCAssignToStack<16, 4>> ]>; +let Entry = 1 in def RetCC_ARM_APCS : CallingConv<[ CCIfType<[i1, i8, i16], CCPromoteToType>, CCIfType<[f32], CCBitConvertToType>, @@ -66,6 +68,7 @@ //===----------------------------------------------------------------------===// // ARM APCS Calling Convention for FastCC (when VFP2 or later is available) //===----------------------------------------------------------------------===// +let Entry = 1 in def FastCC_ARM_APCS : CallingConv<[ // Handle all vector types as either f64 or v2f64. CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType>, @@ -85,6 +88,7 @@ CCDelegateTo ]>; +let Entry = 1 in def RetFastCC_ARM_APCS : CallingConv<[ // Handle all vector types as either f64 or v2f64. CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType>, @@ -101,6 +105,7 @@ // ARM APCS Calling Convention for GHC //===----------------------------------------------------------------------===// +let Entry = 1 in def CC_ARM_APCS_GHC : CallingConv<[ // Handle all vector types as either f64 or v2f64. CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType>, @@ -151,6 +156,7 @@ // ARM AAPCS (EABI) Calling Convention //===----------------------------------------------------------------------===// +let Entry = 1 in def CC_ARM_AAPCS : CallingConv<[ // Handles byval parameters. CCIfByVal>, @@ -173,6 +179,7 @@ CCDelegateTo ]>; +let Entry = 1 in def RetCC_ARM_AAPCS : CallingConv<[ // Handle all vector types as either f64 or v2f64. CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType>, @@ -195,6 +202,7 @@ // Also used for FastCC (when VFP2 or later is available) //===----------------------------------------------------------------------===// +let Entry = 1 in def CC_ARM_AAPCS_VFP : CallingConv<[ // Handles byval parameters. CCIfByVal>, @@ -219,6 +227,7 @@ CCDelegateTo ]>; +let Entry = 1 in def RetCC_ARM_AAPCS_VFP : CallingConv<[ // Handle all vector types as either f64 or v2f64. CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType>, Index: llvm/lib/Target/ARM/ARMFastISel.cpp =================================================================== --- llvm/lib/Target/ARM/ARMFastISel.cpp +++ llvm/lib/Target/ARM/ARMFastISel.cpp @@ -244,8 +244,6 @@ } // end anonymous namespace -#include "ARMGenCallingConv.inc" - // DefinesOptionalPredicate - This is different from DefinesPredicate in that // we don't care about implicit defs here, just places we'll need to add a // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR. Index: llvm/lib/Target/ARM/ARMISelLowering.cpp =================================================================== --- llvm/lib/Target/ARM/ARMISelLowering.cpp +++ llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -1591,8 +1591,6 @@ // Calling Convention Implementation //===----------------------------------------------------------------------===// -#include "ARMGenCallingConv.inc" - /// getEffectiveCallingConv - Get the effective calling convention, taking into /// account presence of floating point hardware and calling convention /// limitations, such as support for variadic functions. Index: llvm/lib/Target/ARM/CMakeLists.txt =================================================================== --- llvm/lib/Target/ARM/CMakeLists.txt +++ llvm/lib/Target/ARM/CMakeLists.txt @@ -22,6 +22,7 @@ ARMAsmPrinter.cpp ARMBaseInstrInfo.cpp ARMBaseRegisterInfo.cpp + ARMCallingConv.cpp ARMCallLowering.cpp ARMCodeGenPrepare.cpp ARMConstantIslandPass.cpp