Index: lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -143,6 +143,10 @@
   getActionDefinitionsBuilder(G_FPTRUNC)
     .legalFor({{S32, S64}});
 
+  getActionDefinitionsBuilder(G_FPEXT)
+    .legalFor({{S64, S32}, {S32, S16}})
+    .lowerFor({{S64, S16}}); // FIXME: Implement
+
   // Use actual fsub instruction
   setAction({G_FSUB, S32}, Legal);
 
@@ -153,13 +157,8 @@
   setAction({G_FCMP, 1, S32}, Legal);
   setAction({G_FCMP, 1, S64}, Legal);
 
-  getActionDefinitionsBuilder(G_ANYEXT)
-    .legalFor({{S32, S16}, {S64, S32}, {S64, S16}});
-
-  getActionDefinitionsBuilder(G_SEXT)
-    .legalFor({{S64, S32}});
-  getActionDefinitionsBuilder(G_ZEXT)
-    .legalFor({{S64, S32}});
+  getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
+    .legalFor({{S64, S32}, {S32, S16}, {S64, S16}});
 
   setAction({G_FPTOSI, S32}, Legal);
   setAction({G_FPTOSI, 1, S32}, Legal);
Index: test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
===================================================================
--- test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
+++ test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
@@ -2,12 +2,12 @@
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
 
 ---
-name: test_anyext_i32_to_i64
+name: test_anyext_s32_to_s64
 body: |
   bb.0.entry:
     liveins: $vgpr0
 
-    ; CHECK-LABEL: name: test_anyext_i32_to_i64
+    ; CHECK-LABEL: name: test_anyext_s32_to_s64
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
     ; CHECK: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
@@ -17,12 +17,12 @@
 ...
 
 ---
-name: test_anyext_i16_to_i64
+name: test_anyext_s16_to_s64
 body: |
   bb.0.entry:
     liveins: $vgpr0
 
-    ; CHECK-LABEL: name: test_anyext_i16_to_i64
+    ; CHECK-LABEL: name: test_anyext_s16_to_s64
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
     ; CHECK: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
@@ -33,12 +33,12 @@
 ...
 
 ---
-name: test_anyext_i16_to_i32
+name: test_anyext_s16_to_s32
 body: |
   bb.0.entry:
     liveins: $vgpr0
 
-    ; CHECK-LABEL: name: test_anyext_i16_to_i32
+    ; CHECK-LABEL: name: test_anyext_s16_to_s32
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
     ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
@@ -49,12 +49,12 @@
 ...
 
 ---
-name: test_anyext_i1_to_i32
+name: test_anyext_i1_to_s32
 body: |
   bb.0.entry:
     liveins: $vgpr0
 
-    ; CHECK-LABEL: name: test_anyext_i1_to_i32
+    ; CHECK-LABEL: name: test_anyext_i1_to_s32
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
     ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
Index: test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir
@@ -0,0 +1,34 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
+
+---
+name: test_fpext_f16_to_f32
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_fpext_f16_to_f32
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+    ; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
+    ; CHECK: $vgpr0 = COPY [[FPEXT]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s16) = G_TRUNC %0
+    %2:_(s32) = G_FPEXT %1
+    $vgpr0 = COPY %2
+...
+
+---
+name: test_fpext_f32_to_f64
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_fpext_f32_to_f64
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[COPY]](s32)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[FPEXT]](s64)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s64) = G_FPEXT %0
+    $vgpr0_vgpr1 = COPY %1
+...
Index: test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
===================================================================
--- test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
+++ test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
@@ -2,12 +2,12 @@
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
 
 ---
-name: test_sext_i32_to_i64
+name: test_sext_s32_to_s64
 body: |
   bb.0.entry:
     liveins: $vgpr0
 
-    ; CHECK-LABEL: name: test_sext_i32_to_i64
+    ; CHECK-LABEL: name: test_sext_s32_to_s64
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s32)
     ; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
@@ -17,12 +17,12 @@
 ...
 
 ---
-name: test_sext_i16_to_i64
+name: test_sext_s16_to_s64
 body: |
   bb.0.entry:
     liveins: $vgpr0
 
-    ; CHECK-LABEL: name: test_sext_i16_to_i64
+    ; CHECK-LABEL: name: test_sext_s16_to_s64
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
     ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
@@ -38,12 +38,12 @@
 ...
 
 ---
-name: test_sext_i16_to_i32
+name: test_sext_s16_to_s32
 body: |
   bb.0.entry:
     liveins: $vgpr0
 
-    ; CHECK-LABEL: name: test_sext_i16_to_i32
+    ; CHECK-LABEL: name: test_sext_s16_to_s32
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
@@ -57,12 +57,12 @@
 ...
 
 ---
-name: test_sext_i1_to_i32
+name: test_sext_i1_to_s32
 body: |
   bb.0.entry:
     liveins: $vgpr0
 
-    ; CHECK-LABEL: name: test_sext_i1_to_i32
+    ; CHECK-LABEL: name: test_sext_i1_to_s32
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
Index: test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
===================================================================
--- test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
+++ test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
@@ -2,12 +2,12 @@
 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
 
 ---
-name: test_zext_i32_to_i64
+name: test_zext_s32_to_s64
 body: |
   bb.0.entry:
     liveins: $vgpr0
 
-    ; CHECK-LABEL: name: test_zext_i32_to_i64
+    ; CHECK-LABEL: name: test_zext_s32_to_s64
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
     ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
@@ -17,12 +17,12 @@
 ...
 
 ---
-name: test_zext_i16_to_i64
+name: test_zext_s16_to_s64
 body: |
   bb.0.entry:
     liveins: $vgpr0
 
-    ; CHECK-LABEL: name: test_zext_i16_to_i64
+    ; CHECK-LABEL: name: test_zext_s16_to_s64
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535
     ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
@@ -35,12 +35,12 @@
 ...
 
 ---
-name: test_zext_i16_to_i32
+name: test_zext_s16_to_s32
 body: |
   bb.0.entry:
     liveins: $vgpr0
 
-    ; CHECK-LABEL: name: test_zext_i16_to_i32
+    ; CHECK-LABEL: name: test_zext_s16_to_s32
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
@@ -53,12 +53,12 @@
 ...
 
 ---
-name: test_zext_i1_to_i32
+name: test_zext_i1_to_s32
 body: |
   bb.0.entry:
     liveins: $vgpr0
 
-    ; CHECK-LABEL: name: test_zext_i1_to_i32
+    ; CHECK-LABEL: name: test_zext_i1_to_s32
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)