Index: lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp =================================================================== --- lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -141,6 +141,7 @@ SDValue ExpandFunnelShift(SDValue Op); SDValue ExpandROT(SDValue Op); SDValue ExpandFMINNUM_FMAXNUM(SDValue Op); + SDValue ExpandAddSubSat(SDValue Op); SDValue ExpandStrictFPOp(SDValue Op); /// Implements vector promotion. @@ -779,6 +780,11 @@ case ISD::FMINNUM: case ISD::FMAXNUM: return ExpandFMINNUM_FMAXNUM(Op); + case ISD::USUBSAT: + case ISD::SSUBSAT: + case ISD::UADDSAT: + case ISD::SADDSAT: + return ExpandAddSubSat(Op); case ISD::STRICT_FADD: case ISD::STRICT_FSUB: case ISD::STRICT_FMUL: @@ -1208,6 +1214,12 @@ return DAG.UnrollVectorOp(Op.getNode()); } +SDValue VectorLegalizer::ExpandAddSubSat(SDValue Op) { + if (SDValue Expanded = TLI.expandAddSubSat(Op.getNode(), DAG)) + return Expanded; + return DAG.UnrollVectorOp(Op.getNode()); +} + SDValue VectorLegalizer::ExpandStrictFPOp(SDValue Op) { EVT VT = Op.getValueType(); EVT EltVT = VT.getVectorElementType(); Index: lib/CodeGen/SelectionDAG/TargetLowering.cpp =================================================================== --- lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -5277,6 +5277,21 @@ SDValue TargetLowering::expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const { unsigned Opcode = Node->getOpcode(); + SDValue LHS = Node->getOperand(0); + SDValue RHS = Node->getOperand(1); + SDLoc dl(Node); + + EVT VT = LHS.getValueType(); + if (VT.isVector()) { + // usub.sat(a, b) -> umax(a, b) - b + if (Opcode == ISD::USUBSAT && isOperationLegal(ISD::UMAX, VT)) { + SDValue Max = DAG.getNode(ISD::UMAX, dl, VT, LHS, RHS); + return DAG.getNode(ISD::SUB, dl, VT, Max, RHS); + } + + return SDValue(); + } + unsigned OverflowOp; switch (Opcode) { case ISD::SADDSAT: @@ -5295,11 +5310,7 @@ llvm_unreachable("Expected method to receive signed or unsigned saturation " "addition or subtraction node."); } - assert(Node->getNumOperands() == 2 && "Expected node to have 2 operands."); - SDLoc dl(Node); - SDValue LHS = Node->getOperand(0); - SDValue RHS = Node->getOperand(1); assert(LHS.getValueType().isScalarInteger() && "Expected operands to be integers. Vector of int arguments should " "already be unrolled."); Index: lib/Target/X86/X86ISelLowering.cpp =================================================================== --- lib/Target/X86/X86ISelLowering.cpp +++ lib/Target/X86/X86ISelLowering.cpp @@ -1222,6 +1222,7 @@ setOperationAction(ISD::SADDSAT, MVT::v16i16, HasInt256 ? Legal : Custom); setOperationAction(ISD::USUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom); setOperationAction(ISD::SSUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom); + setOperationAction(ISD::USUBSAT, MVT::v8i32, Custom); for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) { setOperationAction(ISD::ABS, VT, HasInt256 ? Legal : Custom); @@ -23567,7 +23568,8 @@ return split256IntArith(Op, DAG); } -static SDValue LowerADDSAT_SUBSAT(SDValue Op, SelectionDAG &DAG) { +static SDValue LowerADDSAT_SUBSAT(SDValue Op, const X86Subtarget &Subtraget, + SelectionDAG &DAG) { MVT VT = Op.getSimpleValueType(); if (VT.getScalarType() == MVT::i1) { SDLoc dl(Op); @@ -23583,10 +23585,14 @@ } } - assert(Op.getSimpleValueType().is256BitVector() && - Op.getSimpleValueType().isInteger() && - "Only handle AVX 256-bit vector integer operation"); - return split256IntArith(Op, DAG); + if (VT.is256BitVector() && !Subtraget.hasInt256()) { + assert(VT.isInteger() && + "Only handle AVX 256-bit vector integer operation"); + return split256IntArith(Op, DAG); + } + + // Default to expand. + return SDValue(); } static SDValue LowerABS(SDValue Op, const X86Subtarget &Subtarget, @@ -26300,7 +26306,7 @@ case ISD::UADDSAT: case ISD::SADDSAT: case ISD::USUBSAT: - case ISD::SSUBSAT: return LowerADDSAT_SUBSAT(Op, DAG); + case ISD::SSUBSAT: return LowerADDSAT_SUBSAT(Op, Subtarget, DAG); case ISD::SMAX: case ISD::SMIN: case ISD::UMAX: Index: lib/Target/X86/X86TargetTransformInfo.cpp =================================================================== --- lib/Target/X86/X86TargetTransformInfo.cpp +++ lib/Target/X86/X86TargetTransformInfo.cpp @@ -1780,6 +1780,10 @@ { ISD::CTPOP, MVT::v16i32, 24 }, { ISD::CTTZ, MVT::v8i64, 20 }, { ISD::CTTZ, MVT::v16i32, 28 }, + { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd + { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq + { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq + { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq }; static const CostTblEntry XOPCostTbl[] = { { ISD::BITREVERSE, MVT::v4i64, 4 }, @@ -1823,6 +1827,7 @@ { ISD::UADDSAT, MVT::v32i8, 1 }, { ISD::USUBSAT, MVT::v16i16, 1 }, { ISD::USUBSAT, MVT::v32i8, 1 }, + { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/ { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/ { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ @@ -1858,6 +1863,7 @@ { ISD::UADDSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert + { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ @@ -1878,6 +1884,7 @@ { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd }; static const CostTblEntry SSE42CostTbl[] = { + { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd { ISD::FSQRT, MVT::f32, 18 }, // Nehalem from http://www.agner.org/ { ISD::FSQRT, MVT::v4f32, 18 }, // Nehalem from http://www.agner.org/ }; Index: test/Analysis/CostModel/X86/arith-usat.ll =================================================================== --- test/Analysis/CostModel/X86/arith-usat.ll +++ test/Analysis/CostModel/X86/arith-usat.ll @@ -250,24 +250,43 @@ declare <64 x i8> @llvm.usub.sat.v64i8(<64 x i8>, <64 x i8>) define i32 @sub(i32 %arg) { -; SSE-LABEL: 'sub' -; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call i64 @llvm.usub.sat.i64(i64 undef, i64 undef) -; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> undef, <2 x i64> undef) -; SSE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) -; SSE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) -; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.usub.sat.i32(i32 undef, i32 undef) -; SSE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) -; SSE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) -; SSE-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) -; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.usub.sat.i16(i16 undef, i16 undef) -; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) -; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) -; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32I16 = call <32 x i16> @llvm.usub.sat.v32i16(<32 x i16> undef, <32 x i16> undef) -; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.usub.sat.i8(i8 undef, i8 undef) -; SSE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> undef, <16 x i8> undef) -; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I8 = call <32 x i8> @llvm.usub.sat.v32i8(<32 x i8> undef, <32 x i8> undef) -; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V64I8 = call <64 x i8> @llvm.usub.sat.v64i8(<64 x i8> undef, <64 x i8> undef) -; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef +; SSSE3-LABEL: 'sub' +; SSSE3-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call i64 @llvm.usub.sat.i64(i64 undef, i64 undef) +; SSSE3-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> undef, <2 x i64> undef) +; SSSE3-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) +; SSSE3-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) +; SSSE3-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.usub.sat.i32(i32 undef, i32 undef) +; SSSE3-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) +; SSSE3-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) +; SSSE3-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) +; SSSE3-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.usub.sat.i16(i16 undef, i16 undef) +; SSSE3-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) +; SSSE3-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32I16 = call <32 x i16> @llvm.usub.sat.v32i16(<32 x i16> undef, <32 x i16> undef) +; SSSE3-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.usub.sat.i8(i8 undef, i8 undef) +; SSSE3-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> undef, <16 x i8> undef) +; SSSE3-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I8 = call <32 x i8> @llvm.usub.sat.v32i8(<32 x i8> undef, <32 x i8> undef) +; SSSE3-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V64I8 = call <64 x i8> @llvm.usub.sat.v64i8(<64 x i8> undef, <64 x i8> undef) +; SSSE3-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef +; +; SSE42-LABEL: 'sub' +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call i64 @llvm.usub.sat.i64(i64 undef, i64 undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> undef, <2 x i64> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.usub.sat.i32(i32 undef, i32 undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.usub.sat.i16(i16 undef, i16 undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32I16 = call <32 x i16> @llvm.usub.sat.v32i16(<32 x i16> undef, <32 x i16> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = call i8 @llvm.usub.sat.i8(i8 undef, i8 undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> undef, <16 x i8> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I8 = call <32 x i8> @llvm.usub.sat.v32i8(<32 x i8> undef, <32 x i8> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V64I8 = call <64 x i8> @llvm.usub.sat.v64i8(<64 x i8> undef, <64 x i8> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; AVX1-LABEL: 'sub' ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call i64 @llvm.usub.sat.i64(i64 undef, i64 undef) @@ -275,9 +294,9 @@ ; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.usub.sat.i32(i32 undef, i32 undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.usub.sat.i16(i16 undef, i16 undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16I16 = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) @@ -294,9 +313,9 @@ ; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.usub.sat.i32(i32 undef, i32 undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.usub.sat.i16(i16 undef, i16 undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) @@ -309,13 +328,13 @@ ; ; AVX512F-LABEL: 'sub' ; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call i64 @llvm.usub.sat.i64(i64 undef, i64 undef) -; AVX512F-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> undef, <2 x i64> undef) -; AVX512F-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) -; AVX512F-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) +; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I64 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> undef, <2 x i64> undef) +; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) +; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) ; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.usub.sat.i32(i32 undef, i32 undef) -; AVX512F-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) -; AVX512F-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) -; AVX512F-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) +; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) +; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) +; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) ; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.usub.sat.i16(i16 undef, i16 undef) ; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) ; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) @@ -328,13 +347,13 @@ ; ; AVX512BW-LABEL: 'sub' ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call i64 @llvm.usub.sat.i64(i64 undef, i64 undef) -; AVX512BW-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> undef, <2 x i64> undef) -; AVX512BW-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) -; AVX512BW-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) +; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I64 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> undef, <2 x i64> undef) +; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) +; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.usub.sat.i32(i32 undef, i32 undef) -; AVX512BW-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) -; AVX512BW-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) -; AVX512BW-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) +; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) +; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) +; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.usub.sat.i16(i16 undef, i16 undef) ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) @@ -347,13 +366,13 @@ ; ; AVX512DQ-LABEL: 'sub' ; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I64 = call i64 @llvm.usub.sat.i64(i64 undef, i64 undef) -; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> undef, <2 x i64> undef) -; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) -; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) +; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I64 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> undef, <2 x i64> undef) +; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) +; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) ; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.usub.sat.i32(i32 undef, i32 undef) -; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) -; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) -; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) +; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) +; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) +; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) ; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.usub.sat.i16(i16 undef, i16 undef) ; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) ; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) @@ -370,9 +389,9 @@ ; SLM-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) ; SLM-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) ; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.usub.sat.i32(i32 undef, i32 undef) -; SLM-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) -; SLM-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) -; SLM-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) +; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) +; SLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) +; SLM-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) ; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.usub.sat.i16(i16 undef, i16 undef) ; SLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) ; SLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) @@ -389,9 +408,9 @@ ; GLM-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) ; GLM-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) ; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.usub.sat.i32(i32 undef, i32 undef) -; GLM-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) -; GLM-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) -; GLM-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) +; GLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) +; GLM-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) +; GLM-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) ; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.usub.sat.i16(i16 undef, i16 undef) ; GLM-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) ; GLM-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) @@ -408,9 +427,9 @@ ; BTVER2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I64 = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> undef, <4 x i64> undef) ; BTVER2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I64 = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> undef, <8 x i64> undef) ; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = call i32 @llvm.usub.sat.i32(i32 undef, i32 undef) -; BTVER2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) -; BTVER2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) -; BTVER2-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) +; BTVER2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> undef, <4 x i32> undef) +; BTVER2-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8I32 = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> undef, <8 x i32> undef) +; BTVER2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V16I32 = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> undef, <16 x i32> undef) ; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = call i16 @llvm.usub.sat.i16(i16 undef, i16 undef) ; BTVER2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> undef, <8 x i16> undef) ; BTVER2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16I16 = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> undef, <16 x i16> undef) Index: test/CodeGen/X86/usub_sat_vec.ll =================================================================== --- test/CodeGen/X86/usub_sat_vec.ll +++ test/CodeGen/X86/usub_sat_vec.ll @@ -694,24 +694,52 @@ ; SSE41-NEXT: psrlq $32, %xmm0 ; SSE41-NEXT: retq ; -; AVX-LABEL: v2i32: -; AVX: # %bb.0: -; AVX-NEXT: vpsllq $32, %xmm1, %xmm1 -; AVX-NEXT: vpextrq $1, %xmm1, %rax -; AVX-NEXT: vpsllq $32, %xmm0, %xmm0 -; AVX-NEXT: vpextrq $1, %xmm0, %rcx -; AVX-NEXT: xorl %edx, %edx -; AVX-NEXT: subq %rax, %rcx -; AVX-NEXT: cmovbq %rdx, %rcx -; AVX-NEXT: vmovq %rcx, %xmm2 -; AVX-NEXT: vmovq %xmm1, %rax -; AVX-NEXT: vmovq %xmm0, %rcx -; AVX-NEXT: subq %rax, %rcx -; AVX-NEXT: cmovbq %rdx, %rcx -; AVX-NEXT: vmovq %rcx, %xmm0 -; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] -; AVX-NEXT: vpsrlq $32, %xmm0, %xmm0 -; AVX-NEXT: retq +; AVX1-LABEL: v2i32: +; AVX1: # %bb.0: +; AVX1-NEXT: vpsllq $32, %xmm1, %xmm1 +; AVX1-NEXT: vpextrq $1, %xmm1, %rax +; AVX1-NEXT: vpsllq $32, %xmm0, %xmm0 +; AVX1-NEXT: vpextrq $1, %xmm0, %rcx +; AVX1-NEXT: xorl %edx, %edx +; AVX1-NEXT: subq %rax, %rcx +; AVX1-NEXT: cmovbq %rdx, %rcx +; AVX1-NEXT: vmovq %rcx, %xmm2 +; AVX1-NEXT: vmovq %xmm1, %rax +; AVX1-NEXT: vmovq %xmm0, %rcx +; AVX1-NEXT: subq %rax, %rcx +; AVX1-NEXT: cmovbq %rdx, %rcx +; AVX1-NEXT: vmovq %rcx, %xmm0 +; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] +; AVX1-NEXT: vpsrlq $32, %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: v2i32: +; AVX2: # %bb.0: +; AVX2-NEXT: vpsllq $32, %xmm1, %xmm1 +; AVX2-NEXT: vpextrq $1, %xmm1, %rax +; AVX2-NEXT: vpsllq $32, %xmm0, %xmm0 +; AVX2-NEXT: vpextrq $1, %xmm0, %rcx +; AVX2-NEXT: xorl %edx, %edx +; AVX2-NEXT: subq %rax, %rcx +; AVX2-NEXT: cmovbq %rdx, %rcx +; AVX2-NEXT: vmovq %rcx, %xmm2 +; AVX2-NEXT: vmovq %xmm1, %rax +; AVX2-NEXT: vmovq %xmm0, %rcx +; AVX2-NEXT: subq %rax, %rcx +; AVX2-NEXT: cmovbq %rdx, %rcx +; AVX2-NEXT: vmovq %rcx, %xmm0 +; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] +; AVX2-NEXT: vpsrlq $32, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: v2i32: +; AVX512: # %bb.0: +; AVX512-NEXT: vpsllq $32, %xmm1, %xmm1 +; AVX512-NEXT: vpsllq $32, %xmm0, %xmm0 +; AVX512-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: vpsubq %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: vpsrlq $32, %xmm0, %xmm0 +; AVX512-NEXT: retq %z = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %x, <2 x i32> %y) ret <2 x i32> %z } @@ -789,53 +817,14 @@ ; ; SSE41-LABEL: v4i32: ; SSE41: # %bb.0: -; SSE41-NEXT: pextrd $1, %xmm1, %eax -; SSE41-NEXT: pextrd $1, %xmm0, %ecx -; SSE41-NEXT: xorl %edx, %edx -; SSE41-NEXT: subl %eax, %ecx -; SSE41-NEXT: cmovbl %edx, %ecx -; SSE41-NEXT: movd %xmm1, %eax -; SSE41-NEXT: movd %xmm0, %esi -; SSE41-NEXT: subl %eax, %esi -; SSE41-NEXT: cmovbl %edx, %esi -; SSE41-NEXT: movd %esi, %xmm2 -; SSE41-NEXT: pinsrd $1, %ecx, %xmm2 -; SSE41-NEXT: pextrd $2, %xmm1, %eax -; SSE41-NEXT: pextrd $2, %xmm0, %ecx -; SSE41-NEXT: subl %eax, %ecx -; SSE41-NEXT: cmovbl %edx, %ecx -; SSE41-NEXT: pinsrd $2, %ecx, %xmm2 -; SSE41-NEXT: pextrd $3, %xmm1, %eax -; SSE41-NEXT: pextrd $3, %xmm0, %ecx -; SSE41-NEXT: subl %eax, %ecx -; SSE41-NEXT: cmovbl %edx, %ecx -; SSE41-NEXT: pinsrd $3, %ecx, %xmm2 -; SSE41-NEXT: movdqa %xmm2, %xmm0 +; SSE41-NEXT: pmaxud %xmm1, %xmm0 +; SSE41-NEXT: psubd %xmm1, %xmm0 ; SSE41-NEXT: retq ; ; AVX-LABEL: v4i32: ; AVX: # %bb.0: -; AVX-NEXT: vpextrd $1, %xmm1, %eax -; AVX-NEXT: vpextrd $1, %xmm0, %ecx -; AVX-NEXT: xorl %edx, %edx -; AVX-NEXT: subl %eax, %ecx -; AVX-NEXT: cmovbl %edx, %ecx -; AVX-NEXT: vmovd %xmm1, %eax -; AVX-NEXT: vmovd %xmm0, %esi -; AVX-NEXT: subl %eax, %esi -; AVX-NEXT: cmovbl %edx, %esi -; AVX-NEXT: vmovd %esi, %xmm2 -; AVX-NEXT: vpinsrd $1, %ecx, %xmm2, %xmm2 -; AVX-NEXT: vpextrd $2, %xmm1, %eax -; AVX-NEXT: vpextrd $2, %xmm0, %ecx -; AVX-NEXT: subl %eax, %ecx -; AVX-NEXT: cmovbl %edx, %ecx -; AVX-NEXT: vpinsrd $2, %ecx, %xmm2, %xmm2 -; AVX-NEXT: vpextrd $3, %xmm1, %eax -; AVX-NEXT: vpextrd $3, %xmm0, %ecx -; AVX-NEXT: subl %eax, %ecx -; AVX-NEXT: cmovbl %edx, %ecx -; AVX-NEXT: vpinsrd $3, %ecx, %xmm2, %xmm0 +; AVX-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0 ; AVX-NEXT: retq %z = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %x, <4 x i32> %y) ret <4 x i32> %z @@ -974,193 +963,33 @@ ; ; SSE41-LABEL: v8i32: ; SSE41: # %bb.0: -; SSE41-NEXT: movdqa %xmm0, %xmm4 -; SSE41-NEXT: pextrd $1, %xmm2, %ecx -; SSE41-NEXT: pextrd $1, %xmm0, %edx -; SSE41-NEXT: xorl %eax, %eax -; SSE41-NEXT: subl %ecx, %edx -; SSE41-NEXT: cmovbl %eax, %edx -; SSE41-NEXT: movd %xmm2, %ecx -; SSE41-NEXT: movd %xmm0, %esi -; SSE41-NEXT: subl %ecx, %esi -; SSE41-NEXT: cmovbl %eax, %esi -; SSE41-NEXT: movd %esi, %xmm0 -; SSE41-NEXT: pinsrd $1, %edx, %xmm0 -; SSE41-NEXT: pextrd $2, %xmm2, %ecx -; SSE41-NEXT: pextrd $2, %xmm4, %edx -; SSE41-NEXT: subl %ecx, %edx -; SSE41-NEXT: cmovbl %eax, %edx -; SSE41-NEXT: pinsrd $2, %edx, %xmm0 -; SSE41-NEXT: pextrd $3, %xmm2, %ecx -; SSE41-NEXT: pextrd $3, %xmm4, %edx -; SSE41-NEXT: subl %ecx, %edx -; SSE41-NEXT: cmovbl %eax, %edx -; SSE41-NEXT: pinsrd $3, %edx, %xmm0 -; SSE41-NEXT: pextrd $1, %xmm3, %ecx -; SSE41-NEXT: pextrd $1, %xmm1, %edx -; SSE41-NEXT: subl %ecx, %edx -; SSE41-NEXT: cmovbl %eax, %edx -; SSE41-NEXT: movd %xmm3, %ecx -; SSE41-NEXT: movd %xmm1, %esi -; SSE41-NEXT: subl %ecx, %esi -; SSE41-NEXT: cmovbl %eax, %esi -; SSE41-NEXT: movd %esi, %xmm2 -; SSE41-NEXT: pinsrd $1, %edx, %xmm2 -; SSE41-NEXT: pextrd $2, %xmm3, %ecx -; SSE41-NEXT: pextrd $2, %xmm1, %edx -; SSE41-NEXT: subl %ecx, %edx -; SSE41-NEXT: cmovbl %eax, %edx -; SSE41-NEXT: pinsrd $2, %edx, %xmm2 -; SSE41-NEXT: pextrd $3, %xmm3, %ecx -; SSE41-NEXT: pextrd $3, %xmm1, %edx -; SSE41-NEXT: subl %ecx, %edx -; SSE41-NEXT: cmovbl %eax, %edx -; SSE41-NEXT: pinsrd $3, %edx, %xmm2 -; SSE41-NEXT: movdqa %xmm2, %xmm1 +; SSE41-NEXT: pmaxud %xmm2, %xmm0 +; SSE41-NEXT: psubd %xmm2, %xmm0 +; SSE41-NEXT: pmaxud %xmm3, %xmm1 +; SSE41-NEXT: psubd %xmm3, %xmm1 ; SSE41-NEXT: retq ; ; AVX1-LABEL: v8i32: ; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 -; AVX1-NEXT: vpextrd $1, %xmm2, %ecx ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 -; AVX1-NEXT: vpextrd $1, %xmm3, %edx -; AVX1-NEXT: xorl %eax, %eax -; AVX1-NEXT: subl %ecx, %edx -; AVX1-NEXT: cmovbl %eax, %edx -; AVX1-NEXT: vmovd %xmm2, %ecx -; AVX1-NEXT: vmovd %xmm3, %esi -; AVX1-NEXT: subl %ecx, %esi -; AVX1-NEXT: cmovbl %eax, %esi -; AVX1-NEXT: vmovd %esi, %xmm4 -; AVX1-NEXT: vpinsrd $1, %edx, %xmm4, %xmm4 -; AVX1-NEXT: vpextrd $2, %xmm2, %ecx -; AVX1-NEXT: vpextrd $2, %xmm3, %edx -; AVX1-NEXT: subl %ecx, %edx -; AVX1-NEXT: cmovbl %eax, %edx -; AVX1-NEXT: vpinsrd $2, %edx, %xmm4, %xmm4 -; AVX1-NEXT: vpextrd $3, %xmm2, %ecx -; AVX1-NEXT: vpextrd $3, %xmm3, %edx -; AVX1-NEXT: subl %ecx, %edx -; AVX1-NEXT: cmovbl %eax, %edx -; AVX1-NEXT: vpinsrd $3, %edx, %xmm4, %xmm2 -; AVX1-NEXT: vpextrd $1, %xmm1, %ecx -; AVX1-NEXT: vpextrd $1, %xmm0, %edx -; AVX1-NEXT: subl %ecx, %edx -; AVX1-NEXT: cmovbl %eax, %edx -; AVX1-NEXT: vmovd %xmm1, %ecx -; AVX1-NEXT: vmovd %xmm0, %esi -; AVX1-NEXT: subl %ecx, %esi -; AVX1-NEXT: cmovbl %eax, %esi -; AVX1-NEXT: vmovd %esi, %xmm3 -; AVX1-NEXT: vpinsrd $1, %edx, %xmm3, %xmm3 -; AVX1-NEXT: vpextrd $2, %xmm1, %ecx -; AVX1-NEXT: vpextrd $2, %xmm0, %edx -; AVX1-NEXT: subl %ecx, %edx -; AVX1-NEXT: cmovbl %eax, %edx -; AVX1-NEXT: vpinsrd $2, %edx, %xmm3, %xmm3 -; AVX1-NEXT: vpextrd $3, %xmm1, %ecx -; AVX1-NEXT: vpextrd $3, %xmm0, %edx -; AVX1-NEXT: subl %ecx, %edx -; AVX1-NEXT: cmovbl %eax, %edx -; AVX1-NEXT: vpinsrd $3, %edx, %xmm3, %xmm0 +; AVX1-NEXT: vpmaxud %xmm2, %xmm3, %xmm3 +; AVX1-NEXT: vpsubd %xmm2, %xmm3, %xmm2 +; AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; AVX1-NEXT: retq ; ; AVX2-LABEL: v8i32: ; AVX2: # %bb.0: -; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2 -; AVX2-NEXT: vpextrd $1, %xmm2, %ecx -; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm3 -; AVX2-NEXT: vpextrd $1, %xmm3, %edx -; AVX2-NEXT: xorl %eax, %eax -; AVX2-NEXT: subl %ecx, %edx -; AVX2-NEXT: cmovbl %eax, %edx -; AVX2-NEXT: vmovd %xmm2, %ecx -; AVX2-NEXT: vmovd %xmm3, %esi -; AVX2-NEXT: subl %ecx, %esi -; AVX2-NEXT: cmovbl %eax, %esi -; AVX2-NEXT: vmovd %esi, %xmm4 -; AVX2-NEXT: vpinsrd $1, %edx, %xmm4, %xmm4 -; AVX2-NEXT: vpextrd $2, %xmm2, %ecx -; AVX2-NEXT: vpextrd $2, %xmm3, %edx -; AVX2-NEXT: subl %ecx, %edx -; AVX2-NEXT: cmovbl %eax, %edx -; AVX2-NEXT: vpinsrd $2, %edx, %xmm4, %xmm4 -; AVX2-NEXT: vpextrd $3, %xmm2, %ecx -; AVX2-NEXT: vpextrd $3, %xmm3, %edx -; AVX2-NEXT: subl %ecx, %edx -; AVX2-NEXT: cmovbl %eax, %edx -; AVX2-NEXT: vpinsrd $3, %edx, %xmm4, %xmm2 -; AVX2-NEXT: vpextrd $1, %xmm1, %ecx -; AVX2-NEXT: vpextrd $1, %xmm0, %edx -; AVX2-NEXT: subl %ecx, %edx -; AVX2-NEXT: cmovbl %eax, %edx -; AVX2-NEXT: vmovd %xmm1, %ecx -; AVX2-NEXT: vmovd %xmm0, %esi -; AVX2-NEXT: subl %ecx, %esi -; AVX2-NEXT: cmovbl %eax, %esi -; AVX2-NEXT: vmovd %esi, %xmm3 -; AVX2-NEXT: vpinsrd $1, %edx, %xmm3, %xmm3 -; AVX2-NEXT: vpextrd $2, %xmm1, %ecx -; AVX2-NEXT: vpextrd $2, %xmm0, %edx -; AVX2-NEXT: subl %ecx, %edx -; AVX2-NEXT: cmovbl %eax, %edx -; AVX2-NEXT: vpinsrd $2, %edx, %xmm3, %xmm3 -; AVX2-NEXT: vpextrd $3, %xmm1, %ecx -; AVX2-NEXT: vpextrd $3, %xmm0, %edx -; AVX2-NEXT: subl %ecx, %edx -; AVX2-NEXT: cmovbl %eax, %edx -; AVX2-NEXT: vpinsrd $3, %edx, %xmm3, %xmm0 -; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0 +; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vpsubd %ymm1, %ymm0, %ymm0 ; AVX2-NEXT: retq ; ; AVX512-LABEL: v8i32: ; AVX512: # %bb.0: -; AVX512-NEXT: vextracti128 $1, %ymm1, %xmm2 -; AVX512-NEXT: vpextrd $1, %xmm2, %ecx -; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm3 -; AVX512-NEXT: vpextrd $1, %xmm3, %edx -; AVX512-NEXT: xorl %eax, %eax -; AVX512-NEXT: subl %ecx, %edx -; AVX512-NEXT: cmovbl %eax, %edx -; AVX512-NEXT: vmovd %xmm2, %ecx -; AVX512-NEXT: vmovd %xmm3, %esi -; AVX512-NEXT: subl %ecx, %esi -; AVX512-NEXT: cmovbl %eax, %esi -; AVX512-NEXT: vmovd %esi, %xmm4 -; AVX512-NEXT: vpinsrd $1, %edx, %xmm4, %xmm4 -; AVX512-NEXT: vpextrd $2, %xmm2, %ecx -; AVX512-NEXT: vpextrd $2, %xmm3, %edx -; AVX512-NEXT: subl %ecx, %edx -; AVX512-NEXT: cmovbl %eax, %edx -; AVX512-NEXT: vpinsrd $2, %edx, %xmm4, %xmm4 -; AVX512-NEXT: vpextrd $3, %xmm2, %ecx -; AVX512-NEXT: vpextrd $3, %xmm3, %edx -; AVX512-NEXT: subl %ecx, %edx -; AVX512-NEXT: cmovbl %eax, %edx -; AVX512-NEXT: vpinsrd $3, %edx, %xmm4, %xmm2 -; AVX512-NEXT: vpextrd $1, %xmm1, %ecx -; AVX512-NEXT: vpextrd $1, %xmm0, %edx -; AVX512-NEXT: subl %ecx, %edx -; AVX512-NEXT: cmovbl %eax, %edx -; AVX512-NEXT: vmovd %xmm1, %ecx -; AVX512-NEXT: vmovd %xmm0, %esi -; AVX512-NEXT: subl %ecx, %esi -; AVX512-NEXT: cmovbl %eax, %esi -; AVX512-NEXT: vmovd %esi, %xmm3 -; AVX512-NEXT: vpinsrd $1, %edx, %xmm3, %xmm3 -; AVX512-NEXT: vpextrd $2, %xmm1, %ecx -; AVX512-NEXT: vpextrd $2, %xmm0, %edx -; AVX512-NEXT: subl %ecx, %edx -; AVX512-NEXT: cmovbl %eax, %edx -; AVX512-NEXT: vpinsrd $2, %edx, %xmm3, %xmm3 -; AVX512-NEXT: vpextrd $3, %xmm1, %ecx -; AVX512-NEXT: vpextrd $3, %xmm0, %edx -; AVX512-NEXT: subl %ecx, %edx -; AVX512-NEXT: cmovbl %eax, %edx -; AVX512-NEXT: vpinsrd $3, %edx, %xmm3, %xmm0 -; AVX512-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0 +; AVX512-NEXT: vpmaxud %ymm1, %ymm0, %ymm0 +; AVX512-NEXT: vpsubd %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: retq %z = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> %x, <8 x i32> %y) ret <8 x i32> %z @@ -1419,367 +1248,46 @@ ; ; SSE41-LABEL: v16i32: ; SSE41: # %bb.0: -; SSE41-NEXT: movdqa %xmm1, %xmm8 -; SSE41-NEXT: movdqa %xmm0, %xmm1 -; SSE41-NEXT: pextrd $1, %xmm4, %ecx -; SSE41-NEXT: pextrd $1, %xmm0, %edx -; SSE41-NEXT: xorl %eax, %eax -; SSE41-NEXT: subl %ecx, %edx -; SSE41-NEXT: cmovbl %eax, %edx -; SSE41-NEXT: movd %xmm4, %ecx -; SSE41-NEXT: movd %xmm0, %esi -; SSE41-NEXT: subl %ecx, %esi -; SSE41-NEXT: cmovbl %eax, %esi -; SSE41-NEXT: movd %esi, %xmm0 -; SSE41-NEXT: pinsrd $1, %edx, %xmm0 -; SSE41-NEXT: pextrd $2, %xmm4, %ecx -; SSE41-NEXT: pextrd $2, %xmm1, %edx -; SSE41-NEXT: subl %ecx, %edx -; SSE41-NEXT: cmovbl %eax, %edx -; SSE41-NEXT: pinsrd $2, %edx, %xmm0 -; SSE41-NEXT: pextrd $3, %xmm4, %ecx -; SSE41-NEXT: pextrd $3, %xmm1, %edx -; SSE41-NEXT: subl %ecx, %edx -; SSE41-NEXT: cmovbl %eax, %edx -; SSE41-NEXT: pinsrd $3, %edx, %xmm0 -; SSE41-NEXT: pextrd $1, %xmm5, %ecx -; SSE41-NEXT: pextrd $1, %xmm8, %edx -; SSE41-NEXT: subl %ecx, %edx -; SSE41-NEXT: cmovbl %eax, %edx -; SSE41-NEXT: movd %xmm5, %ecx -; SSE41-NEXT: movd %xmm8, %esi -; SSE41-NEXT: subl %ecx, %esi -; SSE41-NEXT: cmovbl %eax, %esi -; SSE41-NEXT: movd %esi, %xmm1 -; SSE41-NEXT: pinsrd $1, %edx, %xmm1 -; SSE41-NEXT: pextrd $2, %xmm5, %ecx -; SSE41-NEXT: pextrd $2, %xmm8, %edx -; SSE41-NEXT: subl %ecx, %edx -; SSE41-NEXT: cmovbl %eax, %edx -; SSE41-NEXT: pinsrd $2, %edx, %xmm1 -; SSE41-NEXT: pextrd $3, %xmm5, %ecx -; SSE41-NEXT: pextrd $3, %xmm8, %edx -; SSE41-NEXT: subl %ecx, %edx -; SSE41-NEXT: cmovbl %eax, %edx -; SSE41-NEXT: pinsrd $3, %edx, %xmm1 -; SSE41-NEXT: pextrd $1, %xmm6, %ecx -; SSE41-NEXT: pextrd $1, %xmm2, %edx -; SSE41-NEXT: subl %ecx, %edx -; SSE41-NEXT: cmovbl %eax, %edx -; SSE41-NEXT: movd %xmm6, %ecx -; SSE41-NEXT: movd %xmm2, %esi -; SSE41-NEXT: subl %ecx, %esi -; SSE41-NEXT: cmovbl %eax, %esi -; SSE41-NEXT: movd %esi, %xmm4 -; SSE41-NEXT: pinsrd $1, %edx, %xmm4 -; SSE41-NEXT: pextrd $2, %xmm6, %ecx -; SSE41-NEXT: pextrd $2, %xmm2, %edx -; SSE41-NEXT: subl %ecx, %edx -; SSE41-NEXT: cmovbl %eax, %edx -; SSE41-NEXT: pinsrd $2, %edx, %xmm4 -; SSE41-NEXT: pextrd $3, %xmm6, %ecx -; SSE41-NEXT: pextrd $3, %xmm2, %edx -; SSE41-NEXT: subl %ecx, %edx -; SSE41-NEXT: cmovbl %eax, %edx -; SSE41-NEXT: pinsrd $3, %edx, %xmm4 -; SSE41-NEXT: pextrd $1, %xmm7, %ecx -; SSE41-NEXT: pextrd $1, %xmm3, %edx -; SSE41-NEXT: subl %ecx, %edx -; SSE41-NEXT: cmovbl %eax, %edx -; SSE41-NEXT: movd %xmm7, %ecx -; SSE41-NEXT: movd %xmm3, %esi -; SSE41-NEXT: subl %ecx, %esi -; SSE41-NEXT: cmovbl %eax, %esi -; SSE41-NEXT: movd %esi, %xmm5 -; SSE41-NEXT: pinsrd $1, %edx, %xmm5 -; SSE41-NEXT: pextrd $2, %xmm7, %ecx -; SSE41-NEXT: pextrd $2, %xmm3, %edx -; SSE41-NEXT: subl %ecx, %edx -; SSE41-NEXT: cmovbl %eax, %edx -; SSE41-NEXT: pinsrd $2, %edx, %xmm5 -; SSE41-NEXT: pextrd $3, %xmm7, %ecx -; SSE41-NEXT: pextrd $3, %xmm3, %edx -; SSE41-NEXT: subl %ecx, %edx -; SSE41-NEXT: cmovbl %eax, %edx -; SSE41-NEXT: pinsrd $3, %edx, %xmm5 -; SSE41-NEXT: movdqa %xmm4, %xmm2 -; SSE41-NEXT: movdqa %xmm5, %xmm3 +; SSE41-NEXT: pmaxud %xmm4, %xmm0 +; SSE41-NEXT: psubd %xmm4, %xmm0 +; SSE41-NEXT: pmaxud %xmm5, %xmm1 +; SSE41-NEXT: psubd %xmm5, %xmm1 +; SSE41-NEXT: pmaxud %xmm6, %xmm2 +; SSE41-NEXT: psubd %xmm6, %xmm2 +; SSE41-NEXT: pmaxud %xmm7, %xmm3 +; SSE41-NEXT: psubd %xmm7, %xmm3 ; SSE41-NEXT: retq ; ; AVX1-LABEL: v16i32: ; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4 -; AVX1-NEXT: vpextrd $1, %xmm4, %ecx ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5 -; AVX1-NEXT: vpextrd $1, %xmm5, %edx -; AVX1-NEXT: xorl %eax, %eax -; AVX1-NEXT: subl %ecx, %edx -; AVX1-NEXT: cmovbl %eax, %edx -; AVX1-NEXT: vmovd %xmm4, %ecx -; AVX1-NEXT: vmovd %xmm5, %esi -; AVX1-NEXT: subl %ecx, %esi -; AVX1-NEXT: cmovbl %eax, %esi -; AVX1-NEXT: vmovd %esi, %xmm6 -; AVX1-NEXT: vpinsrd $1, %edx, %xmm6, %xmm6 -; AVX1-NEXT: vpextrd $2, %xmm4, %ecx -; AVX1-NEXT: vpextrd $2, %xmm5, %edx -; AVX1-NEXT: subl %ecx, %edx -; AVX1-NEXT: cmovbl %eax, %edx -; AVX1-NEXT: vpinsrd $2, %edx, %xmm6, %xmm6 -; AVX1-NEXT: vpextrd $3, %xmm4, %ecx -; AVX1-NEXT: vpextrd $3, %xmm5, %edx -; AVX1-NEXT: subl %ecx, %edx -; AVX1-NEXT: cmovbl %eax, %edx -; AVX1-NEXT: vpinsrd $3, %edx, %xmm6, %xmm4 -; AVX1-NEXT: vpextrd $1, %xmm2, %ecx -; AVX1-NEXT: vpextrd $1, %xmm0, %edx -; AVX1-NEXT: subl %ecx, %edx -; AVX1-NEXT: cmovbl %eax, %edx -; AVX1-NEXT: vmovd %xmm2, %ecx -; AVX1-NEXT: vmovd %xmm0, %esi -; AVX1-NEXT: subl %ecx, %esi -; AVX1-NEXT: cmovbl %eax, %esi -; AVX1-NEXT: vmovd %esi, %xmm5 -; AVX1-NEXT: vpinsrd $1, %edx, %xmm5, %xmm5 -; AVX1-NEXT: vpextrd $2, %xmm2, %ecx -; AVX1-NEXT: vpextrd $2, %xmm0, %edx -; AVX1-NEXT: subl %ecx, %edx -; AVX1-NEXT: cmovbl %eax, %edx -; AVX1-NEXT: vpinsrd $2, %edx, %xmm5, %xmm5 -; AVX1-NEXT: vpextrd $3, %xmm2, %ecx -; AVX1-NEXT: vpextrd $3, %xmm0, %edx -; AVX1-NEXT: subl %ecx, %edx -; AVX1-NEXT: cmovbl %eax, %edx -; AVX1-NEXT: vpinsrd $3, %edx, %xmm5, %xmm0 +; AVX1-NEXT: vpmaxud %xmm4, %xmm5, %xmm5 +; AVX1-NEXT: vpsubd %xmm4, %xmm5, %xmm4 +; AVX1-NEXT: vpmaxud %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpsubd %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm2 -; AVX1-NEXT: vpextrd $1, %xmm2, %ecx ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4 -; AVX1-NEXT: vpextrd $1, %xmm4, %edx -; AVX1-NEXT: subl %ecx, %edx -; AVX1-NEXT: cmovbl %eax, %edx -; AVX1-NEXT: vmovd %xmm2, %ecx -; AVX1-NEXT: vmovd %xmm4, %esi -; AVX1-NEXT: subl %ecx, %esi -; AVX1-NEXT: cmovbl %eax, %esi -; AVX1-NEXT: vmovd %esi, %xmm5 -; AVX1-NEXT: vpinsrd $1, %edx, %xmm5, %xmm5 -; AVX1-NEXT: vpextrd $2, %xmm2, %ecx -; AVX1-NEXT: vpextrd $2, %xmm4, %edx -; AVX1-NEXT: subl %ecx, %edx -; AVX1-NEXT: cmovbl %eax, %edx -; AVX1-NEXT: vpinsrd $2, %edx, %xmm5, %xmm5 -; AVX1-NEXT: vpextrd $3, %xmm2, %ecx -; AVX1-NEXT: vpextrd $3, %xmm4, %edx -; AVX1-NEXT: subl %ecx, %edx -; AVX1-NEXT: cmovbl %eax, %edx -; AVX1-NEXT: vpinsrd $3, %edx, %xmm5, %xmm2 -; AVX1-NEXT: vpextrd $1, %xmm3, %ecx -; AVX1-NEXT: vpextrd $1, %xmm1, %edx -; AVX1-NEXT: subl %ecx, %edx -; AVX1-NEXT: cmovbl %eax, %edx -; AVX1-NEXT: vmovd %xmm3, %ecx -; AVX1-NEXT: vmovd %xmm1, %esi -; AVX1-NEXT: subl %ecx, %esi -; AVX1-NEXT: cmovbl %eax, %esi -; AVX1-NEXT: vmovd %esi, %xmm4 -; AVX1-NEXT: vpinsrd $1, %edx, %xmm4, %xmm4 -; AVX1-NEXT: vpextrd $2, %xmm3, %ecx -; AVX1-NEXT: vpextrd $2, %xmm1, %edx -; AVX1-NEXT: subl %ecx, %edx -; AVX1-NEXT: cmovbl %eax, %edx -; AVX1-NEXT: vpinsrd $2, %edx, %xmm4, %xmm4 -; AVX1-NEXT: vpextrd $3, %xmm3, %ecx -; AVX1-NEXT: vpextrd $3, %xmm1, %edx -; AVX1-NEXT: subl %ecx, %edx -; AVX1-NEXT: cmovbl %eax, %edx -; AVX1-NEXT: vpinsrd $3, %edx, %xmm4, %xmm1 +; AVX1-NEXT: vpmaxud %xmm2, %xmm4, %xmm4 +; AVX1-NEXT: vpsubd %xmm2, %xmm4, %xmm2 +; AVX1-NEXT: vpmaxud %xmm3, %xmm1, %xmm1 +; AVX1-NEXT: vpsubd %xmm3, %xmm1, %xmm1 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 ; AVX1-NEXT: retq ; ; AVX2-LABEL: v16i32: ; AVX2: # %bb.0: -; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm4 -; AVX2-NEXT: vpextrd $1, %xmm4, %ecx -; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm5 -; AVX2-NEXT: vpextrd $1, %xmm5, %edx -; AVX2-NEXT: xorl %eax, %eax -; AVX2-NEXT: subl %ecx, %edx -; AVX2-NEXT: cmovbl %eax, %edx -; AVX2-NEXT: vmovd %xmm4, %ecx -; AVX2-NEXT: vmovd %xmm5, %esi -; AVX2-NEXT: subl %ecx, %esi -; AVX2-NEXT: cmovbl %eax, %esi -; AVX2-NEXT: vmovd %esi, %xmm6 -; AVX2-NEXT: vpinsrd $1, %edx, %xmm6, %xmm6 -; AVX2-NEXT: vpextrd $2, %xmm4, %ecx -; AVX2-NEXT: vpextrd $2, %xmm5, %edx -; AVX2-NEXT: subl %ecx, %edx -; AVX2-NEXT: cmovbl %eax, %edx -; AVX2-NEXT: vpinsrd $2, %edx, %xmm6, %xmm6 -; AVX2-NEXT: vpextrd $3, %xmm4, %ecx -; AVX2-NEXT: vpextrd $3, %xmm5, %edx -; AVX2-NEXT: subl %ecx, %edx -; AVX2-NEXT: cmovbl %eax, %edx -; AVX2-NEXT: vpinsrd $3, %edx, %xmm6, %xmm4 -; AVX2-NEXT: vpextrd $1, %xmm2, %ecx -; AVX2-NEXT: vpextrd $1, %xmm0, %edx -; AVX2-NEXT: subl %ecx, %edx -; AVX2-NEXT: cmovbl %eax, %edx -; AVX2-NEXT: vmovd %xmm2, %ecx -; AVX2-NEXT: vmovd %xmm0, %esi -; AVX2-NEXT: subl %ecx, %esi -; AVX2-NEXT: cmovbl %eax, %esi -; AVX2-NEXT: vmovd %esi, %xmm5 -; AVX2-NEXT: vpinsrd $1, %edx, %xmm5, %xmm5 -; AVX2-NEXT: vpextrd $2, %xmm2, %ecx -; AVX2-NEXT: vpextrd $2, %xmm0, %edx -; AVX2-NEXT: subl %ecx, %edx -; AVX2-NEXT: cmovbl %eax, %edx -; AVX2-NEXT: vpinsrd $2, %edx, %xmm5, %xmm5 -; AVX2-NEXT: vpextrd $3, %xmm2, %ecx -; AVX2-NEXT: vpextrd $3, %xmm0, %edx -; AVX2-NEXT: subl %ecx, %edx -; AVX2-NEXT: cmovbl %eax, %edx -; AVX2-NEXT: vpinsrd $3, %edx, %xmm5, %xmm0 -; AVX2-NEXT: vinserti128 $1, %xmm4, %ymm0, %ymm0 -; AVX2-NEXT: vextracti128 $1, %ymm3, %xmm2 -; AVX2-NEXT: vpextrd $1, %xmm2, %ecx -; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm4 -; AVX2-NEXT: vpextrd $1, %xmm4, %edx -; AVX2-NEXT: subl %ecx, %edx -; AVX2-NEXT: cmovbl %eax, %edx -; AVX2-NEXT: vmovd %xmm2, %ecx -; AVX2-NEXT: vmovd %xmm4, %esi -; AVX2-NEXT: subl %ecx, %esi -; AVX2-NEXT: cmovbl %eax, %esi -; AVX2-NEXT: vmovd %esi, %xmm5 -; AVX2-NEXT: vpinsrd $1, %edx, %xmm5, %xmm5 -; AVX2-NEXT: vpextrd $2, %xmm2, %ecx -; AVX2-NEXT: vpextrd $2, %xmm4, %edx -; AVX2-NEXT: subl %ecx, %edx -; AVX2-NEXT: cmovbl %eax, %edx -; AVX2-NEXT: vpinsrd $2, %edx, %xmm5, %xmm5 -; AVX2-NEXT: vpextrd $3, %xmm2, %ecx -; AVX2-NEXT: vpextrd $3, %xmm4, %edx -; AVX2-NEXT: subl %ecx, %edx -; AVX2-NEXT: cmovbl %eax, %edx -; AVX2-NEXT: vpinsrd $3, %edx, %xmm5, %xmm2 -; AVX2-NEXT: vpextrd $1, %xmm3, %ecx -; AVX2-NEXT: vpextrd $1, %xmm1, %edx -; AVX2-NEXT: subl %ecx, %edx -; AVX2-NEXT: cmovbl %eax, %edx -; AVX2-NEXT: vmovd %xmm3, %ecx -; AVX2-NEXT: vmovd %xmm1, %esi -; AVX2-NEXT: subl %ecx, %esi -; AVX2-NEXT: cmovbl %eax, %esi -; AVX2-NEXT: vmovd %esi, %xmm4 -; AVX2-NEXT: vpinsrd $1, %edx, %xmm4, %xmm4 -; AVX2-NEXT: vpextrd $2, %xmm3, %ecx -; AVX2-NEXT: vpextrd $2, %xmm1, %edx -; AVX2-NEXT: subl %ecx, %edx -; AVX2-NEXT: cmovbl %eax, %edx -; AVX2-NEXT: vpinsrd $2, %edx, %xmm4, %xmm4 -; AVX2-NEXT: vpextrd $3, %xmm3, %ecx -; AVX2-NEXT: vpextrd $3, %xmm1, %edx -; AVX2-NEXT: subl %ecx, %edx -; AVX2-NEXT: cmovbl %eax, %edx -; AVX2-NEXT: vpinsrd $3, %edx, %xmm4, %xmm1 -; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1 +; AVX2-NEXT: vpmaxud %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpsubd %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpmaxud %ymm3, %ymm1, %ymm1 +; AVX2-NEXT: vpsubd %ymm3, %ymm1, %ymm1 ; AVX2-NEXT: retq ; ; AVX512-LABEL: v16i32: ; AVX512: # %bb.0: -; AVX512-NEXT: vextracti32x4 $3, %zmm1, %xmm2 -; AVX512-NEXT: vpextrd $1, %xmm2, %ecx -; AVX512-NEXT: vextracti32x4 $3, %zmm0, %xmm3 -; AVX512-NEXT: vpextrd $1, %xmm3, %edx -; AVX512-NEXT: xorl %eax, %eax -; AVX512-NEXT: subl %ecx, %edx -; AVX512-NEXT: cmovbl %eax, %edx -; AVX512-NEXT: vmovd %xmm2, %ecx -; AVX512-NEXT: vmovd %xmm3, %esi -; AVX512-NEXT: subl %ecx, %esi -; AVX512-NEXT: cmovbl %eax, %esi -; AVX512-NEXT: vmovd %esi, %xmm4 -; AVX512-NEXT: vpinsrd $1, %edx, %xmm4, %xmm4 -; AVX512-NEXT: vpextrd $2, %xmm2, %ecx -; AVX512-NEXT: vpextrd $2, %xmm3, %edx -; AVX512-NEXT: subl %ecx, %edx -; AVX512-NEXT: cmovbl %eax, %edx -; AVX512-NEXT: vpinsrd $2, %edx, %xmm4, %xmm4 -; AVX512-NEXT: vpextrd $3, %xmm2, %ecx -; AVX512-NEXT: vpextrd $3, %xmm3, %edx -; AVX512-NEXT: subl %ecx, %edx -; AVX512-NEXT: cmovbl %eax, %edx -; AVX512-NEXT: vpinsrd $3, %edx, %xmm4, %xmm2 -; AVX512-NEXT: vextracti32x4 $2, %zmm1, %xmm3 -; AVX512-NEXT: vpextrd $1, %xmm3, %ecx -; AVX512-NEXT: vextracti32x4 $2, %zmm0, %xmm4 -; AVX512-NEXT: vpextrd $1, %xmm4, %edx -; AVX512-NEXT: subl %ecx, %edx -; AVX512-NEXT: cmovbl %eax, %edx -; AVX512-NEXT: vmovd %xmm3, %ecx -; AVX512-NEXT: vmovd %xmm4, %esi -; AVX512-NEXT: subl %ecx, %esi -; AVX512-NEXT: cmovbl %eax, %esi -; AVX512-NEXT: vmovd %esi, %xmm5 -; AVX512-NEXT: vpinsrd $1, %edx, %xmm5, %xmm5 -; AVX512-NEXT: vpextrd $2, %xmm3, %ecx -; AVX512-NEXT: vpextrd $2, %xmm4, %edx -; AVX512-NEXT: subl %ecx, %edx -; AVX512-NEXT: cmovbl %eax, %edx -; AVX512-NEXT: vpinsrd $2, %edx, %xmm5, %xmm5 -; AVX512-NEXT: vpextrd $3, %xmm3, %ecx -; AVX512-NEXT: vpextrd $3, %xmm4, %edx -; AVX512-NEXT: subl %ecx, %edx -; AVX512-NEXT: cmovbl %eax, %edx -; AVX512-NEXT: vpinsrd $3, %edx, %xmm5, %xmm3 -; AVX512-NEXT: vinserti128 $1, %xmm2, %ymm3, %ymm2 -; AVX512-NEXT: vextracti128 $1, %ymm1, %xmm3 -; AVX512-NEXT: vpextrd $1, %xmm3, %ecx -; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm4 -; AVX512-NEXT: vpextrd $1, %xmm4, %edx -; AVX512-NEXT: subl %ecx, %edx -; AVX512-NEXT: cmovbl %eax, %edx -; AVX512-NEXT: vmovd %xmm3, %ecx -; AVX512-NEXT: vmovd %xmm4, %esi -; AVX512-NEXT: subl %ecx, %esi -; AVX512-NEXT: cmovbl %eax, %esi -; AVX512-NEXT: vmovd %esi, %xmm5 -; AVX512-NEXT: vpinsrd $1, %edx, %xmm5, %xmm5 -; AVX512-NEXT: vpextrd $2, %xmm3, %ecx -; AVX512-NEXT: vpextrd $2, %xmm4, %edx -; AVX512-NEXT: subl %ecx, %edx -; AVX512-NEXT: cmovbl %eax, %edx -; AVX512-NEXT: vpinsrd $2, %edx, %xmm5, %xmm5 -; AVX512-NEXT: vpextrd $3, %xmm3, %ecx -; AVX512-NEXT: vpextrd $3, %xmm4, %edx -; AVX512-NEXT: subl %ecx, %edx -; AVX512-NEXT: cmovbl %eax, %edx -; AVX512-NEXT: vpinsrd $3, %edx, %xmm5, %xmm3 -; AVX512-NEXT: vpextrd $1, %xmm1, %ecx -; AVX512-NEXT: vpextrd $1, %xmm0, %edx -; AVX512-NEXT: subl %ecx, %edx -; AVX512-NEXT: cmovbl %eax, %edx -; AVX512-NEXT: vmovd %xmm1, %ecx -; AVX512-NEXT: vmovd %xmm0, %esi -; AVX512-NEXT: subl %ecx, %esi -; AVX512-NEXT: cmovbl %eax, %esi -; AVX512-NEXT: vmovd %esi, %xmm4 -; AVX512-NEXT: vpinsrd $1, %edx, %xmm4, %xmm4 -; AVX512-NEXT: vpextrd $2, %xmm1, %ecx -; AVX512-NEXT: vpextrd $2, %xmm0, %edx -; AVX512-NEXT: subl %ecx, %edx -; AVX512-NEXT: cmovbl %eax, %edx -; AVX512-NEXT: vpinsrd $2, %edx, %xmm4, %xmm4 -; AVX512-NEXT: vpextrd $3, %xmm1, %ecx -; AVX512-NEXT: vpextrd $3, %xmm0, %edx -; AVX512-NEXT: subl %ecx, %edx -; AVX512-NEXT: cmovbl %eax, %edx -; AVX512-NEXT: vpinsrd $3, %edx, %xmm4, %xmm0 -; AVX512-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm0 -; AVX512-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0 +; AVX512-NEXT: vpmaxud %zmm1, %zmm0, %zmm0 +; AVX512-NEXT: vpsubd %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: retq %z = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %x, <16 x i32> %y) ret <16 x i32> %z @@ -1840,21 +1348,43 @@ ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSE41-NEXT: retq ; -; AVX-LABEL: v2i64: -; AVX: # %bb.0: -; AVX-NEXT: vpextrq $1, %xmm1, %rax -; AVX-NEXT: vpextrq $1, %xmm0, %rcx -; AVX-NEXT: xorl %edx, %edx -; AVX-NEXT: subq %rax, %rcx -; AVX-NEXT: cmovbq %rdx, %rcx -; AVX-NEXT: vmovq %rcx, %xmm2 -; AVX-NEXT: vmovq %xmm1, %rax -; AVX-NEXT: vmovq %xmm0, %rcx -; AVX-NEXT: subq %rax, %rcx -; AVX-NEXT: cmovbq %rdx, %rcx -; AVX-NEXT: vmovq %rcx, %xmm0 -; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] -; AVX-NEXT: retq +; AVX1-LABEL: v2i64: +; AVX1: # %bb.0: +; AVX1-NEXT: vpextrq $1, %xmm1, %rax +; AVX1-NEXT: vpextrq $1, %xmm0, %rcx +; AVX1-NEXT: xorl %edx, %edx +; AVX1-NEXT: subq %rax, %rcx +; AVX1-NEXT: cmovbq %rdx, %rcx +; AVX1-NEXT: vmovq %rcx, %xmm2 +; AVX1-NEXT: vmovq %xmm1, %rax +; AVX1-NEXT: vmovq %xmm0, %rcx +; AVX1-NEXT: subq %rax, %rcx +; AVX1-NEXT: cmovbq %rdx, %rcx +; AVX1-NEXT: vmovq %rcx, %xmm0 +; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] +; AVX1-NEXT: retq +; +; AVX2-LABEL: v2i64: +; AVX2: # %bb.0: +; AVX2-NEXT: vpextrq $1, %xmm1, %rax +; AVX2-NEXT: vpextrq $1, %xmm0, %rcx +; AVX2-NEXT: xorl %edx, %edx +; AVX2-NEXT: subq %rax, %rcx +; AVX2-NEXT: cmovbq %rdx, %rcx +; AVX2-NEXT: vmovq %rcx, %xmm2 +; AVX2-NEXT: vmovq %xmm1, %rax +; AVX2-NEXT: vmovq %xmm0, %rcx +; AVX2-NEXT: subq %rax, %rcx +; AVX2-NEXT: cmovbq %rdx, %rcx +; AVX2-NEXT: vmovq %rcx, %xmm0 +; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] +; AVX2-NEXT: retq +; +; AVX512-LABEL: v2i64: +; AVX512: # %bb.0: +; AVX512-NEXT: vpmaxuq %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: vpsubq %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: retq %z = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %x, <2 x i64> %y) ret <2 x i64> %z } @@ -2015,32 +1545,8 @@ ; ; AVX512-LABEL: v4i64: ; AVX512: # %bb.0: -; AVX512-NEXT: vextracti128 $1, %ymm1, %xmm2 -; AVX512-NEXT: vpextrq $1, %xmm2, %rax -; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm3 -; AVX512-NEXT: vpextrq $1, %xmm3, %rcx -; AVX512-NEXT: xorl %edx, %edx -; AVX512-NEXT: subq %rax, %rcx -; AVX512-NEXT: cmovbq %rdx, %rcx -; AVX512-NEXT: vmovq %rcx, %xmm4 -; AVX512-NEXT: vmovq %xmm2, %rax -; AVX512-NEXT: vmovq %xmm3, %rcx -; AVX512-NEXT: subq %rax, %rcx -; AVX512-NEXT: cmovbq %rdx, %rcx -; AVX512-NEXT: vmovq %rcx, %xmm2 -; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0] -; AVX512-NEXT: vpextrq $1, %xmm1, %rax -; AVX512-NEXT: vpextrq $1, %xmm0, %rcx -; AVX512-NEXT: subq %rax, %rcx -; AVX512-NEXT: cmovbq %rdx, %rcx -; AVX512-NEXT: vmovq %rcx, %xmm3 -; AVX512-NEXT: vmovq %xmm1, %rax -; AVX512-NEXT: vmovq %xmm0, %rcx -; AVX512-NEXT: subq %rax, %rcx -; AVX512-NEXT: cmovbq %rdx, %rcx -; AVX512-NEXT: vmovq %rcx, %xmm0 -; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0] -; AVX512-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0 +; AVX512-NEXT: vpmaxuq %ymm1, %ymm0, %ymm0 +; AVX512-NEXT: vpsubq %ymm1, %ymm0, %ymm0 ; AVX512-NEXT: retq %z = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> %x, <4 x i64> %y) ret <4 x i64> %z @@ -2330,60 +1836,8 @@ ; ; AVX512-LABEL: v8i64: ; AVX512: # %bb.0: -; AVX512-NEXT: vextracti32x4 $3, %zmm1, %xmm2 -; AVX512-NEXT: vpextrq $1, %xmm2, %rcx -; AVX512-NEXT: vextracti32x4 $3, %zmm0, %xmm3 -; AVX512-NEXT: vpextrq $1, %xmm3, %rdx -; AVX512-NEXT: xorl %eax, %eax -; AVX512-NEXT: subq %rcx, %rdx -; AVX512-NEXT: cmovbq %rax, %rdx -; AVX512-NEXT: vmovq %rdx, %xmm4 -; AVX512-NEXT: vmovq %xmm2, %rcx -; AVX512-NEXT: vmovq %xmm3, %rdx -; AVX512-NEXT: subq %rcx, %rdx -; AVX512-NEXT: cmovbq %rax, %rdx -; AVX512-NEXT: vmovq %rdx, %xmm2 -; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm4[0] -; AVX512-NEXT: vextracti32x4 $2, %zmm1, %xmm3 -; AVX512-NEXT: vpextrq $1, %xmm3, %rcx -; AVX512-NEXT: vextracti32x4 $2, %zmm0, %xmm4 -; AVX512-NEXT: vpextrq $1, %xmm4, %rdx -; AVX512-NEXT: subq %rcx, %rdx -; AVX512-NEXT: cmovbq %rax, %rdx -; AVX512-NEXT: vmovq %rdx, %xmm5 -; AVX512-NEXT: vmovq %xmm3, %rcx -; AVX512-NEXT: vmovq %xmm4, %rdx -; AVX512-NEXT: subq %rcx, %rdx -; AVX512-NEXT: cmovbq %rax, %rdx -; AVX512-NEXT: vmovq %rdx, %xmm3 -; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm5[0] -; AVX512-NEXT: vinserti128 $1, %xmm2, %ymm3, %ymm2 -; AVX512-NEXT: vextracti128 $1, %ymm1, %xmm3 -; AVX512-NEXT: vpextrq $1, %xmm3, %rcx -; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm4 -; AVX512-NEXT: vpextrq $1, %xmm4, %rdx -; AVX512-NEXT: subq %rcx, %rdx -; AVX512-NEXT: cmovbq %rax, %rdx -; AVX512-NEXT: vmovq %rdx, %xmm5 -; AVX512-NEXT: vmovq %xmm3, %rcx -; AVX512-NEXT: vmovq %xmm4, %rdx -; AVX512-NEXT: subq %rcx, %rdx -; AVX512-NEXT: cmovbq %rax, %rdx -; AVX512-NEXT: vmovq %rdx, %xmm3 -; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm5[0] -; AVX512-NEXT: vpextrq $1, %xmm1, %rcx -; AVX512-NEXT: vpextrq $1, %xmm0, %rdx -; AVX512-NEXT: subq %rcx, %rdx -; AVX512-NEXT: cmovbq %rax, %rdx -; AVX512-NEXT: vmovq %rdx, %xmm4 -; AVX512-NEXT: vmovq %xmm1, %rcx -; AVX512-NEXT: vmovq %xmm0, %rdx -; AVX512-NEXT: subq %rcx, %rdx -; AVX512-NEXT: cmovbq %rax, %rdx -; AVX512-NEXT: vmovq %rdx, %xmm0 -; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm4[0] -; AVX512-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm0 -; AVX512-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0 +; AVX512-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0 +; AVX512-NEXT: vpsubq %zmm1, %zmm0, %zmm0 ; AVX512-NEXT: retq %z = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> %x, <8 x i64> %y) ret <8 x i64> %z