Enable fma formation for fp16 on x86 and aarch64

[scanon]

Summary

The value of isFMAFasterThanFMulAndFAdd for fp16 should match fp32 on these targets when we legalize by extending to fp32 operations, and (on aarch64) when fp16 arithmetic is supported directly the value should just be true.

[fhahn]

The AArch64 side LGTM. Also adding Oliver and Sjoerd as they worked on FP16 side as well, in case they have any thoughts.

The only public documentation for Arm v8.2+ CPUs I could find indicates FADD,FMUL and FMADD have the same latencies and throughputs on Cortex-A75: https://static.docs.arm.com/101398/0200/arm_cortex_a75_software_optimization_guide_v2.pdf

For the X86, I think a test would be great.

[SjoerdMeijer]

The AArch64 side LGTM. Also adding Oliver and Sjoerd as they worked on FP16 side as well, in case they have any thoughts.

I did a same/similar exercise not so long ago for AArch32, M-cores (see https://reviews.llvm.org/D53314). I haven't looked into this for AArch64, but anyway, what I wanted to say is that checking the software optimisation guides is the thing to do: the A55 is also a v8.2 core with FP16. It has a public guide here: http://infocenter.arm.com/help/topic/com.arm.doc.epm128372/arm_cortex_a55_software_optimization_guide_v2.pdf

lib/Target/AArch64/AArch64ISelLowering.cpp

 
 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
   VT = VT.getScalarType();
 
   if (!VT.isSimple())
     return false;
 
   switch (VT.getSimpleVT().SimpleTy) {
+  case MVT::f16:
   case MVT::f32:
   case MVT::f64:
     return true;
   default:
     break;
   }
 
   return false;

lib/Target/X86/X86ISelLowering.cpp

if (!Subtarget.hasAnyFMA())
     return false;
 
   VT = VT.getScalarType();
 
   if (!VT.isSimple())
     return false;
 
   switch (VT.getSimpleVT().SimpleTy) {
+  case MVT::f16:
   case MVT::f32:
   case MVT::f64:
     return true;
   default:
     break;
   }
 
   return false;

test/CodeGen/AArch64/f16-instructions.ll

 ; CHECK-FP16-NEXT: ret
 
 define half @test_round(half %a) #0 {
   %r = call half @llvm.round.f16(half %a)
   ret half %r
 }
 
 ; CHECK-CVT-LABEL: test_fmuladd:
+; CHECK-CVT-NEXT: fcvt s2, h2
 ; CHECK-CVT-NEXT: fcvt s1, h1
 ; CHECK-CVT-NEXT: fcvt s0, h0
-; CHECK-CVT-NEXT: fmul s0, s0, s1
-; CHECK-CVT-NEXT: fcvt h0, s0
-; CHECK-CVT-NEXT: fcvt s0, h0
-; CHECK-CVT-NEXT: fcvt s1, h2
-; CHECK-CVT-NEXT: fadd s0, s0, s1
+; CHECK-CVT-NEXT: fmadd s0, s0, s1, s2
 ; CHECK-CVT-NEXT: fcvt h0, s0
 ; CHECK-CVT-NEXT: ret
 
 ; CHECK-FP16-LABEL: test_fmuladd:
-; CHECK-FP16-NEXT: fmul h0, h0, h1
-; CHECK-FP16-NEXT: fadd h0, h0, h2
+; CHECK-FP16-NEXT: fmadd h0, h0, h1, h2
 ; CHECK-FP16-NEXT: ret
 
 define half @test_fmuladd(half %a, half %b, half %c) #0 {
   %r = call half @llvm.fmuladd.f16(half %a, half %b, half %c)
   ret half %r
 }
 
 ; CHECK-FP16-LABEL: test_vrecpeh_f16: