Index: lib/Target/RISCV/RISCVInstrInfo.h
===================================================================
--- lib/Target/RISCV/RISCVInstrInfo.h
+++ lib/Target/RISCV/RISCVInstrInfo.h
@@ -79,6 +79,11 @@
 
   bool isBranchOffsetInRange(unsigned BranchOpc,
                              int64_t BrOffset) const override;
+
+  bool isAsCheapAsAMove(const MachineInstr &MI) const override;
+
+  bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
+                                         AliasAnalysis *AA) const override;
 };
 }
 #endif
Index: lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- lib/Target/RISCV/RISCVInstrInfo.cpp
+++ lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -448,3 +448,35 @@
   }
   }
 }
+
+bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
+  const unsigned Opcode = MI.getOpcode();
+  switch(Opcode) {
+    default:
+      break;
+    case RISCV::ADDI:
+      //  Catching LI reg, %lo(sym) or LI reg, %pcrel_lo(sym) or something similar.
+      if ((MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0))
+        return true;
+      return false;
+  }
+  return MI.isAsCheapAsAMove();
+}
+
+bool
+RISCVInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
+                                                  AliasAnalysis *AA) const {
+  switch (MI.getOpcode()) {
+  default:
+    // This function should only be called for opcodes with the ReMaterializable
+    // flag set.
+    llvm_unreachable("Unknown rematerializable operation!");
+    break;
+  case RISCV::ADDI:
+    return false;
+  case RISCV::AUIPC:
+  case RISCV::LUI:
+    return true;
+  }
+  return false;
+}