Index: llvm/trunk/lib/Target/AArch64/AArch64.td
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64.td
+++ llvm/trunk/lib/Target/AArch64/AArch64.td
@@ -312,8 +312,8 @@
 def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS",
   "true", "Enable Speculative Store Bypass Safe bit" >;
 
-def FeaturePredCtrl : SubtargetFeature<"predctrl", "HasPredCtrl", "true",
-  "Enable execution and data prediction invalidation instructions" >;
+def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true",
+  "Enable v8.5a execution and data prediction invalidation instructions" >;
 
 def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
     "true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >;
@@ -352,7 +352,7 @@
 def HasV8_5aOps : SubtargetFeature<
   "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
   [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
-   FeatureSSBS, FeatureSB, FeaturePredCtrl, FeatureCacheDeepPersist,
+   FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
    FeatureBranchTargetId]
 >;
 
Index: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
@@ -116,8 +116,8 @@
                        AssemblerPredicate<"FeatureFRInt3264", "frint3264">;
 def HasSB            : Predicate<"Subtarget->hasSB()">,
                        AssemblerPredicate<"FeatureSB", "sb">;
-def HasPredCtrl      : Predicate<"Subtarget->hasPredCtrl()">,
-                       AssemblerPredicate<"FeaturePredCtrl", "predctrl">;
+def HasPredRes      : Predicate<"Subtarget->hasPredRes()">,
+                       AssemblerPredicate<"FeaturePredRes", "predres">;
 def HasCCDP          : Predicate<"Subtarget->hasCCDP()">,
                        AssemblerPredicate<"FeatureCacheDeepPersist", "ccdp">;
 def HasBTI           : Predicate<"Subtarget->hasBTI()">,
Index: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
@@ -128,7 +128,7 @@
   bool HasSpecRestrict = false;
   bool HasSSBS = false;
   bool HasSB = false;
-  bool HasPredCtrl = false;
+  bool HasPredRes = false;
   bool HasCCDP = false;
   bool HasBTI = false;
   bool HasRandGen = false;
@@ -357,7 +357,7 @@
   bool hasSpecRestrict() const { return HasSpecRestrict; }
   bool hasSSBS() const { return HasSSBS; }
   bool hasSB() const { return HasSB; }
-  bool hasPredCtrl() const { return HasPredCtrl; }
+  bool hasPredRes() const { return HasPredRes; }
   bool hasCCDP() const { return HasCCDP; }
   bool hasBTI() const { return HasBTI; }
   bool hasRandGen() const { return HasRandGen; }
Index: llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td
+++ llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td
@@ -501,7 +501,7 @@
   code Requires = [{ {} }];
 }
 
-let Requires = [{ {AArch64::FeaturePredCtrl} }] in {
+let Requires = [{ {AArch64::FeaturePredRes} }] in {
 def : PRCTX<"RCTX", 0b0011>;
 }
 
Index: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -2826,7 +2826,7 @@
     {"simd", {AArch64::FeatureNEON}},
     {"ras", {AArch64::FeatureRAS}},
     {"lse", {AArch64::FeatureLSE}},
-    {"predctrl", {AArch64::FeaturePredCtrl}},
+    {"predres", {AArch64::FeaturePredRes}},
     {"ccdp", {AArch64::FeatureCacheDeepPersist}},
     {"mte", {AArch64::FeatureMTE}},
     {"tlb-rmi", {AArch64::FeatureTLB_RMI}},
Index: llvm/trunk/test/MC/AArch64/armv8.5a-predctrl-error.s
===================================================================
--- llvm/trunk/test/MC/AArch64/armv8.5a-predctrl-error.s
+++ llvm/trunk/test/MC/AArch64/armv8.5a-predctrl-error.s
@@ -1,20 +0,0 @@
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+predctrl < %s 2>&1| FileCheck %s
-
-cfp rctx
-dvp rctx
-cpp rctx
-
-// CHECK: specified cfp op requires a register
-// CHECK: specified dvp op requires a register
-// CHECK: specified cpp op requires a register
-
-cfp x0, x1
-dvp x1, x2
-cpp x2, x3
-
-// CHECK:      invalid operand for prediction restriction instruction
-// CHECK-NEXT: cfp
-// CHECK:      invalid operand for prediction restriction instruction
-// CHECK-NEXT: dvp
-// CHECK:      invalid operand for prediction restriction instruction
-// CHECK-NEXT: cpp
Index: llvm/trunk/test/MC/AArch64/armv8.5a-predctrl.s
===================================================================
--- llvm/trunk/test/MC/AArch64/armv8.5a-predctrl.s
+++ llvm/trunk/test/MC/AArch64/armv8.5a-predctrl.s
@@ -1,18 +0,0 @@
-// RUN:     llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+predctrl < %s      | FileCheck %s
-// RUN:     llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.5a    < %s      | FileCheck %s
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-predctrl < %s 2>&1 | FileCheck %s --check-prefix=NOPREDCTRL
-
-cfp rctx, x0
-dvp rctx, x1
-cpp rctx, x2
-
-// CHECK: cfp rctx, x0      // encoding: [0x80,0x73,0x0b,0xd5]
-// CHECK: dvp rctx, x1      // encoding: [0xa1,0x73,0x0b,0xd5]
-// CHECK: cpp rctx, x2      // encoding: [0xe2,0x73,0x0b,0xd5]
-
-// NOPREDCTRL: CFPRCTX requires predctrl
-// NOPREDCTRL-NEXT: cfp
-// NOPREDCTRL: DVPRCTX requires predctrl
-// NOPREDCTRL-NEXT: dvp
-// NOPREDCTRL: CPPRCTX requires predctrl
-// NOPREDCTRL-NEXT: cpp
Index: llvm/trunk/test/MC/AArch64/armv8.5a-predres-error.s
===================================================================
--- llvm/trunk/test/MC/AArch64/armv8.5a-predres-error.s
+++ llvm/trunk/test/MC/AArch64/armv8.5a-predres-error.s
@@ -0,0 +1,20 @@
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+predres < %s 2>&1| FileCheck %s
+
+cfp rctx
+dvp rctx
+cpp rctx
+
+// CHECK: specified cfp op requires a register
+// CHECK: specified dvp op requires a register
+// CHECK: specified cpp op requires a register
+
+cfp x0, x1
+dvp x1, x2
+cpp x2, x3
+
+// CHECK:      invalid operand for prediction restriction instruction
+// CHECK-NEXT: cfp
+// CHECK:      invalid operand for prediction restriction instruction
+// CHECK-NEXT: dvp
+// CHECK:      invalid operand for prediction restriction instruction
+// CHECK-NEXT: cpp
Index: llvm/trunk/test/MC/AArch64/armv8.5a-predres.s
===================================================================
--- llvm/trunk/test/MC/AArch64/armv8.5a-predres.s
+++ llvm/trunk/test/MC/AArch64/armv8.5a-predres.s
@@ -0,0 +1,18 @@
+// RUN:     llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+predres < %s      | FileCheck %s
+// RUN:     llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.5a    < %s      | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-predres < %s 2>&1 | FileCheck %s --check-prefix=NOPREDCTRL
+
+cfp rctx, x0
+dvp rctx, x1
+cpp rctx, x2
+
+// CHECK: cfp rctx, x0      // encoding: [0x80,0x73,0x0b,0xd5]
+// CHECK: dvp rctx, x1      // encoding: [0xa1,0x73,0x0b,0xd5]
+// CHECK: cpp rctx, x2      // encoding: [0xe2,0x73,0x0b,0xd5]
+
+// NOPREDCTRL: CFPRCTX requires predres
+// NOPREDCTRL-NEXT: cfp
+// NOPREDCTRL: DVPRCTX requires predres
+// NOPREDCTRL-NEXT: dvp
+// NOPREDCTRL: CPPRCTX requires predres
+// NOPREDCTRL-NEXT: cpp
Index: llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-predctrl.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-predctrl.txt
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-predctrl.txt
@@ -1,15 +0,0 @@
-# RUN: llvm-mc -triple=aarch64 -mattr=+predctrl -disassemble < %s      | FileCheck %s
-# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a    -disassemble < %s      | FileCheck %s
-# RUN: llvm-mc -triple=aarch64 -mattr=-predctrl -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
-
-[0x80 0x73 0x0b 0xd5]
-[0xa1 0x73 0x0b 0xd5]
-[0xe2 0x73 0x0b 0xd5]
-
-# CHECK: cfp rctx, x0
-# CHECK: dvp rctx, x1
-# CHECK: cpp rctx, x2
-
-# NOSB: sys #3, c7, c3, #4, x0
-# NOSB: sys #3, c7, c3, #5, x1
-# NOSB: sys #3, c7, c3, #7, x2
Index: llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-predres.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-predres.txt
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-predres.txt
@@ -0,0 +1,15 @@
+# RUN: llvm-mc -triple=aarch64 -mattr=+predres -disassemble < %s      | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a    -disassemble < %s      | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=-predres -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
+
+[0x80 0x73 0x0b 0xd5]
+[0xa1 0x73 0x0b 0xd5]
+[0xe2 0x73 0x0b 0xd5]
+
+# CHECK: cfp rctx, x0
+# CHECK: dvp rctx, x1
+# CHECK: cpp rctx, x2
+
+# NOSB: sys #3, c7, c3, #4, x0
+# NOSB: sys #3, c7, c3, #5, x1
+# NOSB: sys #3, c7, c3, #7, x2