Index: lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -164,7 +164,8 @@
   setAction({G_FCMP, 1, S64}, Legal);
 
   getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
-    .legalFor({{S64, S32}, {S32, S16}, {S64, S16}})
+    .legalFor({{S64, S32}, {S32, S16}, {S64, S16},
+               {S32, S1}, {S64, S1}, {S16, S1}})
     .fewerElementsIf(
       [](const LegalityQuery &Query) {
         return Query.Types[0].isVector();
Index: test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
===================================================================
--- test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
+++ test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
@@ -52,16 +52,28 @@
 name: test_anyext_i1_to_i32
 body: |
   bb.0.entry:
-    liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_anyext_i1_to_i32
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
-    ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
-    %0:_(s32) = COPY $vgpr0
-    %1:_(s1) = G_TRUNC %0
-    %2:_(s32) = G_ANYEXT %1
-    $vgpr0 = COPY %2
+    ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s1)
+    ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
+    %0:_(s1) = G_CONSTANT i1 0
+    %1:_(s32) = G_ANYEXT %0
+    $vgpr0 = COPY %1
+...
+
+---
+name: test_anyext_i1_to_i64
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: name: test_anyext_i1_to_i64
+    ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s1)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[ANYEXT]](s64)
+    %0:_(s1) = G_CONSTANT i1 0
+    %1:_(s64) = G_ANYEXT %0
+    $vgpr0_vgpr1 = COPY %1
 ...
 
 ---
Index: test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
===================================================================
--- test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
+++ test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
@@ -63,16 +63,12 @@
     liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_sext_i1_to_i32
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
-    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
-    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
-    ; CHECK: $vgpr0 = COPY [[ASHR]](s32)
-    %0:_(s32) = COPY $vgpr0
-    %1:_(s1) = G_TRUNC %0
-    %2:_(s32) = G_SEXT %1
-    $vgpr0 = COPY %2
+    ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
+    ; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s1)
+    ; CHECK: $vgpr0 = COPY [[SEXT]](s32)
+    %0:_(s1) = G_CONSTANT i1 0
+    %1:_(s32) = G_SEXT %0
+    $vgpr0 = COPY %1
 ...
 
 ---
Index: test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
===================================================================
--- test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
+++ test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
@@ -56,18 +56,28 @@
 name: test_zext_i1_to_i32
 body: |
   bb.0.entry:
-    liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_zext_i1_to_i32
-    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
-    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
-    ; CHECK: $vgpr0 = COPY [[AND]](s32)
-    %0:_(s32) = COPY $vgpr0
-    %1:_(s1) = G_TRUNC %0
-    %2:_(s32) = G_ZEXT %1
-    $vgpr0 = COPY %2
+    ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
+    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[C]](s1)
+    ; CHECK: $vgpr0 = COPY [[ZEXT]](s32)
+    %0:_(s1) = G_CONSTANT i1 0
+    %1:_(s32) = G_ZEXT %0
+    $vgpr0 = COPY %1
+...
+
+---
+name: test_zext_i1_to_i64
+body: |
+  bb.0.entry:
+
+    ; CHECK-LABEL: name: test_zext_i1_to_i64
+    ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
+    ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s1)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
+    %0:_(s1) = G_CONSTANT i1 0
+    %1:_(s64) = G_ZEXT %0
+    $vgpr0_vgpr1 = COPY %1
 ...
 
 ---