Index: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp =================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2827,7 +2827,15 @@ Known.Zero.setBitsFrom(InVT.getScalarSizeInBits()); break; } - // TODO ISD::SIGN_EXTEND_VECTOR_INREG + case ISD::SIGN_EXTEND_VECTOR_INREG: { + EVT InVT = Op.getOperand(0).getValueType(); + APInt InDemandedElts = DemandedElts.zextOrSelf(InVT.getVectorNumElements()); + Known = computeKnownBits(Op.getOperand(0), InDemandedElts, Depth + 1); + // If the sign bit is known to be zero or one, then sext will extend + // it to the top bits, else it will just zext. + Known = Known.sext(BitWidth); + break; + } case ISD::SIGN_EXTEND: { Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1); // If the sign bit is known to be zero or one, then sext will extend Index: llvm/trunk/test/CodeGen/X86/combine-shl.ll =================================================================== --- llvm/trunk/test/CodeGen/X86/combine-shl.ll +++ llvm/trunk/test/CodeGen/X86/combine-shl.ll @@ -283,17 +283,11 @@ ; SSE41-LABEL: combine_vec_shl_ext_shl1: ; SSE41: # %bb.0: ; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm0 -; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; SSE41-NEXT: pmovsxwd %xmm1, %xmm1 ; SSE41-NEXT: pmovsxwd %xmm0, %xmm0 -; SSE41-NEXT: movdqa %xmm0, %xmm2 -; SSE41-NEXT: pslld $30, %xmm2 -; SSE41-NEXT: pslld $31, %xmm0 -; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7] -; SSE41-NEXT: movdqa %xmm1, %xmm2 -; SSE41-NEXT: pslld $28, %xmm2 -; SSE41-NEXT: pslld $29, %xmm1 -; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7] +; SSE41-NEXT: pslld $30, %xmm0 +; SSE41-NEXT: pxor %xmm1, %xmm1 +; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7] +; SSE41-NEXT: pxor %xmm1, %xmm1 ; SSE41-NEXT: retq ; ; AVX-LABEL: combine_vec_shl_ext_shl1: