Index: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp =================================================================== --- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -777,15 +777,18 @@ return Legalized; case TargetOpcode::G_SELECT: - if (TypeIdx != 0) - return UnableToLegalize; - // Perform operation at larger width (any extension is fine here, high bits - // don't affect the result) and then truncate the result back to the - // original type. Observer.changingInstr(MI); - widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); - widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT); - widenScalarDst(MI, WideTy); + if (TypeIdx == 0) { + // Perform operation at larger width (any extension is fine here, high + // bits don't affect the result) and then truncate the result back to the + // original type. + widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); + widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT); + widenScalarDst(MI, WideTy); + } else { + // Explicit extension is required here since high bits affect the result. + widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); + } Observer.changedInstr(MI); return Legalized; Index: llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp +++ llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp @@ -172,6 +172,15 @@ I.eraseFromParent(); return true; } + case G_SELECT: { + // Handle operands with pointer type. + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I)) + .add(I.getOperand(0)) + .add(I.getOperand(2)) + .add(I.getOperand(1)) + .add(I.getOperand(3)); + break; + } case G_CONSTANT: { int Imm = I.getOperand(1).getCImm()->getValue().getLimitedValue(); unsigned LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass); Index: llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp +++ llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp @@ -35,6 +35,11 @@ getActionDefinitionsBuilder({G_LOAD, G_STORE}) .legalForCartesianProduct({p0, s32}, {p0}); + getActionDefinitionsBuilder(G_SELECT) + .legalForCartesianProduct({p0, s32}, {s32}) + .minScalar(0, s32) + .minScalar(1, s32); + getActionDefinitionsBuilder({G_AND, G_OR, G_XOR}) .legalFor({s32}) .clampScalar(0, s32, s32); Index: llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp +++ llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp @@ -111,6 +111,13 @@ &Mips::ValueMappings[Mips::GPRIdx], &Mips::ValueMappings[Mips::GPRIdx]}); break; + case G_SELECT: + OperandsMapping = + getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], + &Mips::ValueMappings[Mips::GPRIdx], + &Mips::ValueMappings[Mips::GPRIdx], + &Mips::ValueMappings[Mips::GPRIdx]}); + break; default: return getInvalidInstructionMapping(); } Index: llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir =================================================================== --- llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir +++ llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/select.mir @@ -0,0 +1,72 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 +--- | + + define void @select_i32() {entry: ret void} + define void @select_ptr() {entry: ret void} + +... +--- +name: select_i32 +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1, $a2 + + ; MIPS32-LABEL: name: select_i32 + ; MIPS32: liveins: $a0, $a1, $a2 + ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2 + ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0 + ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1 + ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]] + ; MIPS32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]] + ; MIPS32: $v0 = COPY [[MOVN_I_I]] + ; MIPS32: RetRA implicit $v0 + %3:gprb(s32) = COPY $a0 + %1:gprb(s32) = COPY $a1 + %2:gprb(s32) = COPY $a2 + %6:gprb(s32) = G_CONSTANT i32 1 + %7:gprb(s32) = COPY %3(s32) + %5:gprb(s32) = G_AND %7, %6 + %4:gprb(s32) = G_SELECT %5(s32), %1, %2 + $v0 = COPY %4(s32) + RetRA implicit $v0 + +... +--- +name: select_ptr +alignment: 2 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1, $a2 + + ; MIPS32-LABEL: name: select_ptr + ; MIPS32: liveins: $a0, $a1, $a2 + ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2 + ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi 0 + ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi [[LUi]], 1 + ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]] + ; MIPS32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY1]], [[AND]], [[COPY2]] + ; MIPS32: $v0 = COPY [[MOVN_I_I]] + ; MIPS32: RetRA implicit $v0 + %3:gprb(s32) = COPY $a0 + %1:gprb(p0) = COPY $a1 + %2:gprb(p0) = COPY $a2 + %6:gprb(s32) = G_CONSTANT i32 1 + %7:gprb(s32) = COPY %3(s32) + %5:gprb(s32) = G_AND %7, %6 + %4:gprb(p0) = G_SELECT %5(s32), %1, %2 + $v0 = COPY %4(p0) + RetRA implicit $v0 + +... Index: llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/select.mir =================================================================== --- llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/select.mir +++ llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/select.mir @@ -0,0 +1,172 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 +--- | + + define void @select_i8() {entry: ret void} + define void @select_i16() {entry: ret void} + define void @select_i32() {entry: ret void} + define void @select_ptr() {entry: ret void} + define void @select_with_negation() {entry: ret void} + +... +--- +name: select_i8 +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1, $a2 + + ; MIPS32-LABEL: name: select_i8 + ; MIPS32: liveins: $a0, $a1, $a2 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) + ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]] + ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY3]], [[COPY4]] + ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) + ; MIPS32: $v0 = COPY [[COPY6]](s32) + ; MIPS32: RetRA implicit $v0 + %3:_(s32) = COPY $a0 + %0:_(s1) = G_TRUNC %3(s32) + %4:_(s32) = COPY $a1 + %1:_(s8) = G_TRUNC %4(s32) + %5:_(s32) = COPY $a2 + %2:_(s8) = G_TRUNC %5(s32) + %6:_(s8) = G_SELECT %0(s1), %1, %2 + %7:_(s32) = G_ANYEXT %6(s8) + $v0 = COPY %7(s32) + RetRA implicit $v0 + +... +--- +name: select_i16 +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1, $a2 + + ; MIPS32-LABEL: name: select_i16 + ; MIPS32: liveins: $a0, $a1, $a2 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) + ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]] + ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY3]], [[COPY4]] + ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32) + ; MIPS32: $v0 = COPY [[COPY6]](s32) + ; MIPS32: RetRA implicit $v0 + %3:_(s32) = COPY $a0 + %0:_(s1) = G_TRUNC %3(s32) + %4:_(s32) = COPY $a1 + %1:_(s16) = G_TRUNC %4(s32) + %5:_(s32) = COPY $a2 + %2:_(s16) = G_TRUNC %5(s32) + %6:_(s16) = G_SELECT %0(s1), %1, %2 + %7:_(s32) = G_ANYEXT %6(s16) + $v0 = COPY %7(s32) + RetRA implicit $v0 + +... +--- +name: select_i32 +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1, $a2 + + ; MIPS32-LABEL: name: select_i32 + ; MIPS32: liveins: $a0, $a1, $a2 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 + ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] + ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]] + ; MIPS32: $v0 = COPY [[SELECT]](s32) + ; MIPS32: RetRA implicit $v0 + %3:_(s32) = COPY $a0 + %0:_(s1) = G_TRUNC %3(s32) + %1:_(s32) = COPY $a1 + %2:_(s32) = COPY $a2 + %4:_(s32) = G_SELECT %0(s1), %1, %2 + $v0 = COPY %4(s32) + RetRA implicit $v0 + +... +--- +name: select_ptr +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1, $a2 + + ; MIPS32-LABEL: name: select_ptr + ; MIPS32: liveins: $a0, $a1, $a2 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2 + ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] + ; MIPS32: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]] + ; MIPS32: $v0 = COPY [[SELECT]](p0) + ; MIPS32: RetRA implicit $v0 + %3:_(s32) = COPY $a0 + %0:_(s1) = G_TRUNC %3(s32) + %1:_(p0) = COPY $a1 + %2:_(p0) = COPY $a2 + %4:_(p0) = G_SELECT %0(s1), %1, %2 + $v0 = COPY %4(p0) + RetRA implicit $v0 + +... +--- +name: select_with_negation +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1, $a2, $a3 + + ; MIPS32-LABEL: name: select_with_negation + ; MIPS32: liveins: $a0, $a1, $a2, $a3 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 + ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]] + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32) + ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32) + ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY4]], [[COPY5]] + ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[XOR]](s32) + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]] + ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY2]], [[COPY3]] + ; MIPS32: $v0 = COPY [[SELECT]](s32) + ; MIPS32: RetRA implicit $v0 + %0:_(s32) = COPY $a0 + %1:_(s32) = COPY $a1 + %2:_(s32) = COPY $a2 + %3:_(s32) = COPY $a3 + %5:_(s1) = G_CONSTANT i1 true + %4:_(s1) = G_ICMP intpred(slt), %0(s32), %1 + %6:_(s1) = G_XOR %4, %5 + %7:_(s32) = G_SELECT %6(s1), %2, %3 + $v0 = COPY %7(s32) + RetRA implicit $v0 + +... Index: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll +++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll @@ -0,0 +1,83 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32 + +define i8 @select_i8(i1 %test, i8 %a, i8 %b) { +; MIPS32-LABEL: select_i8: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: lui $1, 0 +; MIPS32-NEXT: ori $1, $1, 1 +; MIPS32-NEXT: and $1, $4, $1 +; MIPS32-NEXT: movn $6, $5, $1 +; MIPS32-NEXT: move $2, $6 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cond = select i1 %test, i8 %a, i8 %b + ret i8 %cond +} + +define i16 @select_i16(i1 %test, i16 %a, i16 %b) { +; MIPS32-LABEL: select_i16: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: lui $1, 0 +; MIPS32-NEXT: ori $1, $1, 1 +; MIPS32-NEXT: and $1, $4, $1 +; MIPS32-NEXT: movn $6, $5, $1 +; MIPS32-NEXT: move $2, $6 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cond = select i1 %test, i16 %a, i16 %b + ret i16 %cond +} + +define i32 @select_i32(i1 %test, i32 %a, i32 %b) { +; MIPS32-LABEL: select_i32: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: lui $1, 0 +; MIPS32-NEXT: ori $1, $1, 1 +; MIPS32-NEXT: and $1, $4, $1 +; MIPS32-NEXT: movn $6, $5, $1 +; MIPS32-NEXT: move $2, $6 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cond = select i1 %test, i32 %a, i32 %b + ret i32 %cond +} + +define i32* @select_ptr(i1 %test, i32* %a, i32* %b) { +; MIPS32-LABEL: select_ptr: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: lui $1, 0 +; MIPS32-NEXT: ori $1, $1, 1 +; MIPS32-NEXT: and $1, $4, $1 +; MIPS32-NEXT: movn $6, $5, $1 +; MIPS32-NEXT: move $2, $6 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cond = select i1 %test, i32* %a, i32* %b + ret i32* %cond +} + +define i32 @select_with_negation(i32 %a, i32 %b, i32 %x, i32 %y) { +; MIPS32-LABEL: select_with_negation: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: lui $1, 65535 +; MIPS32-NEXT: ori $1, $1, 65535 +; MIPS32-NEXT: slt $4, $4, $5 +; MIPS32-NEXT: xor $1, $4, $1 +; MIPS32-NEXT: lui $4, 0 +; MIPS32-NEXT: ori $4, $4, 1 +; MIPS32-NEXT: and $1, $1, $4 +; MIPS32-NEXT: movn $7, $6, $1 +; MIPS32-NEXT: move $2, $7 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %cmp = icmp slt i32 %a, %b + %lneg = xor i1 %cmp, true + %cond = select i1 %lneg, i32 %x, i32 %y + ret i32 %cond +} Index: llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir =================================================================== --- llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir +++ llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/select.mir @@ -0,0 +1,70 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 +--- | + + define void @select_i32(i32, i32) {entry: ret void} + define void @select_ptr(i32, i32) {entry: ret void} + +... +--- +name: select_i32 +alignment: 2 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1, $a2 + + ; MIPS32-LABEL: name: select_i32 + ; MIPS32: liveins: $a0, $a1, $a2 + ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY $a2 + ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 + ; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32) + ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]] + ; MIPS32: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]] + ; MIPS32: $v0 = COPY [[SELECT]](s32) + ; MIPS32: RetRA implicit $v0 + %3:_(s32) = COPY $a0 + %1:_(s32) = COPY $a1 + %2:_(s32) = COPY $a2 + %6:_(s32) = G_CONSTANT i32 1 + %7:_(s32) = COPY %3(s32) + %5:_(s32) = G_AND %7, %6 + %4:_(s32) = G_SELECT %5(s32), %1, %2 + $v0 = COPY %4(s32) + RetRA implicit $v0 + +... +--- +name: select_ptr +alignment: 2 +legalized: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1, $a2 + + ; MIPS32-LABEL: name: select_ptr + ; MIPS32: liveins: $a0, $a1, $a2 + ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:gprb(p0) = COPY $a2 + ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1 + ; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[COPY]](s32) + ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C]] + ; MIPS32: [[SELECT:%[0-9]+]]:gprb(p0) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]] + ; MIPS32: $v0 = COPY [[SELECT]](p0) + ; MIPS32: RetRA implicit $v0 + %3:_(s32) = COPY $a0 + %1:_(p0) = COPY $a1 + %2:_(p0) = COPY $a2 + %6:_(s32) = G_CONSTANT i32 1 + %7:_(s32) = COPY %3(s32) + %5:_(s32) = G_AND %7, %6 + %4:_(p0) = G_SELECT %5(s32), %1, %2 + $v0 = COPY %4(p0) + RetRA implicit $v0 + +...