Index: include/llvm/Support/ARMTargetParser.h
===================================================================
--- include/llvm/Support/ARMTargetParser.h
+++ include/llvm/Support/ARMTargetParser.h
@@ -45,6 +45,7 @@
AEK_SHA2 = 1 << 15,
AEK_AES = 1 << 16,
AEK_FP16FML = 1 << 17,
+ AEK_SB = 1 << 18,
// Unsupported extensions.
AEK_OS = 0x8000000,
AEK_IWMMXT = 0x10000000,
Index: include/llvm/Support/ARMTargetParser.def
===================================================================
--- include/llvm/Support/ARMTargetParser.def
+++ include/llvm/Support/ARMTargetParser.def
@@ -158,6 +158,7 @@
ARM_ARCH_EXT_NAME("maverick", ARM::AEK_MAVERICK, nullptr, nullptr)
ARM_ARCH_EXT_NAME("xscale", ARM::AEK_XSCALE, nullptr, nullptr)
ARM_ARCH_EXT_NAME("fp16fml", ARM::AEK_FP16FML, "+fp16fml", "-fp16fml")
+ARM_ARCH_EXT_NAME("sb", ARM::AEK_SB, "+sb", "-sb")
#undef ARM_ARCH_EXT_NAME
#ifndef ARM_HW_DIV_NAME
Index: lib/Target/ARM/ARM.td
===================================================================
--- lib/Target/ARM/ARM.td
+++ lib/Target/ARM/ARM.td
@@ -368,6 +368,9 @@
def FeatureSpecCtrl : SubtargetFeature<"specctrl", "HasSpecCtrl", "true",
"Enable speculation control barrier" >;
+def FeatureSB : SubtargetFeature<"sb", "HasSB", "true",
+ "Enable v8.5a Speculation Barrier" >;
+
//===----------------------------------------------------------------------===//
// ARM architecture class
//
@@ -459,7 +462,8 @@
def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true",
"Support ARM v8.5a instructions",
- [HasV8_4aOps, FeatureSpecCtrl]>;
+ [HasV8_4aOps, FeatureSpecCtrl,
+ FeatureSB]>;
//===----------------------------------------------------------------------===//
// ARM Processor subtarget features.
Index: lib/Target/ARM/ARMInstrInfo.td
===================================================================
--- lib/Target/ARM/ARMInstrInfo.td
+++ lib/Target/ARM/ARMInstrInfo.td
@@ -397,6 +397,8 @@
// Armv8.5-A extensions
def HasSpecCtrl : Predicate<"Subtarget->hasSpecCtrl()">,
AssemblerPredicate<"FeatureSpecCtrl", "specctrl">;
+def HasSB : Predicate<"Subtarget->hasSB()">,
+ AssemblerPredicate<"FeatureSB", "sb">;
//===----------------------------------------------------------------------===//
// ARM Flag Definitions.
@@ -4895,7 +4897,7 @@
// Armv8.5-A speculation barrier
def SB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "sb", "", []>,
- Requires<[IsARM, HasSpecCtrl]>, Sched<[]> {
+ Requires<[IsARM, HasSB]>, Sched<[]> {
let Inst{31-0} = 0xf57ff070;
let Unpredictable = 0x000fff0f;
let hasSideEffects = 1;
Index: lib/Target/ARM/ARMInstrThumb2.td
===================================================================
--- lib/Target/ARM/ARMInstrThumb2.td
+++ lib/Target/ARM/ARMInstrThumb2.td
@@ -3239,7 +3239,7 @@
// Armv8.5-A speculation barrier
def t2SB : Thumb2XI<(outs), (ins), AddrModeNone, 4, NoItinerary, "sb", "", []>,
- Requires<[IsThumb2, HasSpecCtrl]>, Sched<[]> {
+ Requires<[IsThumb2, HasSB]>, Sched<[]> {
let Inst{31-0} = 0xf3bf8f70;
let Unpredictable = 0x000f2f0f;
let hasSideEffects = 1;
Index: lib/Target/ARM/ARMSubtarget.h
===================================================================
--- lib/Target/ARM/ARMSubtarget.h
+++ lib/Target/ARM/ARMSubtarget.h
@@ -417,6 +417,9 @@
bool UseSjLjEH = false;
/// Has speculation barrier
+ bool HasSB = false;
+
+ /// Has speculation control
bool HasSpecCtrl = false;
/// Implicitly convert an instruction to a different one if its immediates
@@ -629,6 +632,7 @@
bool useNaClTrap() const { return UseNaClTrap; }
bool useSjLjEH() const { return UseSjLjEH; }
bool hasSpecCtrl() const { return HasSpecCtrl; }
+ bool hasSB() const { return HasSB; }
bool genLongCalls() const { return GenLongCalls; }
bool genExecuteOnly() const { return GenExecuteOnly; }
Index: test/MC/ARM/armv8.5a-sb.s
===================================================================
--- /dev/null
+++ test/MC/ARM/armv8.5a-sb.s
@@ -0,0 +1,15 @@
+// RUN: llvm-mc -triple armv8 -show-encoding -mattr=+sb < %s | FileCheck %s
+// RUN: llvm-mc -triple armv8 -show-encoding -mattr=+v8.5a < %s | FileCheck %s
+// RUN: not llvm-mc -triple armv8 -show-encoding -mattr=-sb < %s 2>&1 | FileCheck %s --check-prefix=NOSB
+// RUN: llvm-mc -triple thumbv8 -show-encoding -mattr=+sb < %s | FileCheck %s --check-prefix=THUMB
+// RUN: llvm-mc -triple thumbv8 -show-encoding -mattr=+v8.5a < %s | FileCheck %s --check-prefix=THUMB
+// RUN: not llvm-mc -triple thumbv8 -show-encoding -mattr=-sb < %s 2>&1 | FileCheck %s --check-prefix=NOSB
+
+// Flag manipulation
+sb
+
+// CHECK: sb @ encoding: [0x70,0xf0,0x7f,0xf5]
+// THUMB: sb @ encoding: [0xbf,0xf3,0x70,0x8f]
+
+// NOSB: instruction requires: sb
+// NOSB-NEXT: sb
Index: test/MC/ARM/armv8.5a-specctrl.s
===================================================================
--- test/MC/ARM/armv8.5a-specctrl.s
+++ /dev/null
@@ -1,15 +0,0 @@
-// RUN: llvm-mc -triple armv8 -show-encoding -mattr=+specctrl < %s | FileCheck %s
-// RUN: llvm-mc -triple armv8 -show-encoding -mattr=+v8.5a < %s | FileCheck %s
-// RUN: not llvm-mc -triple armv8 -show-encoding -mattr=-specctrl < %s 2>&1 | FileCheck %s --check-prefix=NOSB
-// RUN: llvm-mc -triple thumbv8 -show-encoding -mattr=+specctrl < %s | FileCheck %s --check-prefix=THUMB
-// RUN: llvm-mc -triple thumbv8 -show-encoding -mattr=+v8.5a < %s | FileCheck %s --check-prefix=THUMB
-// RUN: not llvm-mc -triple thumbv8 -show-encoding -mattr=-specctrl < %s 2>&1 | FileCheck %s --check-prefix=NOSB
-
-// Flag manipulation
-sb
-
-// CHECK: sb @ encoding: [0x70,0xf0,0x7f,0xf5]
-// THUMB: sb @ encoding: [0xbf,0xf3,0x70,0x8f]
-
-// NOSB: instruction requires: specctrl
-// NOSB-NEXT: sb
Index: test/MC/Disassembler/ARM/armv8.5a-sb-thumb.txt
===================================================================
--- /dev/null
+++ test/MC/Disassembler/ARM/armv8.5a-sb-thumb.txt
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple=thumbv8 -mattr=+sb -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=thumbv8 -mattr=+v8.5a -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=thumbv8 -mattr=-sb -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
+
+0xbf 0xf3 0x70 0x8f
+
+# CHECK: sb
+# NOSB: invalid instruction encoding
+# NOSB-NEXT: 0xbf 0xf3 0x70 0x8f
Index: test/MC/Disassembler/ARM/armv8.5a-sb.txt
===================================================================
--- test/MC/Disassembler/ARM/armv8.5a-sb.txt
+++ test/MC/Disassembler/ARM/armv8.5a-sb.txt
@@ -1,6 +1,6 @@
-# RUN: llvm-mc -triple=armv8 -mattr=+specctrl -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=armv8 -mattr=+sb -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=armv8 -mattr=+v8.5a -disassemble < %s | FileCheck %s
-# RUN: llvm-mc -triple=armv8 -mattr=-specctrl -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
+# RUN: llvm-mc -triple=armv8 -mattr=-sb -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
0x70 0xf0 0x7f 0xf5
Index: test/MC/Disassembler/ARM/armv8.5a-specctrl-thumb.txt
===================================================================
--- test/MC/Disassembler/ARM/armv8.5a-specctrl-thumb.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-# RUN: llvm-mc -triple=thumbv8 -mattr=+specctrl -disassemble < %s | FileCheck %s
-# RUN: llvm-mc -triple=thumbv8 -mattr=+v8.5a -disassemble < %s | FileCheck %s
-# RUN: llvm-mc -triple=thumbv8 -mattr=-specctrl -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
-
-0xbf 0xf3 0x70 0x8f
-
-# CHECK: sb
-# NOSB: invalid instruction encoding
-# NOSB-NEXT: 0xbf 0xf3 0x70 0x8f
Index: unittests/Support/TargetParserTest.cpp
===================================================================
--- unittests/Support/TargetParserTest.cpp
+++ unittests/Support/TargetParserTest.cpp
@@ -584,7 +584,8 @@
{"iwmmxt", "noiwmmxt", nullptr, nullptr},
{"iwmmxt2", "noiwmmxt2", nullptr, nullptr},
{"maverick", "maverick", nullptr, nullptr},
- {"xscale", "noxscale", nullptr, nullptr}};
+ {"xscale", "noxscale", nullptr, nullptr},
+ {"sb", "nosb", "+sb", "-sb"}};
for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
EXPECT_EQ(StringRef(ArchExt[i][2]), ARM::getArchExtFeature(ArchExt[i][0]));