Index: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -14389,7 +14389,7 @@
     return SDValue();
 
   SDLoc DL(N);
-  SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i64);
+  SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Glue);
   SDValue Cmp = RHS.getOperand(0);
   SDValue Z = Cmp.getOperand(0);
   auto *Constant = dyn_cast<ConstantSDNode>(Cmp.getOperand(1));
Index: llvm/trunk/test/CodeGen/PowerPC/adde_return_type.ll
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/adde_return_type.ll
+++ llvm/trunk/test/CodeGen/PowerPC/adde_return_type.ll
@@ -0,0 +1,11 @@
+; REQUIRES: asserts
+; RUN: llc -mtriple=powerpc64le-unknown-unknown -debug-only=legalize-types \
+; RUN:   < %s -o /dev/null 2>&1 | FileCheck %s
+
+define i64 @testAddeReturnType(i64 %X, i64 %Z) {
+; CHECK: Legally typed node: {{.*}}: i64,glue = adde {{.*}} 
+  %cmp = icmp ne i64 %Z, 0
+  %conv1 = zext i1 %cmp to i64
+  %add = add nsw i64 %conv1, %X
+  ret i64 %add
+}