Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1105,6 +1105,37 @@ "nop instruction"); } + if (inMicroMipsMode()) { + MCOperand Opnd; + unsigned Opcode = Inst.getOpcode(); + + switch (Opcode) { + default: + break; + case Mips::SWM_MM16: + case Mips::LWM_MM16: + unsigned opNum = Inst.getNumOperands(); + if (opNum < 8 && (Inst.getOperand(opNum - 1).isImm() + && (Inst.getOperand(opNum - 1).getImm() < 32)) + && (Inst.getOperand(opNum - 2).isReg() + && (Inst.getOperand(opNum - 2).getReg() == Mips::SP)) + && (Inst.getOperand(0).isReg() + && (Inst.getOperand(0).getReg() == Mips::RA))) + // It can be implemented as SWM16 or LWM16 instruction - no need to + // change opcode. + break; + else if (Inst.getOperand(opNum - 1).isImm() + && (Inst.getOperand(opNum - 1).getImm() < 32)) + // It can be implemented as SWM32 or LWM32 instruction - change opcode. + Inst.setOpcode(Opcode == Mips::SWM_MM16 ? Mips::SWM_MM : Mips::LWM_MM); + else + // Offset is out of range - error. + return Error(IDLoc, "Illegal operand"); + + break; + } + } + if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder()) { // If this instruction has a delay slot and .set reorder is active, // emit a NOP after it. Index: lib/Target/Mips/Disassembler/MipsDisassembler.cpp =================================================================== --- lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -354,6 +354,11 @@ uint64_t Address, const void *Decoder); +static DecodeStatus DecodeRegListOperand16(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + namespace llvm { extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, TheMips64elTarget; @@ -1430,3 +1435,23 @@ return MCDisassembler::Success; } + +static DecodeStatus DecodeRegListOperand16(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) { + unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; + unsigned RegNum; + + unsigned RegLst = fieldFromInstruction(Insn, 4, 2); + // Empty register lists are not allowed. + if (RegLst == 0) return MCDisassembler::Fail; + + RegNum = RegLst & 0x3; + for (unsigned i = 0; i < RegNum - 1; i++) + Inst.addOperand(MCOperand::CreateReg(Regs[i])); + + Inst.addOperand(MCOperand::CreateReg(Mips::RA)); + + return MCDisassembler::Success; +} Index: lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp =================================================================== --- lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp +++ lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp @@ -233,6 +233,8 @@ break; case Mips::SWM_MM: case Mips::LWM_MM: + case Mips::SWM_MM16: + case Mips::LWM_MM16: opNum = MI->getNumOperands() - 2; break; } Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h +++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h @@ -131,6 +131,9 @@ unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + unsigned getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; @@ -157,6 +160,10 @@ unsigned getRegisterListOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + + unsigned getRegisterListOpValue16(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; }; // class MipsMCCodeEmitter } // namespace llvm. Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -615,6 +615,30 @@ return (OffBits & 0x0FFF) | RegBits; } +unsigned MipsMCCodeEmitter:: +getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + // opNum can be invalid if instruction had reglist as operand + // MemOperand is always last operand of instruction (base + offset) + switch (MI.getOpcode()) { + default: + break; + case Mips::SWM_MM16: + case Mips::LWM_MM16: + OpNo = MI.getNumOperands() - 2; + break; + } + + // Offset is encoded in bits 4-0. + assert(MI.getOperand(OpNo).isReg()); + // Base register is always SP - thus it is not encoded. + assert(MI.getOperand(OpNo+1).isImm()); + unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); + + return ((OffBits >> 1) & 0x0F); +} + unsigned MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, @@ -709,4 +733,11 @@ return res; } +unsigned +MipsMCCodeEmitter::getRegisterListOpValue16(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + return (MI.getNumOperands() - 4); +} + #include "MipsGenMCCodeEmitter.inc" Index: lib/Target/Mips/MicroMipsInstrFormats.td =================================================================== --- lib/Target/Mips/MicroMipsInstrFormats.td +++ lib/Target/Mips/MicroMipsInstrFormats.td @@ -666,3 +666,15 @@ let Inst{15-12} = funct; let Inst{11-0} = addr{11-0}; } + +class LWM_FM_MM16 funct> : MMArch { + bits<2> rt; + bits<4> addr; + + bits<16> Inst; + + let Inst{15-10} = 0x11; + let Inst{9-6} = funct; + let Inst{5-4} = rt; + let Inst{3-0} = addr; +} Index: lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsInstrInfo.td +++ lib/Target/Mips/MicroMipsInstrInfo.td @@ -16,6 +16,14 @@ let OperandType = "OPERAND_MEMORY"; } +def mem_mm_4sp : Operand { + let PrintMethod = "printMemOperand"; + let MIOperandInfo = (ops GPR32, uimm8); + let EncoderMethod = "getMemEncodingMMImm4sp"; + let ParserMatchClass = MipsMemAsmOperand; + let OperandType = "OPERAND_MEMORY"; +} + def jmptarget_mm : Operand { let EncoderMethod = "getJumpTargetOpValueMM"; } @@ -150,6 +158,13 @@ let DecoderMethod = "DecodeRegListOperand"; } +def reglist16 : Operand { + let EncoderMethod = "getRegisterListOpValue16"; + let ParserMatchClass = RegListAsmOperand; + let PrintMethod = "printRegisterList"; + let DecoderMethod = "DecodeRegListOperand16"; +} + class StoreMultMM : InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr), @@ -166,6 +181,20 @@ let mayLoad = 1; } +class StoreMultMM16 : + MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr), + !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> { + let mayStore = 1; +} + +class LoadMultMM16 : + MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr), + !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> { + let mayLoad = 1; +} + def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>; def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>; def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>; @@ -273,6 +302,8 @@ /// Load and Store Instructions - multiple def SWM_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>; def LWM_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>; + def SWM_MM16 : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>; + def LWM_MM16 : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>; /// Move Conditional def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, Index: test/MC/Mips/micromips-invalid.s =================================================================== --- test/MC/Mips/micromips-invalid.s +++ test/MC/Mips/micromips-invalid.s @@ -7,4 +7,10 @@ swm $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected swm $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected swm $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand + lwm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected + lwm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected + lwm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand + swm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected + swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected + swm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand Index: test/MC/Mips/micromips-loadstore-instructions.s =================================================================== --- test/MC/Mips/micromips-loadstore-instructions.s +++ test/MC/Mips/micromips-loadstore-instructions.s @@ -24,6 +24,8 @@ # CHECK-EL: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x84,0x20,0x08,0x50] # CHECK-EL: swm32 $16, $17, 8($4) # encoding: [0x44,0x20,0x08,0xd0] # CHECK-EL: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x84,0x20,0x08,0xd0] +# CHECK-EL: lwm16 $ra, $16, $17, 8($sp) # encoding: [0x14,0x45] +# CHECK-EL: swm16 $ra, $16, $17, 8($sp) # encoding: [0x54,0x45] #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ @@ -38,6 +40,8 @@ # CHECK-EB: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0x50,0x08] # CHECK-EB: swm32 $16, $17, 8($4) # encoding: [0x20,0x44,0xd0,0x08] # CHECK-EB: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0xd0,0x08] +# CHECK-EB: lwm16 $ra, $16, $17, 8($sp) # encoding: [0x45,0x14] +# CHECK-EB: swm16 $ra, $16, $17, 8($sp) # encoding: [0x45,0x54] lb $5, 8($4) lbu $6, 8($4) lh $2, 8($4) @@ -53,3 +57,5 @@ lwm $16 - $19, 8($4) swm $16, $17, 8($4) swm $16 - $19, 8($4) + lwm16 $16, $17, $ra, 8($sp) + swm16 $16, $17, $ra, 8($sp)