Index: test/MC/PowerPC/ppc-reloc.s
===================================================================
--- test/MC/PowerPC/ppc-reloc.s
+++ test/MC/PowerPC/ppc-reloc.s
@@ -7,6 +7,8 @@
 	.align 2
 foo:
 	bl printf@plt
+	bl printf
+	beq printf
 	bl _GLOBAL_OFFSET_TABLE_@local-4
 .LC1:
 	.size foo, . - foo
@@ -14,6 +16,8 @@
 # CHECK:      Relocations [
 # CHECK-NEXT:   Section {{.*}} .rela.text {
 # CHECK-NEXT:     0x0 R_PPC_PLTREL24 printf 0x0
-# CHECK-NEXT:     0x4 R_PPC_LOCAL24PC _GLOBAL_OFFSET_TABLE_ 0xFFFFFFFC
+# CHECK-NEXT:     0x4 R_PPC_REL24 printf 0x0
+# CHECK-NEXT:     0x8 R_PPC_REL14 printf 0x0
+# CHECK-NEXT:     0xC R_PPC_LOCAL24PC _GLOBAL_OFFSET_TABLE_ 0xFFFFFFFC
 # CHECK-NEXT:   }
 # CHECK-NEXT: ]
Index: test/MC/PowerPC/ppc64-relocs-01.s
===================================================================
--- test/MC/PowerPC/ppc64-relocs-01.s
+++ test/MC/PowerPC/ppc64-relocs-01.s
@@ -10,6 +10,7 @@
 .L.access_int64:
         ld 4, .LC1@toc(2)
         bl sin
+        beq sin
 
         .section .toc,"aw",@progbits
 .LC1:
@@ -27,6 +28,7 @@
 # CHECK:        Section ({{[0-9]+}}) .rela.text {
 # CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_DS .toc
 # CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_REL24    sin
+# CHECK-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_REL14    sin
 # CHECK-NEXT:   }
 
 # The .opd entry for the 'access_int64' function creates 2 relocations:
Index: test/tools/llvm-readobj/Inputs/relocs.py
===================================================================
--- test/tools/llvm-readobj/Inputs/relocs.py
+++ test/tools/llvm-readobj/Inputs/relocs.py
@@ -563,6 +563,9 @@
   R_PPC64_ADDR16_HI           = 5
   R_PPC64_ADDR14              = 7
   R_PPC64_REL24               = 10
+  R_PPC64_REL14               = 11
+  R_PPC64_REL14_BRTAKEN       = 12
+  R_PPC64_REL14_BRNTAKEN      = 13
   R_PPC64_REL32               = 26
   R_PPC64_ADDR64              = 38
   R_PPC64_ADDR16_HIGHER       = 39