Index: lib/Target/ARM/ARMTargetTransformInfo.h =================================================================== --- lib/Target/ARM/ARMTargetTransformInfo.h +++ lib/Target/ARM/ARMTargetTransformInfo.h @@ -94,6 +94,8 @@ bool enableInterleavedAccessVectorization() { return true; } + bool shouldFavorPostInc() const { return ST->isMClass() && ST->isThumb2(); } + /// Floating-point computation using ARMv8 AArch32 Advanced /// SIMD instructions remains unchanged from ARMv7. Only AArch64 SIMD /// is IEEE-754 compliant, but it's not covered in this target. Index: lib/Transforms/Scalar/LoopStrengthReduce.cpp =================================================================== --- lib/Transforms/Scalar/LoopStrengthReduce.cpp +++ lib/Transforms/Scalar/LoopStrengthReduce.cpp @@ -1208,12 +1208,26 @@ bool HasBaseReg, int64_t Scale, Instruction *Fixup = nullptr); +static const SCEVConstant* GetConstantStart(const SCEV *S) { + if (auto *C = dyn_cast(S)) + return C; + + if (auto *AddRec = dyn_cast(S)) + return GetConstantStart(AddRec->getStart()); + + if (auto *Add = dyn_cast(S)) + return GetConstantStart(Add->getOperand(0)); + + return nullptr; +} + /// Tally up interesting quantities from the given register. void Cost::RateRegister(const SCEV *Reg, SmallPtrSetImpl &Regs, const Loop *L, ScalarEvolution &SE, DominatorTree &DT, const TargetTransformInfo &TTI) { + unsigned NumRegs = 1; if (const SCEVAddRecExpr *AR = dyn_cast(Reg)) { // If this is an addrec for another loop, it should be an invariant // with respect to L since L is the innermost loop (at least @@ -1236,17 +1250,28 @@ } unsigned LoopCost = 1; - if (TTI.shouldFavorPostInc()) { + if (TTI.shouldFavorPostInc() && + (TTI.isIndexedLoadLegal(TTI.MIM_PostInc, AR->getType()) || + TTI.isIndexedStoreLegal(TTI.MIM_PostInc, AR->getType()))) { + + if (isa(AR->getOperand(1))) { + if (auto *Start = GetConstantStart(AR)) { + const APInt &StartInt = Start->getAPInt(); + const APInt &ARInt = cast(AR->getOperand(1))->getAPInt(); + // We can turn this access into a post increment as the initial offset + // required matches the recurrence. + if ((StartInt.isNegative() && StartInt.abs() == ARInt) || + (ARInt.isNegative() && ARInt.abs() == StartInt)) + NumRegs = 0; + } + } + const SCEV *LoopStep = AR->getStepRecurrence(SE); if (isa(LoopStep)) { - // Check if a post-indexed load/store can be used. - if (TTI.isIndexedLoadLegal(TTI.MIM_PostInc, AR->getType()) || - TTI.isIndexedStoreLegal(TTI.MIM_PostInc, AR->getType())) { - const SCEV *LoopStart = AR->getStart(); - if (!isa(LoopStart) && + const SCEV *LoopStart = AR->getStart(); + if (!isa(LoopStart) && SE.isLoopInvariant(LoopStart, L)) - LoopCost = 0; - } + LoopCost = 0; } } C.AddRecCost += LoopCost; @@ -1261,8 +1286,8 @@ } } } - ++C.NumRegs; + C.NumRegs += NumRegs; // Rough heuristic; favor registers which don't require extra setup // instructions in the preheader. if (!isa(Reg) && @@ -3738,8 +3763,8 @@ void LSRInstance::GenerateConstantOffsetsImpl( LSRUse &LU, unsigned LUIdx, const Formula &Base, const SmallVectorImpl &Worklist, size_t Idx, bool IsScaledReg) { - const SCEV *G = IsScaledReg ? Base.ScaledReg : Base.BaseRegs[Idx]; - for (int64_t Offset : Worklist) { + + auto GenerateOffset = [&](const SCEV *G, int64_t Offset) { Formula F = Base; F.BaseOffset = (uint64_t)Base.BaseOffset - Offset; if (isLegalUse(TTI, LU.MinOffset - Offset, LU.MaxOffset - Offset, LU.Kind, @@ -3761,8 +3786,28 @@ (void)InsertFormula(LU, LUIdx, F); } + }; + + const SCEV *G = IsScaledReg ? Base.ScaledReg : Base.BaseRegs[Idx]; + + if (TTI.shouldFavorPostInc()) { + if (auto *GAddRec = dyn_cast(G)) { + if (auto *StepSCEV = GetConstantStart(GAddRec->getStepRecurrence(SE))) { + const APInt &StepInt = StepSCEV->getAPInt(); + int64_t Step = StepInt.isNegative() ? + StepInt.getSExtValue() : StepInt.getZExtValue(); + + for (int64_t Offset : Worklist) { + Offset -= Step; + GenerateOffset(G, Offset); + } + } + } } + for (int64_t Offset : Worklist) + GenerateOffset(G, Offset); + int64_t Imm = ExtractImmediate(G, SE); if (G->isZero() || Imm == 0) return; Index: test/CodeGen/ARM/dsp-post-incs.ll =================================================================== --- /dev/null +++ test/CodeGen/ARM/dsp-post-incs.ll @@ -0,0 +1,414 @@ +; RUN: llc -mtriple=thumbv8m.main -mattr=+dsp,+fp-armv8 %s -o - | FileCheck %s + +; Tests to check that post increment addressing modes are used instead of +; updating base pointers with add instructions. + +; CHECK-LABEL: test_qadd_2 +; CHECK: sub{{.*}} [[A:r[0-9]+]], r0, #8 +; CHECK: subs [[B:r[0-9]+]], #8 +; CHECK: subs [[OUT:r[0-9]+]], #8 + +; CHECK: ldr{{.*}}, {{\[}}[[B]], #8]! +; CHECK: ldr{{.*}}, {{\[}}[[A]], #8]! +; CHECK: str{{.*}}, {{\[}}[[OUT]], #8]! +; CHECK: ldr{{.*}}, {{\[}}[[B]], #4] +; CHECK: ldr{{.*}}, {{\[}}[[A]], #4] +; CHECK: str{{.*}}, {{\[}}[[OUT]], #4] +; CHECK: blo +define void @test_qadd_2(i32* %a.array, i32* %b.array, i32* %out.array, i32 %N) { +entry: + br label %loop + +loop: + %i = phi i32 [ 0, %entry ], [ %i.next, %loop ] + %idx.1 = phi i32 [ 0, %entry ], [ %idx.next, %loop ] + %gep.a.1 = getelementptr inbounds i32, i32* %a.array, i32 %idx.1 + %a.1 = load i32, i32* %gep.a.1 + %gep.b.1 = getelementptr inbounds i32, i32* %b.array, i32 %idx.1 + %b.1 = load i32, i32* %gep.b.1 + %qadd.1 = call i32 @llvm.arm.qadd(i32 %a.1, i32 %b.1) + %addr.1 = getelementptr inbounds i32, i32* %out.array, i32 %idx.1 + store i32 %qadd.1, i32* %addr.1 + %idx.2 = or i32 %idx.1, 1 + %gep.a.2 = getelementptr inbounds i32, i32* %a.array, i32 %idx.2 + %a.2 = load i32, i32* %gep.a.2 + %gep.b.2 = getelementptr inbounds i32, i32* %b.array, i32 %idx.2 + %b.2 = load i32, i32* %gep.b.2 + %qadd.2 = call i32 @llvm.arm.qadd(i32 %a.2, i32 %b.2) + %addr.2 = getelementptr inbounds i32, i32* %out.array, i32 %idx.2 + store i32 %qadd.2, i32* %addr.2 + %i.next = add nsw nuw i32 %i, -2 + %idx.next = add nsw nuw i32 %idx.1, 2 + %cmp = icmp ult i32 %i.next, %N + br i1 %cmp, label %loop, label %exit + +exit: + ret void +} + +; CHECK-LABEl: test_qadd_2_backwards + +; CHECK: [[shift:[rl0-9]+]], r3, #2 +; CHECK: add{{.*}} [[A:r[0-9]+]], r0, [[shift]], lsl #2 +; CHECK: add{{.*}} [[B:r[0-9]+]], r1, [[shift]], lsl #2 +; CHECK: add{{.*}} [[OUT:r[0-9]+]], r2, [[shift]], lsl #2 + +; CHECK: ldr{{.*}}, {{\[}}[[B]], #-8]! +; CHECK: ldr{{.*}}, {{\[}}[[A]], #-8]! +; CHECK: str{{.*}}, {{\[}}[[OUT]], #-8]! +; CHECK: ldr{{.*}}, {{\[}}[[B]], #-4] +; CHECK: ldr{{.*}}, {{\[}}[[A]], #-4] +; CHECK: str{{.*}}, {{\[}}[[OUT]], #-4] +; CHECK: blo +define void @test_qadd_2_backwards(i32* %a.array, i32* %b.array, i32* %out.array, i32 %N) { +entry: + br label %loop + +loop: + %i = phi i32 [ 0, %entry ], [ %i.next, %loop ] + %idx.1 = phi i32 [ %N, %entry ], [ %idx.next, %loop ] + %gep.a.1 = getelementptr inbounds i32, i32* %a.array, i32 %idx.1 + %a.1 = load i32, i32* %gep.a.1 + %gep.b.1 = getelementptr inbounds i32, i32* %b.array, i32 %idx.1 + %b.1 = load i32, i32* %gep.b.1 + %qadd.1 = call i32 @llvm.arm.qadd(i32 %a.1, i32 %b.1) + %addr.1 = getelementptr inbounds i32, i32* %out.array, i32 %idx.1 + store i32 %qadd.1, i32* %addr.1 + %idx.2 = sub nsw nuw i32 %idx.1, 1 + %gep.a.2 = getelementptr inbounds i32, i32* %a.array, i32 %idx.2 + %a.2 = load i32, i32* %gep.a.2 + %gep.b.2 = getelementptr inbounds i32, i32* %b.array, i32 %idx.2 + %b.2 = load i32, i32* %gep.b.2 + %qadd.2 = call i32 @llvm.arm.qadd(i32 %a.2, i32 %b.2) + %addr.2 = getelementptr inbounds i32, i32* %out.array, i32 %idx.2 + store i32 %qadd.2, i32* %addr.2 + %i.next = add nsw nuw i32 %i, -2 + %idx.next = sub nsw nuw i32 %idx.1, 2 + %cmp = icmp ult i32 %i.next, %N + br i1 %cmp, label %loop, label %exit + +exit: + ret void +} + +; CHECK-LABEL: test_qadd_3 +; CHECK: subs [[A:r[0-9]+]], #12 +; CHECK: subs [[B:r[0-9]+]], #12 +; CHECK: subs [[OUT:r[0-9]+]], #12 + +; CHECK: ldr{{.*}}, {{\[}}[[B]], #12]! +; CHECK: ldr{{.*}}, {{\[}}[[A]], #12]! +; CHECK: str{{.*}}, {{\[}}[[OUT]], #12]! +; CHECK: ldr{{.*}}, {{\[}}[[B]], #4] +; CHECK: ldr{{.*}}, {{\[}}[[A]], #4] +; CHECK: str{{.*}}, {{\[}}[[OUT]], #4] +; CHECK: ldr{{.*}}, {{\[}}[[B]], #8] +; CHECK: ldr{{.*}}, {{\[}}[[A]], #8] +; CHECK: str{{.*}}, {{\[}}[[OUT]], #8] +; CHECK: blo +define void @test_qadd_3(i32* %a.array, i32* %b.array, i32* %out.array, i32 %N) { +entry: + br label %loop + +loop: + %i = phi i32 [ 0, %entry ], [ %i.next, %loop ] + %idx.1 = phi i32 [ 0, %entry ], [ %idx.next, %loop ] + %gep.a.1 = getelementptr inbounds i32, i32* %a.array, i32 %idx.1 + %a.1 = load i32, i32* %gep.a.1 + %gep.b.1 = getelementptr inbounds i32, i32* %b.array, i32 %idx.1 + %b.1 = load i32, i32* %gep.b.1 + %qadd.1 = call i32 @llvm.arm.qadd(i32 %a.1, i32 %b.1) + %addr.1 = getelementptr inbounds i32, i32* %out.array, i32 %idx.1 + store i32 %qadd.1, i32* %addr.1 + %idx.2 = add nuw nsw i32 %idx.1, 1 + %gep.a.2 = getelementptr inbounds i32, i32* %a.array, i32 %idx.2 + %a.2 = load i32, i32* %gep.a.2 + %gep.b.2 = getelementptr inbounds i32, i32* %b.array, i32 %idx.2 + %b.2 = load i32, i32* %gep.b.2 + %qadd.2 = call i32 @llvm.arm.qadd(i32 %a.2, i32 %b.2) + %addr.2 = getelementptr inbounds i32, i32* %out.array, i32 %idx.2 + store i32 %qadd.2, i32* %addr.2 + %idx.3 = add nuw nsw i32 %idx.1, 2 + %gep.a.3 = getelementptr inbounds i32, i32* %a.array, i32 %idx.3 + %a.3 = load i32, i32* %gep.a.3 + %gep.b.3 = getelementptr inbounds i32, i32* %b.array, i32 %idx.3 + %b.3 = load i32, i32* %gep.b.3 + %qadd.3 = call i32 @llvm.arm.qadd(i32 %a.3, i32 %b.3) + %addr.3 = getelementptr inbounds i32, i32* %out.array, i32 %idx.3 + store i32 %qadd.3, i32* %addr.3 + %i.next = add nsw nuw i32 %i, -3 + %idx.next = add nsw nuw i32 %idx.1, 3 + %cmp = icmp ult i32 %i.next, %N + br i1 %cmp, label %loop, label %exit + +exit: + ret void +} + +; CHECK-LABEL: test_qadd_4 +; CHECK: subs [[A:r[0-9]+]], #16 +; CHECK: subs [[B:r[0-9]+]], #16 +; CHECK: subs [[OUT:r[0-9]+]], #16 + +; CHECK: ldr{{.*}}, {{\[}}[[B]], #16]! +; CHECK: ldr{{.*}}, {{\[}}[[A]], #16]! +; CHECK: str{{.*}}, {{\[}}[[OUT]], #16]! +; CHECK: ldr{{.*}}, {{\[}}[[B]], #4] +; CHECK: ldr{{.*}}, {{\[}}[[A]], #4] +; CHECK: str{{.*}}, {{\[}}[[OUT]], #4] +; CHECK: ldr{{.*}}, {{\[}}[[B]], #8] +; CHECK: ldr{{.*}}, {{\[}}[[A]], #8] +; CHECK: str{{.*}}, {{\[}}[[OUT]], #8] +; CHECK: ldr{{.*}}, {{\[}}[[B]], #12] +; CHECK: ldr{{.*}}, {{\[}}[[A]], #12] +; CHECK: str{{.*}}, {{\[}}[[OUT]], #12] +; CHECK: blo +define void @test_qadd_4(i32* %a.array, i32* %b.array, i32* %out.array, i32 %N) { +entry: + br label %loop + +loop: + %i = phi i32 [ 0, %entry ], [ %i.next, %loop ] + %idx.1 = phi i32 [ 0, %entry ], [ %idx.next, %loop ] + %gep.a.1 = getelementptr inbounds i32, i32* %a.array, i32 %idx.1 + %a.1 = load i32, i32* %gep.a.1 + %gep.b.1 = getelementptr inbounds i32, i32* %b.array, i32 %idx.1 + %b.1 = load i32, i32* %gep.b.1 + %qadd.1 = call i32 @llvm.arm.qadd(i32 %a.1, i32 %b.1) + %addr.1 = getelementptr inbounds i32, i32* %out.array, i32 %idx.1 + store i32 %qadd.1, i32* %addr.1 + %idx.2 = or i32 %idx.1, 1 + %gep.a.2 = getelementptr inbounds i32, i32* %a.array, i32 %idx.2 + %a.2 = load i32, i32* %gep.a.2 + %gep.b.2 = getelementptr inbounds i32, i32* %b.array, i32 %idx.2 + %b.2 = load i32, i32* %gep.b.2 + %qadd.2 = call i32 @llvm.arm.qadd(i32 %a.2, i32 %b.2) + %addr.2 = getelementptr inbounds i32, i32* %out.array, i32 %idx.2 + store i32 %qadd.2, i32* %addr.2 + %idx.3 = or i32 %idx.1, 2 + %gep.a.3 = getelementptr inbounds i32, i32* %a.array, i32 %idx.3 + %a.3 = load i32, i32* %gep.a.3 + %gep.b.3 = getelementptr inbounds i32, i32* %b.array, i32 %idx.3 + %b.3 = load i32, i32* %gep.b.3 + %qadd.3 = call i32 @llvm.arm.qadd(i32 %a.3, i32 %b.3) + %addr.3 = getelementptr inbounds i32, i32* %out.array, i32 %idx.3 + store i32 %qadd.3, i32* %addr.3 + %idx.4 = or i32 %idx.1, 3 + %gep.a.4 = getelementptr inbounds i32, i32* %a.array, i32 %idx.4 + %a.4 = load i32, i32* %gep.a.4 + %gep.b.4 = getelementptr inbounds i32, i32* %b.array, i32 %idx.4 + %b.4 = load i32, i32* %gep.b.4 + %qadd.4 = call i32 @llvm.arm.qadd(i32 %a.4, i32 %b.4) + %addr.4 = getelementptr inbounds i32, i32* %out.array, i32 %idx.4 + store i32 %qadd.4, i32* %addr.4 + %i.next = add nsw nuw i32 %i, -4 + %idx.next = add nsw nuw i32 %idx.1, 4 + %cmp = icmp ult i32 %i.next, %N + br i1 %cmp, label %loop, label %exit + +exit: + ret void +} + +; CHECK-LABEL: test_qadd16_2 +; CHECK: sub.w [[A:r[0-9]+]], r0, #8 +; CHECK: subs [[B:r[0-9]+]], #8 +; CHECK: subs [[OUT:r[0-9]+]], #16 + +; CHECK: ldr{{.*}}, {{\[}}[[B]], #8]! +; CHECK: ldr{{.*}}, {{\[}}[[A]], #8]! +; CHECK: str{{.*}}, {{\[}}[[OUT]], #16]! +; CHECK: ldr{{.*}}, {{\[}}[[B]], #4] +; CHECK: ldr{{.*}}, {{\[}}[[A]], #4] +; CHECK: str{{.*}}, {{\[}}[[OUT]], #8] +define void @test_qadd16_2(i16* %a.array, i16* %b.array, i32* %out.array, i32 %N) { +entry: + br label %loop + +loop: + %i = phi i32 [ 0, %entry ], [ %i.next, %loop ] + %idx.1 = phi i32 [ 0, %entry ], [ %idx.next, %loop ] + %gep.a.1 = getelementptr inbounds i16, i16* %a.array, i32 %idx.1 + %cast.a.1 = bitcast i16* %gep.a.1 to i32* + %a.1 = load i32, i32* %cast.a.1 + %gep.b.1 = getelementptr inbounds i16, i16* %b.array, i32 %idx.1 + %cast.b.1 = bitcast i16* %gep.b.1 to i32* + %b.1 = load i32, i32* %cast.b.1 + %qadd.1 = call i32 @llvm.arm.qadd16(i32 %a.1, i32 %b.1) + %addr.1 = getelementptr inbounds i32, i32* %out.array, i32 %idx.1 + store i32 %qadd.1, i32* %addr.1 + %idx.2 = add nsw nuw i32 %idx.1, 2 + %gep.a.2 = getelementptr inbounds i16, i16* %a.array, i32 %idx.2 + %cast.a.2 = bitcast i16* %gep.a.2 to i32* + %a.2 = load i32, i32* %cast.a.2 + %gep.b.2 = getelementptr inbounds i16, i16* %b.array, i32 %idx.2 + %cast.b.2 = bitcast i16* %gep.b.2 to i32* + %b.2 = load i32, i32* %cast.b.2 + %qadd.2 = call i32 @llvm.arm.qadd16(i32 %a.2, i32 %b.2) + %addr.2 = getelementptr inbounds i32, i32* %out.array, i32 %idx.2 + store i32 %qadd.2, i32* %addr.2 + %i.next = add nsw nuw i32 %i, -2 + %idx.next = add nsw nuw i32 %idx.1, 4 + %cmp = icmp ult i32 %i.next, %N + br i1 %cmp, label %loop, label %exit + +exit: + ret void +} + +; TODO: I think we should be able to use post inc addressing with VLDM +; instructions. +; CHECK-LABEL: test_fma +; CHECK: subs [[A:r[0-9]+]], #8 +; CHECK: subs [[B:r[0-9]+]], #8 + +; CHECK: vldr s{{.*}}, {{\[}}[[B]], #8] +; CHECK: vldr s{{.*}}, {{\[}}[[A]], #8] +; CHECK: vldr s{{.*}}, {{\[}}[[B]], #12] +; CHECK: vldr s{{.*}}, {{\[}}[[A]], #12] +define float @test_fma(float* %a, float* %b, i32 %N) { +entry: + br label %loop + +loop: + %i = phi i32 [ 0, %entry ], [ %i.next, %loop ] + %idx.1 = phi i32 [ 0, %entry ], [ %idx.next, %loop ] + %res = phi float [ 0.0, %entry ], [ %fma.2, %loop ] + %gep.a.1 = getelementptr inbounds float, float* %a, i32 %idx.1 + %a.1 = load float, float* %gep.a.1 + %gep.b.1 = getelementptr inbounds float, float* %b, i32 %idx.1 + %b.1 = load float, float* %gep.b.1 + %fmul.1 = fmul float %a.1, %b.1 + %fma.1 = fadd float %fmul.1, %res + %idx.2 = or i32 %idx.1, 1 + %gep.a.2 = getelementptr inbounds float, float* %a, i32 %idx.2 + %a.2 = load float, float* %gep.a.2 + %gep.b.2 = getelementptr inbounds float, float* %b, i32 %idx.2 + %b.2 = load float, float* %gep.b.2 + %fmul.2 = fmul float %a.2, %b.2 + %fma.2 = fadd float %fmul.2, %fma.1 + %i.next = add nsw nuw i32 %i, -2 + %idx.next = add nsw nuw i32 %idx.1, 2 + %cmp = icmp ult i32 %i.next, %N + br i1 %cmp, label %loop, label %exit + +exit: + ret float %fma.2 +} + +; CHECK-LABEL: convolve_16bit + +; CHECK: ldr.w {{.*}}, [{{.*}}, lsl #2] +; CHECK: ldr.w [[pA:r[rl0-9]+]], [{{.*}}, lsl #2] +; CHECK: ldr.w [[pB:[rl0-9]+]], [{{.*}}, lsl #2] +; CHECK: add{{.*}} [[A:[rl0-9]+]], [[pA]], {{.*}}, lsl #1 +; CHECK: sub{{.*}} [[B:[rl0-9]+]], [[pB]], #8 + +; CHECK: ldr{{.*}}, {{\[}}[[B]], #8]! +; CHECK: ldr{{.*}}, {{\[}}[[A]], #8]! +; CHECK: ldr{{.*}}, {{\[}}[[B]], #4] +; CHECK: ldr{{.*}}, {{\[}}[[A]], #4] +define void @convolve_16bit(i16** nocapture readonly %input_image, i16** nocapture readonly %filter, + i32 %filter_dim, i32 %out_width, i32 %out_height, + i32** nocapture readonly %convolved) { +entry: + %cmp92 = icmp eq i32 %out_height, 0 + br i1 %cmp92, label %for.cond.cleanup, label %for.cond1.preheader.lr.ph + +for.cond1.preheader.lr.ph: ; preds = %entry + %xtraiter = and i32 %filter_dim, 3 + %unroll_iter = sub i32 %filter_dim, %xtraiter + br label %for.cond1.preheader + +for.cond1.preheader: ; preds = %for.cond.cleanup3, %for.cond1.preheader.lr.ph + %res_y.093 = phi i32 [ 0, %for.cond1.preheader.lr.ph ], [ %add28, %for.cond.cleanup3 ] + %arrayidx22 = getelementptr inbounds i32*, i32** %convolved, i32 %res_y.093 + %tmp3 = load i32*, i32** %arrayidx22, align 4 + br label %for.cond9.preheader.us.us.preheader + +for.cond9.preheader.us.us.preheader: ; preds = %for.cond5.for.cond.cleanup7_crit_edge.us, %for.cond5.preheader.lr.ph + %res_x.060.us = phi i32 [ %add25.us, %for.cond5.for.cond.cleanup7_crit_edge.us ], [ 0, %for.cond1.preheader ] + br label %for.cond9.preheader.us.us + +for.cond9.preheader.us.us: ; preds = %for.cond9.for.cond.cleanup11_crit_edge.us.us, %for.cond9.preheader.us.us.preheader + %filter_y.056.us.us = phi i32 [ %inc20.us.us, %for.cond9.for.cond.cleanup11_crit_edge.us.us.unr-lcssa ], [ 0, %for.cond9.preheader.us.us.preheader ] + %result_element.055.us.us = phi i32 [ %add18.us.us.3, %for.cond9.for.cond.cleanup11_crit_edge.us.us.unr-lcssa ], [ 0, %for.cond9.preheader.us.us.preheader ] + %add.us.us = add i32 %filter_y.056.us.us, %res_y.093 + %arrayidx.us.us = getelementptr inbounds i16*, i16** %filter, i32 %filter_y.056.us.us + %tmp5 = load i16*, i16** %arrayidx.us.us, align 4 + %arrayidx15.us.us = getelementptr inbounds i16*, i16** %input_image, i32 %add.us.us + %tmp6 = load i16*, i16** %arrayidx15.us.us, align 4 + br label %for.body12.us.us + +for.body12.us.us: ; preds = %for.body12.us.us, %for.cond9.preheader.us.us + %filter_x.053.us.us = phi i32 [ %inc.us.us.3, %for.body12.us.us ], [ 0, %for.cond9.preheader.us.us ] + %result_element.152.us.us = phi i32 [ %add18.us.us.3, %for.body12.us.us ], [ %result_element.055.us.us, %for.cond9.preheader.us.us ] + %niter = phi i32 [ %niter.nsub.3, %for.body12.us.us ], [ %unroll_iter, %for.cond9.preheader.us.us ] + %add13.us.us = add i32 %filter_x.053.us.us, %res_x.060.us + %arrayidx14.us.us = getelementptr inbounds i16, i16* %tmp5, i32 %filter_x.053.us.us + %tmp9 = load i16, i16* %arrayidx14.us.us, align 2 + %conv.us.us = sext i16 %tmp9 to i32 + %arrayidx16.us.us = getelementptr inbounds i16, i16* %tmp6, i32 %add13.us.us + %tmp10 = load i16, i16* %arrayidx16.us.us, align 2 + %conv17.us.us = sext i16 %tmp10 to i32 + %mul.us.us = mul nsw i32 %conv17.us.us, %conv.us.us + %add18.us.us = add nsw i32 %mul.us.us, %result_element.152.us.us + %inc.us.us = or i32 %filter_x.053.us.us, 1 + %add13.us.us.1 = add i32 %inc.us.us, %res_x.060.us + %arrayidx14.us.us.1 = getelementptr inbounds i16, i16* %tmp5, i32 %inc.us.us + %tmp11 = load i16, i16* %arrayidx14.us.us.1, align 2 + %conv.us.us.1 = sext i16 %tmp11 to i32 + %arrayidx16.us.us.1 = getelementptr inbounds i16, i16* %tmp6, i32 %add13.us.us.1 + %tmp12 = load i16, i16* %arrayidx16.us.us.1, align 2 + %conv17.us.us.1 = sext i16 %tmp12 to i32 + %mul.us.us.1 = mul nsw i32 %conv17.us.us.1, %conv.us.us.1 + %add18.us.us.1 = add nsw i32 %mul.us.us.1, %add18.us.us + %inc.us.us.1 = or i32 %filter_x.053.us.us, 2 + %add13.us.us.2 = add i32 %inc.us.us.1, %res_x.060.us + %arrayidx14.us.us.2 = getelementptr inbounds i16, i16* %tmp5, i32 %inc.us.us.1 + %tmp13 = load i16, i16* %arrayidx14.us.us.2, align 2 + %conv.us.us.2 = sext i16 %tmp13 to i32 + %arrayidx16.us.us.2 = getelementptr inbounds i16, i16* %tmp6, i32 %add13.us.us.2 + %tmp14 = load i16, i16* %arrayidx16.us.us.2, align 2 + %conv17.us.us.2 = sext i16 %tmp14 to i32 + %mul.us.us.2 = mul nsw i32 %conv17.us.us.2, %conv.us.us.2 + %add18.us.us.2 = add nsw i32 %mul.us.us.2, %add18.us.us.1 + %inc.us.us.2 = or i32 %filter_x.053.us.us, 3 + %add13.us.us.3 = add i32 %inc.us.us.2, %res_x.060.us + %arrayidx14.us.us.3 = getelementptr inbounds i16, i16* %tmp5, i32 %inc.us.us.2 + %tmp15 = load i16, i16* %arrayidx14.us.us.3, align 2 + %conv.us.us.3 = sext i16 %tmp15 to i32 + %arrayidx16.us.us.3 = getelementptr inbounds i16, i16* %tmp6, i32 %add13.us.us.3 + %tmp16 = load i16, i16* %arrayidx16.us.us.3, align 2 + %conv17.us.us.3 = sext i16 %tmp16 to i32 + %mul.us.us.3 = mul nsw i32 %conv17.us.us.3, %conv.us.us.3 + %add18.us.us.3 = add nsw i32 %mul.us.us.3, %add18.us.us.2 + %inc.us.us.3 = add i32 %filter_x.053.us.us, 4 + %niter.nsub.3 = add i32 %niter, -4 + %niter.ncmp.3 = icmp eq i32 %niter.nsub.3, 0 + br i1 %niter.ncmp.3, label %for.cond9.for.cond.cleanup11_crit_edge.us.us.unr-lcssa, label %for.body12.us.us + +for.cond9.for.cond.cleanup11_crit_edge.us.us.unr-lcssa: ; preds = %for.body12.us.us, %for.cond9.preheader.us.us + %inc20.us.us = add nuw i32 %filter_y.056.us.us, 1 + %exitcond98 = icmp eq i32 %inc20.us.us, %filter_dim + br i1 %exitcond98, label %for.cond5.for.cond.cleanup7_crit_edge.us, label %for.cond9.preheader.us.us + +for.cond5.for.cond.cleanup7_crit_edge.us: ; preds = %for.cond9.for.cond.cleanup11_crit_edge.us.us + %arrayidx23.us = getelementptr inbounds i32, i32* %tmp3, i32 %res_x.060.us + store i32 %add18.us.us.3, i32* %arrayidx23.us, align 4 + %add25.us = add nuw i32 %res_x.060.us, 1 + %exitcond99 = icmp eq i32 %add25.us, %out_width + br i1 %exitcond99, label %for.cond.cleanup3, label %for.cond9.preheader.us.us.preheader + +for.cond.cleanup3: ; preds = %for.cond5.for.cond.cleanup7_crit_edge.us, %for.cond5.preheader.preheader, %for.cond1.preheader + %add28 = add nuw i32 %res_y.093, 1 + %exitcond100 = icmp eq i32 %add28, %out_height + br i1 %exitcond100, label %for.cond.cleanup, label %for.cond1.preheader + +for.cond.cleanup: ; preds = %for.cond.cleanup3, %entry + ret void +} + +declare i32 @llvm.arm.qadd(i32, i32) +declare i32 @llvm.arm.qadd16(i32, i32) + Index: test/CodeGen/ARM/loop-align-cortex-m.ll =================================================================== --- test/CodeGen/ARM/loop-align-cortex-m.ll +++ test/CodeGen/ARM/loop-align-cortex-m.ll @@ -1,10 +1,10 @@ ; RUN: llc -mtriple=thumbv7m-none-eabi %s -mcpu=cortex-m3 -o - | FileCheck %s ; RUN: llc -mtriple=thumbv7m-none-eabi %s -mcpu=cortex-m4 -o - | FileCheck %s -; RUN: llc -mtriple=thumbv7m-none-eabi %s -mcpu=cortex-m33 -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8m-none-eabi %s -mcpu=cortex-m33 -o - | FileCheck %s define void @test_loop_alignment(i32* %in, i32* %out) optsize { ; CHECK-LABEL: test_loop_alignment: -; CHECK: movs {{r[0-9]+}}, #0 +; CHECK: mov.w {{r[0-9]+}}, #1024 ; CHECK: .p2align 2 entry: @@ -27,7 +27,7 @@ define void @test_loop_alignment_minsize(i32* %in, i32* %out) minsize { ; CHECK-LABEL: test_loop_alignment_minsize: -; CHECK: movs {{r[0-9]+}}, #0 +; CHECK: mov.w {{r[0-9]+}}, #1024 ; CHECK-NOT: .p2align entry: Index: test/CodeGen/ARM/t2-shrink-ldrpost.ll =================================================================== --- test/CodeGen/ARM/t2-shrink-ldrpost.ll +++ test/CodeGen/ARM/t2-shrink-ldrpost.ll @@ -4,9 +4,8 @@ target triple = "thumbv7m--linux-gnu" ; CHECK-LABEL: f: -; CHECK: ldm r{{[0-9]}}!, {r[[x:[0-9]]]} -; CHECK: add.w r[[x]], r[[x]], #3 -; CHECK: stm r{{[0-9]}}!, {r[[x]]} +; CHECK: ldr{{.*}}, [{{.*}}, #4]! +; CHECK: str{{.*}}, [{{.*}}, #4]! define void @f(i32 %n, i32* nocapture %a, i32* nocapture readonly %b) optsize minsize { %1 = icmp sgt i32 %n, 0 br i1 %1, label %.lr.ph, label %._crit_edge @@ -29,7 +28,8 @@ } ; CHECK-LABEL: f_nominsize: -; CHECK-NOT: ldm +; CHECK: ldr{{.*}}, [{{.*}}, #4]! +; CHECK: str{{.*}}, [{{.*}}, #4]! define void @f_nominsize(i32 %n, i32* nocapture %a, i32* nocapture readonly %b) optsize { %1 = icmp sgt i32 %n, 0 br i1 %1, label %.lr.ph, label %._crit_edge Index: test/Transforms/LoopStrengthReduce/ARM/complexity.ll =================================================================== --- test/Transforms/LoopStrengthReduce/ARM/complexity.ll +++ test/Transforms/LoopStrengthReduce/ARM/complexity.ll @@ -1,21 +1,27 @@ target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" -; RUN: opt -mtriple=thumbv7em %s -S -loop-reduce -lsr-complexity-limit=65536 -o - | FileCheck %s --check-prefix=CHECK-DEFAULT -; RUN: opt -mtriple=thumbv7em %s -S -loop-reduce -lsr-complexity-limit=2147483647 -o - | FileCheck %s --check-prefix=CHECK-COMPLEX +; RUN: opt -mtriple=thumbv7em %s -S -loop-reduce -lsr-complexity-limit=65536 -o - | FileCheck %s +; RUN: opt -mtriple=thumbv7em %s -S -loop-reduce -lsr-complexity-limit=2147483647 -o - | FileCheck %s -; CHECK-DEFAULT-LABEL: for.body12.us.us: -; CHECK-DEFAULT: phi i32 -; CHECK-DEFAULT: [[LSR_IV:%[^ ]+]] = phi i32 [ [[LSR_IV_NEXT:%[^ ]+]], %for.body12.us.us ], [ 0, %for.cond9.preheader.us.us ] -; CHECK-DEFAULT: phi i32 -; CHECK-DEFAULT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 8 +; CHECK-LABEL: for.cond9.preheader.us.us: +; CHECK: [[SCEVGEP:%[^ ]+]] = getelementptr i16, i16* %tmp5, i32 -4 +; CHECK: [[SCEVGEP9:%[^ ]+]] = getelementptr i16, i16* %tmp6, i32 %lsr.iv7 -; CHECK-COMPLEX-LABEL: for.body12.us.us: -; CHECK-COMPLEX: phi i32 -; CHECK-COMPLEX: [[LSR_IV6:%[^ ]+]] = phi i16* [ [[SCEVGEP7:%[^ ]+]], %for.body12.us.us ], [ [[SCEVGEP5:%[^ ]+]], %for.cond9.preheader.us.us ] -; CHECK-COMPLEX: [[LSR_IV:%[^ ]+]] = phi i16* [ [[SCEVGEP1:%[^ ]+]], %for.body12.us.us ], [ [[SCEVGEP:%[^ ]+]], %for.cond9.preheader.us.us ] -; CHECK-COMPLEX: phi i32 -; CHECK-COMPLEX: [[SCEVGEP1]] = getelementptr i16, i16* [[LSR_IV]], i32 4 -; CHECK-COMPLEX: [[SCEVGEP7]] = getelementptr i16, i16* [[LSR_IV6]], i32 4 +; CHECK-DEFAULT-LABEL: for.body12.us.us: +; CHECK: [[LSR_IV10:%[^ ]+]] = phi i16* [ [[SCEVGEP11:%[^ ]+]], %for.body12.us.us ], [ [[SCEVGEP9]], %for.cond9.preheader.us.us ] +; CHECK: phi i32 +; CHECK: [[LSR_IV:%[^ ]+]] = phi i16* [ [[SCEVGEP1:%[^ ]+]], %for.body12.us.us ], [ [[SCEVGEP]], %for.cond9.preheader.us.us ] +; CHECK: phi i32 +; CHECK: getelementptr i16, i16* [[LSR_IV]], i32 4 +; CHECK: getelementptr i16, i16* [[LSR_IV10]], i32 4 +; CHECK: getelementptr i16, i16* [[LSR_IV]], i32 5 +; CHECK: getelementptr i16, i16* [[LSR_IV10]], i32 5 +; CHECK: getelementptr i16, i16* [[LSR_IV]], i32 6 +; CHECK: getelementptr i16, i16* [[LSR_IV10]], i32 6 +; CHECK: getelementptr i16, i16* [[LSR_IV]], i32 7 +; CHECK: getelementptr i16, i16* [[LSR_IV10]], i32 7 +; CHECK: [[SCEVGEP1]] = getelementptr i16, i16* [[LSR_IV]], i32 4 +; CHECK: [[SCEVGEP11]] = getelementptr i16, i16* [[LSR_IV10]], i32 4 define void @convolve(i16** nocapture readonly %input_image, i16** nocapture readonly %filter, i32 %filter_dim, i32 %out_width, i32 %out_height, i32** nocapture readonly %convolved) { entry: