Index: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp =================================================================== --- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -578,7 +578,9 @@ MI.eraseFromParent(); return Legalized; } - case TargetOpcode::G_OR: { + case TargetOpcode::G_AND: + case TargetOpcode::G_OR: + case TargetOpcode::G_XOR: { // Legalize bitwise operation: // A = BinOp B, C // into: @@ -617,7 +619,8 @@ // Do the operation on each small part. for (int i = 0; i < NumParts; ++i) - MIRBuilder.buildOr(DstRegs[i], SrcsReg1[i], SrcsReg2[i]); + MIRBuilder.buildInstr(MI.getOpcode(), {DstRegs[i]}, + {SrcsReg1[i], SrcsReg2[i]}); // Gather the destination registers into the final destination. unsigned DstReg = MI.getOperand(0).getReg(); Index: llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp +++ llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp @@ -34,7 +34,11 @@ getActionDefinitionsBuilder({G_LOAD, G_STORE}) .legalForCartesianProduct({p0, s32}, {p0}); - getActionDefinitionsBuilder({G_AND, G_OR, G_XOR, G_SHL, G_ASHR, G_LSHR}) + getActionDefinitionsBuilder({G_AND, G_OR, G_XOR}) + .legalFor({s32}) + .clampScalar(0, s32, s32); + + getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR}) .legalFor({s32}); getActionDefinitionsBuilder(G_ICMP) Index: llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir =================================================================== --- llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir +++ llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/bitwise.mir @@ -2,9 +2,9 @@ # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 --- | - define void @and(i32, i32) {entry: ret void} - define void @or(i32, i32) {entry: ret void} - define void @xor(i32, i32) {entry: ret void} + define void @and_i32() {entry: ret void} + define void @or_i32() {entry: ret void} + define void @xor_i32() {entry: ret void} define void @shl(i32) {entry: ret void} define void @ashr(i32) {entry: ret void} define void @lshr(i32) {entry: ret void} @@ -14,7 +14,7 @@ ... --- -name: and +name: and_i32 alignment: 2 legalized: true regBankSelected: true @@ -23,7 +23,7 @@ bb.1.entry: liveins: $a0, $a1 - ; MIPS32-LABEL: name: and + ; MIPS32-LABEL: name: and_i32 ; MIPS32: liveins: $a0, $a1 ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 @@ -38,7 +38,7 @@ ... --- -name: or +name: or_i32 alignment: 2 legalized: true regBankSelected: true @@ -47,7 +47,7 @@ bb.1.entry: liveins: $a0, $a1 - ; MIPS32-LABEL: name: or + ; MIPS32-LABEL: name: or_i32 ; MIPS32: liveins: $a0, $a1 ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 @@ -62,7 +62,7 @@ ... --- -name: xor +name: xor_i32 alignment: 2 legalized: true regBankSelected: true @@ -71,7 +71,7 @@ bb.1.entry: liveins: $a0, $a1 - ; MIPS32-LABEL: name: xor + ; MIPS32-LABEL: name: xor_i32 ; MIPS32: liveins: $a0, $a1 ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0 ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1 Index: llvm/trunk/test/CodeGen/Mips/GlobalISel/irtranslator/bitwise.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/GlobalISel/irtranslator/bitwise.ll +++ llvm/trunk/test/CodeGen/Mips/GlobalISel/irtranslator/bitwise.ll @@ -1,48 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 -define i32 @and(i32 %a, i32 %b) { - ; MIPS32-LABEL: name: and - ; MIPS32: bb.1.entry: - ; MIPS32: liveins: $a0, $a1 - ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 - ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 - ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]] - ; MIPS32: $v0 = COPY [[AND]](s32) - ; MIPS32: RetRA implicit $v0 -entry: - %and = and i32 %b, %a - ret i32 %and -} - -define i32 @or(i32 %a, i32 %b) { - ; MIPS32-LABEL: name: or - ; MIPS32: bb.1.entry: - ; MIPS32: liveins: $a0, $a1 - ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 - ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 - ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]] - ; MIPS32: $v0 = COPY [[OR]](s32) - ; MIPS32: RetRA implicit $v0 -entry: - %or = or i32 %b, %a - ret i32 %or -} - -define i32 @xor(i32 %a, i32 %b) { - ; MIPS32-LABEL: name: xor - ; MIPS32: bb.1.entry: - ; MIPS32: liveins: $a0, $a1 - ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 - ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 - ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]] - ; MIPS32: $v0 = COPY [[XOR]](s32) - ; MIPS32: RetRA implicit $v0 -entry: - %xor = xor i32 %b, %a - ret i32 %xor -} - define i32 @shl(i32 %a) { ; MIPS32-LABEL: name: shl ; MIPS32: bb.1.entry: Index: llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir =================================================================== --- llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir +++ llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir @@ -2,9 +2,21 @@ # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32 --- | - define void @and(i32, i32) {entry: ret void} - define void @or(i32, i32) {entry: ret void} - define void @xor(i32, i32) {entry: ret void} + define void @and_i1() {entry: ret void} + define void @and_i8() {entry: ret void} + define void @and_i16() {entry: ret void} + define void @and_i32() {entry: ret void} + define void @and_i64() {entry: ret void} + define void @or_i1() {entry: ret void} + define void @or_i8() {entry: ret void} + define void @or_i16() {entry: ret void} + define void @or_i32() {entry: ret void} + define void @or_i64() {entry: ret void} + define void @xor_i1() {entry: ret void} + define void @xor_i8() {entry: ret void} + define void @xor_i16() {entry: ret void} + define void @xor_i32() {entry: ret void} + define void @xor_i64() {entry: ret void} define void @shl(i32) {entry: ret void} define void @ashr(i32) {entry: ret void} define void @lshr(i32) {entry: ret void} @@ -14,14 +26,98 @@ ... --- -name: and +name: and_i1 alignment: 2 tracksRegLiveness: true body: | bb.1.entry: liveins: $a0, $a1 - ; MIPS32-LABEL: name: and + ; MIPS32-LABEL: name: and_i1 + ; MIPS32: liveins: $a0, $a1 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]] + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32) + ; MIPS32: $v0 = COPY [[COPY4]](s32) + ; MIPS32: RetRA implicit $v0 + %2:_(s32) = COPY $a0 + %0:_(s1) = G_TRUNC %2(s32) + %3:_(s32) = COPY $a1 + %1:_(s1) = G_TRUNC %3(s32) + %4:_(s1) = G_AND %1, %0 + %5:_(s32) = G_ANYEXT %4(s1) + $v0 = COPY %5(s32) + RetRA implicit $v0 + +... +--- +name: and_i8 +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1 + + ; MIPS32-LABEL: name: and_i8 + ; MIPS32: liveins: $a0, $a1 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]] + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32) + ; MIPS32: $v0 = COPY [[COPY4]](s32) + ; MIPS32: RetRA implicit $v0 + %2:_(s32) = COPY $a0 + %0:_(s8) = G_TRUNC %2(s32) + %3:_(s32) = COPY $a1 + %1:_(s8) = G_TRUNC %3(s32) + %4:_(s8) = G_AND %1, %0 + %5:_(s32) = G_ANYEXT %4(s8) + $v0 = COPY %5(s32) + RetRA implicit $v0 + +... +--- +name: and_i16 +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1 + + ; MIPS32-LABEL: name: and_i16 + ; MIPS32: liveins: $a0, $a1 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]] + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32) + ; MIPS32: $v0 = COPY [[COPY4]](s32) + ; MIPS32: RetRA implicit $v0 + %2:_(s32) = COPY $a0 + %0:_(s16) = G_TRUNC %2(s32) + %3:_(s32) = COPY $a1 + %1:_(s16) = G_TRUNC %3(s32) + %4:_(s16) = G_AND %1, %0 + %5:_(s32) = G_ANYEXT %4(s16) + $v0 = COPY %5(s32) + RetRA implicit $v0 + +... +--- +name: and_i32 +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1 + + ; MIPS32-LABEL: name: and_i32 ; MIPS32: liveins: $a0, $a1 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 @@ -36,14 +132,130 @@ ... --- -name: or +name: and_i64 +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1, $a2, $a3 + + ; MIPS32-LABEL: name: and_i64 + ; MIPS32: liveins: $a0, $a1, $a2, $a3 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 + ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY]] + ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[COPY1]] + ; MIPS32: $v0 = COPY [[AND]](s32) + ; MIPS32: $v1 = COPY [[AND1]](s32) + ; MIPS32: RetRA implicit $v0, implicit $v1 + %2:_(s32) = COPY $a0 + %3:_(s32) = COPY $a1 + %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %4:_(s32) = COPY $a2 + %5:_(s32) = COPY $a3 + %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32) + %6:_(s64) = G_AND %1, %0 + %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64) + $v0 = COPY %7(s32) + $v1 = COPY %8(s32) + RetRA implicit $v0, implicit $v1 + +... +--- +name: or_i1 +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1 + + ; MIPS32-LABEL: name: or_i1 + ; MIPS32: liveins: $a0, $a1 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]] + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR]](s32) + ; MIPS32: $v0 = COPY [[COPY4]](s32) + ; MIPS32: RetRA implicit $v0 + %2:_(s32) = COPY $a0 + %0:_(s1) = G_TRUNC %2(s32) + %3:_(s32) = COPY $a1 + %1:_(s1) = G_TRUNC %3(s32) + %4:_(s1) = G_OR %1, %0 + %5:_(s32) = G_ANYEXT %4(s1) + $v0 = COPY %5(s32) + RetRA implicit $v0 + +... +--- +name: or_i8 alignment: 2 tracksRegLiveness: true body: | bb.1.entry: liveins: $a0, $a1 - ; MIPS32-LABEL: name: or + ; MIPS32-LABEL: name: or_i8 + ; MIPS32: liveins: $a0, $a1 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]] + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR]](s32) + ; MIPS32: $v0 = COPY [[COPY4]](s32) + ; MIPS32: RetRA implicit $v0 + %2:_(s32) = COPY $a0 + %0:_(s8) = G_TRUNC %2(s32) + %3:_(s32) = COPY $a1 + %1:_(s8) = G_TRUNC %3(s32) + %4:_(s8) = G_OR %1, %0 + %5:_(s32) = G_ANYEXT %4(s8) + $v0 = COPY %5(s32) + RetRA implicit $v0 + +... +--- +name: or_i16 +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1 + + ; MIPS32-LABEL: name: or_i16 + ; MIPS32: liveins: $a0, $a1 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]] + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR]](s32) + ; MIPS32: $v0 = COPY [[COPY4]](s32) + ; MIPS32: RetRA implicit $v0 + %2:_(s32) = COPY $a0 + %0:_(s16) = G_TRUNC %2(s32) + %3:_(s32) = COPY $a1 + %1:_(s16) = G_TRUNC %3(s32) + %4:_(s16) = G_OR %1, %0 + %5:_(s32) = G_ANYEXT %4(s16) + $v0 = COPY %5(s32) + RetRA implicit $v0 + +... +--- +name: or_i32 +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1 + + ; MIPS32-LABEL: name: or_i32 ; MIPS32: liveins: $a0, $a1 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 @@ -58,14 +270,130 @@ ... --- -name: xor +name: or_i64 +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1, $a2, $a3 + + ; MIPS32-LABEL: name: or_i64 + ; MIPS32: liveins: $a0, $a1, $a2, $a3 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 + ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY]] + ; MIPS32: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY3]], [[COPY1]] + ; MIPS32: $v0 = COPY [[OR]](s32) + ; MIPS32: $v1 = COPY [[OR1]](s32) + ; MIPS32: RetRA implicit $v0, implicit $v1 + %2:_(s32) = COPY $a0 + %3:_(s32) = COPY $a1 + %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %4:_(s32) = COPY $a2 + %5:_(s32) = COPY $a3 + %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32) + %6:_(s64) = G_OR %1, %0 + %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64) + $v0 = COPY %7(s32) + $v1 = COPY %8(s32) + RetRA implicit $v0, implicit $v1 + +... +--- +name: xor_i1 +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1 + + ; MIPS32-LABEL: name: xor_i1 + ; MIPS32: liveins: $a0, $a1 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY3]] + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[XOR]](s32) + ; MIPS32: $v0 = COPY [[COPY4]](s32) + ; MIPS32: RetRA implicit $v0 + %2:_(s32) = COPY $a0 + %0:_(s1) = G_TRUNC %2(s32) + %3:_(s32) = COPY $a1 + %1:_(s1) = G_TRUNC %3(s32) + %4:_(s1) = G_XOR %1, %0 + %5:_(s32) = G_ANYEXT %4(s1) + $v0 = COPY %5(s32) + RetRA implicit $v0 + +... +--- +name: xor_i8 alignment: 2 tracksRegLiveness: true body: | bb.1.entry: liveins: $a0, $a1 - ; MIPS32-LABEL: name: xor + ; MIPS32-LABEL: name: xor_i8 + ; MIPS32: liveins: $a0, $a1 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY3]] + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[XOR]](s32) + ; MIPS32: $v0 = COPY [[COPY4]](s32) + ; MIPS32: RetRA implicit $v0 + %2:_(s32) = COPY $a0 + %0:_(s8) = G_TRUNC %2(s32) + %3:_(s32) = COPY $a1 + %1:_(s8) = G_TRUNC %3(s32) + %4:_(s8) = G_XOR %1, %0 + %5:_(s32) = G_ANYEXT %4(s8) + $v0 = COPY %5(s32) + RetRA implicit $v0 + +... +--- +name: xor_i16 +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1 + + ; MIPS32-LABEL: name: xor_i16 + ; MIPS32: liveins: $a0, $a1 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY3]] + ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[XOR]](s32) + ; MIPS32: $v0 = COPY [[COPY4]](s32) + ; MIPS32: RetRA implicit $v0 + %2:_(s32) = COPY $a0 + %0:_(s16) = G_TRUNC %2(s32) + %3:_(s32) = COPY $a1 + %1:_(s16) = G_TRUNC %3(s32) + %4:_(s16) = G_XOR %1, %0 + %5:_(s32) = G_ANYEXT %4(s16) + $v0 = COPY %5(s32) + RetRA implicit $v0 + +... +--- +name: xor_i32 +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1 + + ; MIPS32-LABEL: name: xor_i32 ; MIPS32: liveins: $a0, $a1 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 @@ -80,6 +408,38 @@ ... --- +name: xor_i64 +alignment: 2 +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $a0, $a1, $a2, $a3 + + ; MIPS32-LABEL: name: xor_i64 + ; MIPS32: liveins: $a0, $a1, $a2, $a3 + ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0 + ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1 + ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 + ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 + ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY]] + ; MIPS32: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY3]], [[COPY1]] + ; MIPS32: $v0 = COPY [[XOR]](s32) + ; MIPS32: $v1 = COPY [[XOR1]](s32) + ; MIPS32: RetRA implicit $v0, implicit $v1 + %2:_(s32) = COPY $a0 + %3:_(s32) = COPY $a1 + %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32) + %4:_(s32) = COPY $a2 + %5:_(s32) = COPY $a3 + %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32) + %6:_(s64) = G_XOR %1, %0 + %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64) + $v0 = COPY %7(s32) + $v1 = COPY %8(s32) + RetRA implicit $v0, implicit $v1 + +... +--- name: shl alignment: 2 tracksRegLiveness: true Index: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll +++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll @@ -1,9 +1,41 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py - ; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32 -define i32 @and(i32 %a, i32 %b) { -; MIPS32-LABEL: and: +define i1 @and_i1(i1 %a, i1 %b) { +; MIPS32-LABEL: and_i1: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: and $2, $5, $4 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %and = and i1 %b, %a + ret i1 %and +} + +define i8 @and_i8(i8 %a, i8 %b) { +; MIPS32-LABEL: and_i8: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: and $2, $5, $4 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %and = and i8 %b, %a + ret i8 %and +} + +define i16 @and_i16(i16 %a, i16 %b) { +; MIPS32-LABEL: and_i16: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: and $2, $5, $4 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %and = and i16 %b, %a + ret i16 %and +} + +define i32 @and_i32(i32 %a, i32 %b) { +; MIPS32-LABEL: and_i32: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: and $2, $5, $4 ; MIPS32-NEXT: jr $ra @@ -13,8 +45,53 @@ ret i32 %and } -define i32 @or(i32 %a, i32 %b) { -; MIPS32-LABEL: or: +define i64 @and_i64(i64 %a, i64 %b) { +; MIPS32-LABEL: and_i64: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: and $2, $6, $4 +; MIPS32-NEXT: and $3, $7, $5 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %and = and i64 %b, %a + ret i64 %and +} + +define i1 @or_i1(i1 %a, i1 %b) { +; MIPS32-LABEL: or_i1: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: or $2, $5, $4 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %or = or i1 %b, %a + ret i1 %or +} + +define i8 @or_i8(i8 %a, i8 %b) { +; MIPS32-LABEL: or_i8: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: or $2, $5, $4 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %or = or i8 %b, %a + ret i8 %or +} + +define i16 @or_i16(i16 %a, i16 %b) { +; MIPS32-LABEL: or_i16: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: or $2, $5, $4 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %or = or i16 %b, %a + ret i16 %or +} + +define i32 @or_i32(i32 %a, i32 %b) { +; MIPS32-LABEL: or_i32: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: or $2, $5, $4 ; MIPS32-NEXT: jr $ra @@ -24,8 +101,53 @@ ret i32 %or } -define i32 @xor(i32 %a, i32 %b) { -; MIPS32-LABEL: xor: +define i64 @or_i64(i64 %a, i64 %b) { +; MIPS32-LABEL: or_i64: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: or $2, $6, $4 +; MIPS32-NEXT: or $3, $7, $5 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %or = or i64 %b, %a + ret i64 %or +} + +define i1 @xor_i1(i1 %a, i1 %b) { +; MIPS32-LABEL: xor_i1: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: xor $2, $5, $4 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %xor = xor i1 %b, %a + ret i1 %xor +} + +define i8 @xor_i8(i8 %a, i8 %b) { +; MIPS32-LABEL: xor_i8: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: xor $2, $5, $4 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %xor = xor i8 %b, %a + ret i8 %xor +} + +define i16 @xor_i16(i16 %a, i16 %b) { +; MIPS32-LABEL: xor_i16: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: xor $2, $5, $4 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %xor = xor i16 %b, %a + ret i16 %xor +} + +define i32 @xor_i32(i32 %a, i32 %b) { +; MIPS32-LABEL: xor_i32: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: xor $2, $5, $4 ; MIPS32-NEXT: jr $ra @@ -35,6 +157,18 @@ ret i32 %xor } +define i64 @xor_i64(i64 %a, i64 %b) { +; MIPS32-LABEL: xor_i64: +; MIPS32: # %bb.0: # %entry +; MIPS32-NEXT: xor $2, $6, $4 +; MIPS32-NEXT: xor $3, $7, $5 +; MIPS32-NEXT: jr $ra +; MIPS32-NEXT: nop +entry: + %xor = xor i64 %b, %a + ret i64 %xor +} + define i32 @shl(i32 %a) { ; MIPS32-LABEL: shl: ; MIPS32: # %bb.0: # %entry Index: llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir =================================================================== --- llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir +++ llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/bitwise.mir @@ -3,9 +3,9 @@ --- | - define void @and(i32, i32) {entry: ret void} - define void @or(i32, i32) {entry: ret void} - define void @xor(i32, i32) {entry: ret void} + define void @and_i32() {entry: ret void} + define void @or_i32() {entry: ret void} + define void @xor_i32() {entry: ret void} define void @shl(i32) {entry: ret void} define void @ashr(i32) {entry: ret void} define void @lshr(i32) {entry: ret void} @@ -15,7 +15,7 @@ ... --- -name: and +name: and_i32 alignment: 2 legalized: true tracksRegLiveness: true @@ -23,7 +23,7 @@ bb.1.entry: liveins: $a0, $a1 - ; MIPS32-LABEL: name: and + ; MIPS32-LABEL: name: and_i32 ; MIPS32: liveins: $a0, $a1 ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1 @@ -38,7 +38,7 @@ ... --- -name: or +name: or_i32 alignment: 2 legalized: true tracksRegLiveness: true @@ -46,7 +46,7 @@ bb.1.entry: liveins: $a0, $a1 - ; MIPS32-LABEL: name: or + ; MIPS32-LABEL: name: or_i32 ; MIPS32: liveins: $a0, $a1 ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1 @@ -61,7 +61,7 @@ ... --- -name: xor +name: xor_i32 alignment: 2 legalized: true tracksRegLiveness: true @@ -69,7 +69,7 @@ bb.1.entry: liveins: $a0, $a1 - ; MIPS32-LABEL: name: xor + ; MIPS32-LABEL: name: xor_i32 ; MIPS32: liveins: $a0, $a1 ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0 ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $a1