Index: lib/Target/Hexagon/CMakeLists.txt =================================================================== --- lib/Target/Hexagon/CMakeLists.txt +++ lib/Target/Hexagon/CMakeLists.txt @@ -2,6 +2,7 @@ tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info) tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info) +tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter) tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer) tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel) tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv) Index: lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt =================================================================== --- lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt +++ lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt @@ -1,5 +1,8 @@ add_llvm_library(LLVMHexagonDesc HexagonMCAsmInfo.cpp + HexagonMCCodeEmitter.cpp HexagonMCInst.cpp HexagonMCTargetDesc.cpp ) + +add_dependencies(LLVMHexagonDesc HexagonCommonTableGen) \ No newline at end of file Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h +++ lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h @@ -0,0 +1,60 @@ +//===-- HexagonMCCodeEmitter.h - Hexagon Target Descriptions ----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// \brief Definition for classes that emit Hexagon machine code from MCInsts +/// +//===----------------------------------------------------------------------===// + +#ifndef HEXAGONMCCODEEMITTER_H +#define HEXAGONMCCODEEMITTER_H + +#include "llvm/MC/MCCodeEmitter.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/raw_ostream.h" + +namespace llvm { + +class HexagonMCCodeEmitter : public MCCodeEmitter { + MCSubtargetInfo const &MST; + MCContext &MCT; + +public: + HexagonMCCodeEmitter(MCInstrInfo const &aMII, MCSubtargetInfo const &aMST, + MCContext &aMCT); + + MCSubtargetInfo const &getSubtargetInfo() const; + + void EncodeInstruction(MCInst const &MI, raw_ostream &OS, + SmallVectorImpl &Fixups, + MCSubtargetInfo const &STI) const override; + + // getBinaryCodeForInstr - TableGen'erated function for getting the + // binary encoding for an instruction. + uint64_t getBinaryCodeForInstr(MCInst const &MI, + SmallVectorImpl &Fixups, + MCSubtargetInfo const &STI) const; + + /// \brief Return binary encoding of operand. + unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO, + SmallVectorImpl &Fixups, + MCSubtargetInfo const &STI) const; + +private: + HexagonMCCodeEmitter(HexagonMCCodeEmitter const &) = delete; + void operator=(HexagonMCCodeEmitter const &) = delete; +}; // class HexagonMCCodeEmitter + +} // namespace llvm + +#endif /* HEXAGONMCCODEEMITTER_H */ Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp +++ lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp @@ -0,0 +1,88 @@ +//===-- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions ------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "Hexagon.h" +#include "MCTargetDesc/HexagonBaseInfo.h" +#include "MCTargetDesc/HexagonMCCodeEmitter.h" +#include "MCTargetDesc/HexagonMCTargetDesc.h" +#include "MCTargetDesc/HexagonMCInst.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/MC/MCCodeEmitter.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" + +#define DEBUG_TYPE "mccodeemitter" + +using namespace llvm; +using namespace Hexagon; + +STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); + +namespace { +/// \brief 10.6 Instruction Packets +/// \brief Possible values for instruction packet parse field. +enum class ParseField { duplex = 0x0, last0 = 0x1, last1 = 0x2, end = 0x3 }; +/// \brief Returns the packet bits based on instruction position. +uint32_t getPacketBits(HexagonMCInst const &HMI) { + unsigned const ParseFieldOffset = 14; + ParseField Field = HMI.isPacketEnd() ? ParseField::end : ParseField::last0; + return static_cast (Field) << ParseFieldOffset; +} +void emitLittleEndian(uint64_t Binary, raw_ostream &OS) { + OS << static_cast((Binary >> 0x00) & 0xff); + OS << static_cast((Binary >> 0x08) & 0xff); + OS << static_cast((Binary >> 0x10) & 0xff); + OS << static_cast((Binary >> 0x18) & 0xff); +} +} + +HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII, + MCSubtargetInfo const &aMST, + MCContext &aMCT) + : MST(aMST), MCT(aMCT) {} + +void HexagonMCCodeEmitter::EncodeInstruction(MCInst const &MI, raw_ostream &OS, + SmallVectorImpl &Fixups, + MCSubtargetInfo const &STI) const { + HexagonMCInst const &HMB = static_cast(MI); + uint64_t Binary = getBinaryCodeForInstr(HMB, Fixups, STI) | getPacketBits(HMB); + assert(HMB.getDesc().getSize() == 4 && "All instructions should be 32bit"); + emitLittleEndian(Binary, OS); + ++MCNumEmitted; +} + +unsigned +HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO, + SmallVectorImpl &Fixups, + MCSubtargetInfo const &STI) const { + if (MO.isReg()) + return MCT.getRegisterInfo()->getEncodingValue(MO.getReg()); + if (MO.isImm()) + return static_cast(MO.getImm()); + llvm_unreachable("Only Immediates and Registers implemented right now"); +} + +MCSubtargetInfo const &HexagonMCCodeEmitter::getSubtargetInfo() const { + return MST; +} + +MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII, + MCRegisterInfo const &MRI, + MCSubtargetInfo const &MST, + MCContext &MCT) { + return new HexagonMCCodeEmitter(MII, MST, MCT); +} + +#include "HexagonGenMCCodeEmitter.inc" Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h +++ lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h @@ -15,11 +15,20 @@ #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H namespace llvm { +class MCCodeEmitter; +class MCContext; +class MCInstrInfo; +class MCRegisterInfo; class MCSubtargetInfo; class Target; extern Target TheHexagonTarget; +MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII, + const MCRegisterInfo &MRI, + const MCSubtargetInfo &MST, + MCContext &MCT); + } // End llvm namespace // Define symbolic names for Hexagon registers. This defines a mapping from Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -46,9 +46,8 @@ return X; } -static MCSubtargetInfo *createHexagonMCSubtargetInfo(StringRef TT, - StringRef CPU, - StringRef FS) { +static MCSubtargetInfo * +createHexagonMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); InitHexagonMCSubtargetInfo(X, TT, CPU, FS); return X; @@ -59,8 +58,8 @@ MCAsmInfo *MAI = new HexagonMCAsmInfo(TT); // VirtualFP = (R30 + #0). - MCCFIInstruction Inst = MCCFIInstruction::createDefCfa( - nullptr, Hexagon::R30, 0); + MCCFIInstruction Inst = + MCCFIInstruction::createDefCfa(nullptr, Hexagon::R30, 0); MAI->addInitialFrameState(Inst); return MAI; @@ -67,8 +66,8 @@ } static MCCodeGenInfo *createHexagonMCCodeGenInfo(StringRef TT, Reloc::Model RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) { + CodeModel::Model CM, + CodeGenOpt::Level OL) { MCCodeGenInfo *X = new MCCodeGenInfo(); // For the time being, use static relocations, since there's really no // support for PIC yet. @@ -86,7 +85,8 @@ createHexagonMCCodeGenInfo); // Register the MC instruction info. - TargetRegistry::RegisterMCInstrInfo(TheHexagonTarget, createHexagonMCInstrInfo); + TargetRegistry::RegisterMCInstrInfo(TheHexagonTarget, + createHexagonMCInstrInfo); // Register the MC register info. TargetRegistry::RegisterMCRegInfo(TheHexagonTarget, @@ -95,4 +95,8 @@ // Register the MC subtarget info. TargetRegistry::RegisterMCSubtargetInfo(TheHexagonTarget, createHexagonMCSubtargetInfo); + + // Register the MC Code Emitter + TargetRegistry::RegisterMCCodeEmitter(TheHexagonTarget, + createHexagonMCCodeEmitter); } Index: unittests/MC/CMakeLists.txt =================================================================== --- unittests/MC/CMakeLists.txt +++ unittests/MC/CMakeLists.txt @@ -7,3 +7,9 @@ StringTableBuilderTest.cpp YAMLTest.cpp ) + +foreach(t ${LLVM_TARGETS_TO_BUILD}) + if (IS_DIRECTORY "${CMAKE_CURRENT_LIST_DIR}/${t}") + add_subdirectory(${t}) + endif (IS_DIRECTORY "${CMAKE_CURRENT_LIST_DIR}/${t}") +endforeach() Index: unittests/MC/Hexagon/CMakeLists.txt =================================================================== --- unittests/MC/Hexagon/CMakeLists.txt +++ unittests/MC/Hexagon/CMakeLists.txt @@ -0,0 +1,10 @@ +set(LLVM_LINK_COMPONENTS + HexagonCodeGen + ) + +include_directories (${LLVM_MAIN_SRC_DIR}/lib/Target/Hexagon) +include_directories (${LLVM_BINARY_DIR}/lib/Target/Hexagon) + +add_llvm_unittest(HexagonTests + HexagonMCCodeEmitterTest.cpp + ) Index: unittests/MC/Hexagon/HexagonMCCodeEmitterTest.cpp =================================================================== --- unittests/MC/Hexagon/HexagonMCCodeEmitterTest.cpp +++ unittests/MC/Hexagon/HexagonMCCodeEmitterTest.cpp @@ -0,0 +1,53 @@ +#include "gtest/gtest.h" + +#include + +#include "llvm/MC/MCCodeEmitter.h" +#include "llvm/MC/MCContext.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/TargetSelect.h" + +#include "MCTargetDesc/HexagonMCInst.h" +#include "MCTargetDesc/HexagonMCTargetDesc.h" + +namespace { +class TestEmitter { +public: + TestEmitter() : Triple("hexagon-unknown-elf") { + LLVMInitializeHexagonTargetInfo(); + LLVMInitializeHexagonTarget(); + LLVMInitializeHexagonTargetMC(); + std::string error; + Target = llvm::TargetRegistry::lookupTarget("hexagon", error); + assert(Target != nullptr && "Expected to find target"); + assert(error.empty() && "Error should be empty if we have a target"); + RegisterInfo = Target->createMCRegInfo(Triple); + assert(RegisterInfo != nullptr && "Expecting to find register info"); + AsmInfo = Target->createMCAsmInfo(*RegisterInfo, Triple); + assert(AsmInfo != nullptr && "Expecting to find asm info"); + Context = new llvm::MCContext(AsmInfo, RegisterInfo, nullptr); + assert(Context != nullptr && "Expecting to create a context"); + Subtarget = Target->createMCSubtargetInfo(Triple, "hexagonv4", ""); + assert(Subtarget != nullptr && "Expecting to find a subtarget"); + InstrInfo = Target->createMCInstrInfo(); + assert(InstrInfo != nullptr && "Expecting to find instr info"); + Emitter = Target->createMCCodeEmitter(*InstrInfo, *RegisterInfo, *Subtarget, + *Context); + assert(Emitter != nullptr); + } + std::string Triple; + llvm::Target const *Target; + llvm::MCRegisterInfo *RegisterInfo; + llvm::MCAsmInfo *AsmInfo; + llvm::MCContext *Context; + llvm::MCSubtargetInfo *Subtarget; + llvm::MCInstrInfo *InstrInfo; + llvm::MCCodeEmitter *Emitter; +}; +TestEmitter Emitter; +} + +TEST(HexagonMCCodeEmitter, emitter_creation) { + ASSERT_NE(nullptr, Emitter.Emitter); +}