Index: lib/Basic/Targets/PPC.h
===================================================================
--- lib/Basic/Targets/PPC.h
+++ lib/Basic/Targets/PPC.h
@@ -176,6 +176,8 @@
 
   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
 
+  ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
+
   bool validateAsmConstraint(const char *&Name,
                              TargetInfo::ConstraintInfo &Info) const override {
     switch (*Name) {
Index: lib/Basic/Targets/PPC.cpp
===================================================================
--- lib/Basic/Targets/PPC.cpp
+++ lib/Basic/Targets/PPC.cpp
@@ -412,6 +412,36 @@
   return llvm::makeArrayRef(GCCRegAliases);
 }
 
+// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
+// vs0 ~ vs31 is mapping to 32 - 63,
+// vs32 ~ vs63 is mapping to 77 - 108. 
+const TargetInfo::AddlRegName GCCAddlRegNames[] = {
+    // Table of additional register names to use in user input.
+    {{"vs0"}, 32},   {{"vs1"}, 33},   {{"vs2"}, 34},   {{"vs3"}, 35}, 
+    {{"vs4"}, 36},   {{"vs5"}, 37},   {{"vs6"}, 38},   {{"vs7"}, 39},
+    {{"vs8"}, 40},   {{"vs9"}, 41},   {{"vs10"}, 42},  {{"vs11"}, 43},
+    {{"vs12"}, 44},  {{"vs13"}, 45},  {{"vs14"}, 46},  {{"vs15"}, 47},
+    {{"vs16"}, 48},  {{"vs17"}, 49},  {{"vs18"}, 50},  {{"vs19"}, 51},
+    {{"vs20"}, 52},  {{"vs21"}, 53},  {{"vs22"}, 54},  {{"vs23"}, 55},
+    {{"vs24"}, 56},  {{"vs25"}, 57},  {{"vs26"}, 58},  {{"vs27"}, 59},
+    {{"vs28"}, 60},  {{"vs29"}, 61},  {{"vs30"}, 62},  {{"vs31"}, 63},
+    {{"vs32"}, 77},  {{"vs33"}, 78},  {{"vs34"}, 79},  {{"vs35"}, 80},
+    {{"vs36"}, 81},  {{"vs37"}, 82},  {{"vs38"}, 83},  {{"vs39"}, 84},
+    {{"vs40"}, 85},  {{"vs41"}, 86},  {{"vs42"}, 87},  {{"vs43"}, 88},
+    {{"vs44"}, 89},  {{"vs45"}, 90},  {{"vs46"}, 91},  {{"vs47"}, 92},
+    {{"vs48"}, 93},  {{"vs49"}, 94},  {{"vs50"}, 95},  {{"vs51"}, 96},
+    {{"vs52"}, 97},  {{"vs53"}, 98},  {{"vs54"}, 99},  {{"vs55"}, 100},
+    {{"vs56"}, 101}, {{"vs57"}, 102}, {{"vs58"}, 103}, {{"vs59"}, 104},
+    {{"vs60"}, 105}, {{"vs61"}, 106}, {{"vs62"}, 107}, {{"vs63"}, 108},
+};
+
+ArrayRef<TargetInfo::AddlRegName> PPCTargetInfo::getGCCAddlRegNames() const {
+  if (ABI == "elfv2")
+    return llvm::makeArrayRef(GCCAddlRegNames);
+  else 
+    return TargetInfo::getGCCAddlRegNames(); 
+}
+
 static constexpr llvm::StringLiteral ValidCPUNames[] = {
     {"generic"}, {"440"},         {"450"},     {"601"},    {"602"},
     {"603"},     {"603e"},        {"603ev"},   {"604"},    {"604e"},
Index: test/CodeGen/inline-asm-matching-ppc-vsx.c
===================================================================
--- test/CodeGen/inline-asm-matching-ppc-vsx.c
+++ test/CodeGen/inline-asm-matching-ppc-vsx.c
@@ -0,0 +1,20 @@
+// REQUIRES: powerpc-registered-target
+
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-feature +vsx \
+// RUN:   -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
+
+// This case is to test VSX register support in the clobbers list for inline asm.
+void testVSX (void) {
+  unsigned int a = 0;
+  unsigned int *dbell=&a;
+  int d;
+  __asm__ __volatile__ (
+    "lxvw4x  %%vs32, 0, %2\n\t"
+    "stxvw4x %%vs32, 0, %1"
+    : "=m"(*(volatile unsigned int*)(dbell))
+    : "r" (dbell), "r" (&d)
+    : "vs32"
+  );
+}
+
+// CHECK: call void asm sideeffect "lxvw4x  %vs32, 0, $2\0A\09stxvw4x %vs32, 0, $1", "=*m,r,r,~{vs32}"