Index: lib/Target/AArch64/AArch64TargetMachine.cpp
===================================================================
--- lib/Target/AArch64/AArch64TargetMachine.cpp
+++ lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -556,6 +556,12 @@
 }
 
 void AArch64PassConfig::addPreEmitPass() {
+  // Machine Block Placement might have created new opportunities when run
+  // at O3, where the Tail Duplication Threshold is set to 4 instructions.
+  // Run the load/store optimizer once more.
+  if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
+    addPass(createAArch64LoadStoreOptimizationPass());
+
   if (EnableA53Fix835769)
     addPass(createAArch64A53Fix835769());
   // Relax conditional branch instructions if they're otherwise out of
Index: test/CodeGen/AArch64/ldst-opt-after-block-placement.ll
===================================================================
--- test/CodeGen/AArch64/ldst-opt-after-block-placement.ll
+++ test/CodeGen/AArch64/ldst-opt-after-block-placement.ll
@@ -9,15 +9,13 @@
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    tbz w0, #0, .LBB0_2
 ; CHECK-NEXT:  // %bb.1: // %if.then
-; CHECK-NEXT:    ldr x8, [x1, #16]
+; CHECK-NEXT:    ldp x9, x8, [x1, #8]
 ; CHECK-NEXT:    str xzr, [x1, #16]
-; CHECK-NEXT:    ldr x9, [x1, #8]
 ; CHECK-NEXT:    cmp x8, x9
 ; CHECK-NEXT:    b.lt .LBB0_3
 ; CHECK-NEXT:    b .LBB0_4
 ; CHECK-NEXT:  .LBB0_2: // %if.else
-; CHECK-NEXT:    ldr x8, [x1]
-; CHECK-NEXT:    ldr x9, [x1, #8]
+; CHECK-NEXT:    ldp x8, x9, [x1]
 ; CHECK-NEXT:    cmp x8, x9
 ; CHECK-NEXT:    b.ge .LBB0_4
 ; CHECK-NEXT:  .LBB0_3: // %exit1