Index: llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp =================================================================== --- llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp +++ llvm/trunk/lib/Target/X86/X86TargetTransformInfo.cpp @@ -1224,6 +1224,27 @@ // FIXME: Need a better design of the cost table to handle non-simple types of // potential massive combinations (elem_num x src_type x dst_type). + static const TypeConversionCostTblEntry AVX512BWConversionTbl[] { + { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, + { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 1 }, + + // Mask sign extend has an instruction. + { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, + { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, + + // Mask zero extend is a load + broadcast. + { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, + { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, + }; + static const TypeConversionCostTblEntry AVX512DQConversionTbl[] = { { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 1 }, { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, @@ -1549,6 +1570,12 @@ if (!SrcTy.isSimple() || !DstTy.isSimple()) return BaseT::getCastInstrCost(Opcode, Dst, Src); + if (ST->hasBWI()) + if (const auto *Entry = ConvertCostTableLookup(AVX512BWConversionTbl, ISD, + DstTy.getSimpleVT(), + SrcTy.getSimpleVT())) + return Entry->Cost; + if (ST->hasDQI()) if (const auto *Entry = ConvertCostTableLookup(AVX512DQConversionTbl, ISD, DstTy.getSimpleVT(), Index: llvm/trunk/test/Analysis/CostModel/X86/extend.ll =================================================================== --- llvm/trunk/test/Analysis/CostModel/X86/extend.ll +++ llvm/trunk/test/Analysis/CostModel/X86/extend.ll @@ -247,7 +247,7 @@ ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4i16 = zext <4 x i8> undef to <4 x i16> ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8i16 = zext <8 x i8> undef to <8 x i16> ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16i16 = zext <16 x i8> undef to <16 x i16> -; AVX512BW-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V32i16 = zext <32 x i8> undef to <32 x i16> +; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32i16 = zext <32 x i8> undef to <32 x i16> ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; BTVER2-LABEL: 'zext_vXi8' @@ -378,15 +378,15 @@ ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16i32 = zext <16 x i1> undef to <16 x i32> ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2i16 = zext <2 x i1> undef to <2 x i16> ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V4i16 = zext <4 x i1> undef to <4 x i16> -; AVX512BW-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8i16 = zext <8 x i1> undef to <8 x i16> -; AVX512BW-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V16i16 = zext <16 x i1> undef to <16 x i16> -; AVX512BW-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V32i16 = zext <32 x i1> undef to <32 x i16> +; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i16 = zext <8 x i1> undef to <8 x i16> +; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16i16 = zext <16 x i1> undef to <16 x i16> +; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32i16 = zext <32 x i1> undef to <32 x i16> ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2i8 = zext <2 x i1> undef to <2 x i8> ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V4i8 = zext <4 x i1> undef to <4 x i8> ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8i8 = zext <8 x i1> undef to <8 x i8> -; AVX512BW-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V16i8 = zext <16 x i1> undef to <16 x i8> -; AVX512BW-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V32i8 = zext <32 x i1> undef to <32 x i8> -; AVX512BW-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %V64i8 = zext <64 x i1> undef to <64 x i8> +; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16i8 = zext <16 x i1> undef to <16 x i8> +; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32i8 = zext <32 x i1> undef to <32 x i8> +; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V64i8 = zext <64 x i1> undef to <64 x i8> ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; BTVER2-LABEL: 'zext_vXi1' @@ -671,7 +671,7 @@ ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i16 = sext <4 x i8> undef to <4 x i16> ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8i16 = sext <8 x i8> undef to <8 x i16> ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16i16 = sext <16 x i8> undef to <16 x i16> -; AVX512BW-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V32i16 = sext <32 x i8> undef to <32 x i16> +; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32i16 = sext <32 x i8> undef to <32 x i16> ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; BTVER2-LABEL: 'sext_vXi8' @@ -802,15 +802,15 @@ ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16i32 = sext <16 x i1> undef to <16 x i32> ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2i16 = sext <2 x i1> undef to <2 x i16> ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V4i16 = sext <4 x i1> undef to <4 x i16> -; AVX512BW-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8i16 = sext <8 x i1> undef to <8 x i16> -; AVX512BW-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V16i16 = sext <16 x i1> undef to <16 x i16> -; AVX512BW-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V32i16 = sext <32 x i1> undef to <32 x i16> +; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8i16 = sext <8 x i1> undef to <8 x i16> +; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16i16 = sext <16 x i1> undef to <16 x i16> +; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32i16 = sext <32 x i1> undef to <32 x i16> ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V2i8 = sext <2 x i1> undef to <2 x i8> ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V4i8 = sext <4 x i1> undef to <4 x i8> ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8i8 = sext <8 x i1> undef to <8 x i8> -; AVX512BW-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V16i8 = sext <16 x i1> undef to <16 x i8> -; AVX512BW-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V32i8 = sext <32 x i1> undef to <32 x i8> -; AVX512BW-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %V64i8 = sext <64 x i1> undef to <64 x i8> +; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16i8 = sext <16 x i1> undef to <16 x i8> +; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V32i8 = sext <32 x i1> undef to <32 x i8> +; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V64i8 = sext <64 x i1> undef to <64 x i8> ; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; ; BTVER2-LABEL: 'sext_vXi1' Index: llvm/trunk/test/Analysis/CostModel/X86/min-legal-vector-width.ll =================================================================== --- llvm/trunk/test/Analysis/CostModel/X86/min-legal-vector-width.ll +++ llvm/trunk/test/Analysis/CostModel/X86/min-legal-vector-width.ll @@ -17,7 +17,7 @@ ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %B = zext <8 x i32> undef to <8 x i64> ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %C = zext <16 x i8> undef to <16 x i32> ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %D = zext <16 x i16> undef to <16 x i32> -; SKX256-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %E = zext <32 x i8> undef to <32 x i16> +; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %E = zext <32 x i8> undef to <32 x i16> ; SKX256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; VEC512-LABEL: 'zext256' @@ -25,7 +25,7 @@ ; VEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %B = zext <8 x i32> undef to <8 x i64> ; VEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %C = zext <16 x i8> undef to <16 x i32> ; VEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %D = zext <16 x i16> undef to <16 x i32> -; VEC512-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %E = zext <32 x i8> undef to <32 x i16> +; VEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %E = zext <32 x i8> undef to <32 x i16> ; VEC512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %A = zext <8 x i16> undef to <8 x i64> @@ -50,7 +50,7 @@ ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %B = zext <8 x i32> undef to <8 x i64> ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %C = zext <16 x i8> undef to <16 x i32> ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %D = zext <16 x i16> undef to <16 x i32> -; SKX256-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %E = zext <32 x i8> undef to <32 x i16> +; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %E = zext <32 x i8> undef to <32 x i16> ; SKX256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; VEC512-LABEL: 'zext512' @@ -58,7 +58,7 @@ ; VEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %B = zext <8 x i32> undef to <8 x i64> ; VEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %C = zext <16 x i8> undef to <16 x i32> ; VEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %D = zext <16 x i16> undef to <16 x i32> -; VEC512-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %E = zext <32 x i8> undef to <32 x i16> +; VEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %E = zext <32 x i8> undef to <32 x i16> ; VEC512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %A = zext <8 x i16> undef to <8 x i64> @@ -85,7 +85,7 @@ ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %C = sext <8 x i32> undef to <8 x i64> ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %D = sext <16 x i8> undef to <16 x i32> ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %E = sext <16 x i16> undef to <16 x i32> -; SKX256-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %F = sext <32 x i8> undef to <32 x i16> +; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F = sext <32 x i8> undef to <32 x i16> ; SKX256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; VEC512-LABEL: 'sext256' @@ -94,7 +94,7 @@ ; VEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %C = sext <8 x i32> undef to <8 x i64> ; VEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %D = sext <16 x i8> undef to <16 x i32> ; VEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %E = sext <16 x i16> undef to <16 x i32> -; VEC512-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %F = sext <32 x i8> undef to <32 x i16> +; VEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F = sext <32 x i8> undef to <32 x i16> ; VEC512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %A = sext <8 x i8> undef to <8 x i64> @@ -122,7 +122,7 @@ ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %C = sext <8 x i32> undef to <8 x i64> ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %D = sext <16 x i8> undef to <16 x i32> ; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %E = sext <16 x i16> undef to <16 x i32> -; SKX256-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %F = sext <32 x i8> undef to <32 x i16> +; SKX256-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F = sext <32 x i8> undef to <32 x i16> ; SKX256-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; VEC512-LABEL: 'sext512' @@ -131,7 +131,7 @@ ; VEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %C = sext <8 x i32> undef to <8 x i64> ; VEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %D = sext <16 x i8> undef to <16 x i32> ; VEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %E = sext <16 x i16> undef to <16 x i32> -; VEC512-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %F = sext <32 x i8> undef to <32 x i16> +; VEC512-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %F = sext <32 x i8> undef to <32 x i16> ; VEC512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %A = sext <8 x i8> undef to <8 x i64>