Index: lib/Target/SystemZ/SystemZInstrFP.td =================================================================== --- lib/Target/SystemZ/SystemZInstrFP.td +++ lib/Target/SystemZ/SystemZInstrFP.td @@ -187,7 +187,7 @@ let Predicates = [FeatureNoVectorEnhancements1] in { def : Pat<(f32 (fpround FP128:$src)), - (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_hh32)>; + (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_h32)>; def : Pat<(f64 (fpround FP128:$src)), (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_h64)>; } Index: lib/Target/SystemZ/SystemZRegisterInfo.h =================================================================== --- lib/Target/SystemZ/SystemZRegisterInfo.h +++ lib/Target/SystemZ/SystemZRegisterInfo.h @@ -24,10 +24,10 @@ // Return the subreg to use for referring to the even and odd registers // in a GR128 pair. Is32Bit says whether we want a GR32 or GR64. inline unsigned even128(bool Is32bit) { - return Is32bit ? subreg_hl32 : subreg_h64; + return Is32bit ? subreg_l32 : subreg_h64; } inline unsigned odd128(bool Is32bit) { - return Is32bit ? subreg_l32 : subreg_l64; + return Is32bit ? subreg_ll32 : subreg_l64; } } // end namespace SystemZ Index: lib/Target/SystemZ/SystemZRegisterInfo.cpp =================================================================== --- lib/Target/SystemZ/SystemZRegisterInfo.cpp +++ lib/Target/SystemZ/SystemZRegisterInfo.cpp @@ -34,11 +34,11 @@ if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) || MO.getSubReg() == SystemZ::subreg_l32 || - MO.getSubReg() == SystemZ::subreg_hl32) + MO.getSubReg() == SystemZ::subreg_ll32) return &SystemZ::GR32BitRegClass; if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) || MO.getSubReg() == SystemZ::subreg_h32 || - MO.getSubReg() == SystemZ::subreg_hh32) + MO.getSubReg() == SystemZ::subreg_lh32) return &SystemZ::GRH32BitRegClass; if (VRM && VRM->hasPhys(MO.getReg())) { Index: lib/Target/SystemZ/SystemZRegisterInfo.td =================================================================== --- lib/Target/SystemZ/SystemZRegisterInfo.td +++ lib/Target/SystemZ/SystemZRegisterInfo.td @@ -21,12 +21,12 @@ } let Namespace = "SystemZ" in { -def subreg_l32 : SubRegIndex<32, 0>; // Also acts as subreg_ll32. -def subreg_h32 : SubRegIndex<32, 32>; // Also acts as subreg_lh32. +def subreg_l32 : SubRegIndex<32, 0>; // Also acts as subreg_hl32. +def subreg_h32 : SubRegIndex<32, 32>; // Also acts as subreg_hh32. def subreg_l64 : SubRegIndex<64, 0>; def subreg_h64 : SubRegIndex<64, 64>; -def subreg_hh32 : ComposedSubRegIndex; -def subreg_hl32 : ComposedSubRegIndex; +def subreg_lh32 : ComposedSubRegIndex; +def subreg_ll32 : ComposedSubRegIndex; } // Define a register class that contains values of types TYPES and an @@ -59,17 +59,17 @@ // One of the 16 64-bit general-purpose registers. class GPR64 num, string n, GPR32 low, GPR32 high> - : SystemZRegWithSubregs { + : SystemZRegWithSubregs { let HWEncoding = num; - let SubRegIndices = [subreg_l32, subreg_h32]; + let SubRegIndices = [subreg_h32, subreg_l32]; let CoveredBySubRegs = 1; } // 8 even-odd pairs of GPR64s. class GPR128 num, string n, GPR64 low, GPR64 high> - : SystemZRegWithSubregs { + : SystemZRegWithSubregs { let HWEncoding = num; - let SubRegIndices = [subreg_l64, subreg_h64]; + let SubRegIndices = [subreg_h64, subreg_l64]; let CoveredBySubRegs = 1; } @@ -190,9 +190,9 @@ // 8 pairs of FPR64s, with a one-register gap inbetween. class FPR128 num, string n, FPR64 low, FPR64 high> - : SystemZRegWithSubregs { + : SystemZRegWithSubregs { let HWEncoding = num; - let SubRegIndices = [subreg_l64, subreg_h64]; + let SubRegIndices = [subreg_h64, subreg_l64]; let CoveredBySubRegs = 1; } Index: test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir =================================================================== --- test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir +++ test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir @@ -248,9 +248,9 @@ bb.9: %82 = VLVGP %67.subreg_h64, %67.subreg_h64 - %82 = VLVGH %82, %58.subreg_hl32, $noreg, 0 - %82 = VLVGH %82, %80.subreg_hl32, $noreg, 1 - dead %82 = VLVGH %82, %90.subreg_hl32, $noreg, 2 + %82 = VLVGH %82, %58.subreg_l32, $noreg, 0 + %82 = VLVGH %82, %80.subreg_l32, $noreg, 1 + dead %82 = VLVGH %82, %90.subreg_l32, $noreg, 2 %96 = AFIMux %96, 1879048192, implicit-def dead $cc %96 = SRL %96, $noreg, 31 dead %11 = VLVGF %11, %96, $noreg, 1 Index: test/CodeGen/SystemZ/cond-move-05.mir =================================================================== --- test/CodeGen/SystemZ/cond-move-05.mir +++ test/CodeGen/SystemZ/cond-move-05.mir @@ -67,8 +67,8 @@ undef %3.subreg_l64:gr128bit = LGHI 1 %3.subreg_h64:gr128bit = LLILL 0 %3:gr128bit = DLGR %3, %0 - CLFIMux %3.subreg_hl32, 3631842929, implicit-def $cc - %6:grx32bit = LOCRMux undef %6, %3.subreg_hl32, 14, 4, implicit killed $cc + CLFIMux %3.subreg_l32, 3631842929, implicit-def $cc + %6:grx32bit = LOCRMux undef %6, %3.subreg_l32, 14, 4, implicit killed $cc CHIMux %6, 0, implicit-def $cc BRC 14, 8, %bb.2.for.inc591.1.i.i, implicit killed $cc J %bb.1.cleanup584.i.i Index: test/CodeGen/SystemZ/regalloc-GR128-02.mir =================================================================== --- test/CodeGen/SystemZ/regalloc-GR128-02.mir +++ test/CodeGen/SystemZ/regalloc-GR128-02.mir @@ -63,6 +63,6 @@ Return bb.2 (%ir-block.5): - dead %0:grx32bit = COPY undef %6.subreg_l32 + dead %0:grx32bit = COPY undef %6.subreg_ll32 ... Index: test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir =================================================================== --- test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir +++ test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir @@ -22,7 +22,7 @@ body: | bb.0: %0 : gr128bit = IMPLICIT_DEF - %0.subreg_hl32 = COPY %0.subreg_l32 + %0.subreg_l32 = COPY %0.subreg_ll32 %1 : gr64bit = COPY %0.subreg_l64 %2 : addr64bit = LARL @g_167 STC %1.subreg_l32, %2, 8, $noreg