Index: llvm/lib/Target/AArch64/AArch64.td =================================================================== --- llvm/lib/Target/AArch64/AArch64.td +++ llvm/lib/Target/AArch64/AArch64.td @@ -306,6 +306,7 @@ include "AArch64Schedule.td" include "AArch64InstrInfo.td" +include "AArch64SchedPredicates.td" def AArch64InstrInfo : InstrInfo; Index: llvm/lib/Target/AArch64/AArch64InstrInfo.h =================================================================== --- llvm/lib/Target/AArch64/AArch64InstrInfo.h +++ llvm/lib/Target/AArch64/AArch64InstrInfo.h @@ -62,14 +62,6 @@ unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; - /// Returns true if there is a shiftable register and that the shift value - /// is non-zero. - static bool hasShiftedReg(const MachineInstr &MI); - - /// Returns true if there is an extendable register and that the extending - /// value is non-zero. - static bool hasExtendedReg(const MachineInstr &MI); - /// Does this instruction set its full destination register to zero? static bool isGPRZero(const MachineInstr &MI); @@ -79,11 +71,6 @@ /// Does this instruction rename an FPR without modifying bits? static bool isFPRCopy(const MachineInstr &MI); - /// Return true if this is load/store scales or extends its register offset. - /// This refers to scaling a dynamic index as opposed to scaled immediates. - /// MI should be a memory op that allows scaled addressing. - static bool isScaledAddr(const MachineInstr &MI); - /// Return true if pairing the given load or store is hinted to be /// unprofitable. static bool isLdStPairSuppressed(const MachineInstr &MI); @@ -277,6 +264,9 @@ /// on Windows. static bool isSEHInstruction(const MachineInstr &MI); +#define GET_TII_HELPER_DECLS +#include "AArch64GenInstrInfo.inc" + private: /// Sets the offsets on outlined instructions in \p MBB which use SP /// so that they will be valid post-outlining. Index: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -1938,71 +1938,6 @@ return true; } -/// Return true if this is this instruction has a non-zero immediate -bool AArch64InstrInfo::hasShiftedReg(const MachineInstr &MI) { - switch (MI.getOpcode()) { - default: - break; - case AArch64::ADDSWrs: - case AArch64::ADDSXrs: - case AArch64::ADDWrs: - case AArch64::ADDXrs: - case AArch64::ANDSWrs: - case AArch64::ANDSXrs: - case AArch64::ANDWrs: - case AArch64::ANDXrs: - case AArch64::BICSWrs: - case AArch64::BICSXrs: - case AArch64::BICWrs: - case AArch64::BICXrs: - case AArch64::EONWrs: - case AArch64::EONXrs: - case AArch64::EORWrs: - case AArch64::EORXrs: - case AArch64::ORNWrs: - case AArch64::ORNXrs: - case AArch64::ORRWrs: - case AArch64::ORRXrs: - case AArch64::SUBSWrs: - case AArch64::SUBSXrs: - case AArch64::SUBWrs: - case AArch64::SUBXrs: - if (MI.getOperand(3).isImm()) { - unsigned val = MI.getOperand(3).getImm(); - return (val != 0); - } - break; - } - return false; -} - -/// Return true if this is this instruction has a non-zero immediate -bool AArch64InstrInfo::hasExtendedReg(const MachineInstr &MI) { - switch (MI.getOpcode()) { - default: - break; - case AArch64::ADDSWrx: - case AArch64::ADDSXrx: - case AArch64::ADDSXrx64: - case AArch64::ADDWrx: - case AArch64::ADDXrx: - case AArch64::ADDXrx64: - case AArch64::SUBSWrx: - case AArch64::SUBSXrx: - case AArch64::SUBSXrx64: - case AArch64::SUBWrx: - case AArch64::SUBXrx: - case AArch64::SUBXrx64: - if (MI.getOperand(3).isImm()) { - unsigned val = MI.getOperand(3).getImm(); - return (val != 0); - } - break; - } - - return false; -} - // Return true if this instruction simply sets its single destination register // to zero. This is equivalent to a register rename of the zero-register. bool AArch64InstrInfo::isGPRZero(const MachineInstr &MI) { @@ -2125,67 +2060,6 @@ return 0; } -/// Return true if this is load/store scales or extends its register offset. -/// This refers to scaling a dynamic index as opposed to scaled immediates. -/// MI should be a memory op that allows scaled addressing. -bool AArch64InstrInfo::isScaledAddr(const MachineInstr &MI) { - switch (MI.getOpcode()) { - default: - break; - case AArch64::LDRBBroW: - case AArch64::LDRBroW: - case AArch64::LDRDroW: - case AArch64::LDRHHroW: - case AArch64::LDRHroW: - case AArch64::LDRQroW: - case AArch64::LDRSBWroW: - case AArch64::LDRSBXroW: - case AArch64::LDRSHWroW: - case AArch64::LDRSHXroW: - case AArch64::LDRSWroW: - case AArch64::LDRSroW: - case AArch64::LDRWroW: - case AArch64::LDRXroW: - case AArch64::STRBBroW: - case AArch64::STRBroW: - case AArch64::STRDroW: - case AArch64::STRHHroW: - case AArch64::STRHroW: - case AArch64::STRQroW: - case AArch64::STRSroW: - case AArch64::STRWroW: - case AArch64::STRXroW: - case AArch64::LDRBBroX: - case AArch64::LDRBroX: - case AArch64::LDRDroX: - case AArch64::LDRHHroX: - case AArch64::LDRHroX: - case AArch64::LDRQroX: - case AArch64::LDRSBWroX: - case AArch64::LDRSBXroX: - case AArch64::LDRSHWroX: - case AArch64::LDRSHXroX: - case AArch64::LDRSWroX: - case AArch64::LDRSroX: - case AArch64::LDRWroX: - case AArch64::LDRXroX: - case AArch64::STRBBroX: - case AArch64::STRBroX: - case AArch64::STRDroX: - case AArch64::STRHHroX: - case AArch64::STRHroX: - case AArch64::STRQroX: - case AArch64::STRSroX: - case AArch64::STRWroX: - case AArch64::STRXroX: - - unsigned Val = MI.getOperand(3).getImm(); - AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getMemExtendType(Val); - return (ExtType != AArch64_AM::UXTX) || AArch64_AM::getMemDoShift(Val); - } - return false; -} - /// Check all MachineMemOperands for a hint to suppress pairing. bool AArch64InstrInfo::isLdStPairSuppressed(const MachineInstr &MI) { return llvm::any_of(MI.memoperands(), [](MachineMemOperand *MMO) { @@ -5962,3 +5836,6 @@ MachineFunction &MF) const { return MF.getFunction().optForMinSize(); } + +#define GET_TII_HELPERS +#include "AArch64GenInstrInfo.inc" Index: llvm/lib/Target/AArch64/AArch64SchedPredicates.td =================================================================== --- /dev/null +++ llvm/lib/Target/AArch64/AArch64SchedPredicates.td @@ -0,0 +1,338 @@ +//===- AArch64SchedPredicates.td - AArch64 Sched Preds -----*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines scheduling predicate definitions that are used by the +// AArch64 subtargets. +// +//===----------------------------------------------------------------------===// + +// Generic predicates. + +// Identify whether an instruction is the 32-bit GP form based on its result. +def IsWFormPred : CheckAll<[CheckIsRegOperand<0>, + CheckAny<[CheckRegOperand<0, W0>, + CheckRegOperand<0, W1>, + CheckRegOperand<0, W2>, + CheckRegOperand<0, W3>, + CheckRegOperand<0, W4>, + CheckRegOperand<0, W5>, + CheckRegOperand<0, W6>, + CheckRegOperand<0, W7>, + CheckRegOperand<0, W8>, + CheckRegOperand<0, W9>, + CheckRegOperand<0, W10>, + CheckRegOperand<0, W11>, + CheckRegOperand<0, W12>, + CheckRegOperand<0, W13>, + CheckRegOperand<0, W14>, + CheckRegOperand<0, W15>, + CheckRegOperand<0, W16>, + CheckRegOperand<0, W17>, + CheckRegOperand<0, W18>, + CheckRegOperand<0, W19>, + CheckRegOperand<0, W20>, + CheckRegOperand<0, W21>, + CheckRegOperand<0, W22>, + CheckRegOperand<0, W23>, + CheckRegOperand<0, W24>, + CheckRegOperand<0, W25>, + CheckRegOperand<0, W26>, + CheckRegOperand<0, W27>, + CheckRegOperand<0, W28>, + CheckRegOperand<0, W29>, + CheckRegOperand<0, W30>, + CheckRegOperand<0, WSP>, + CheckRegOperand<0, WZR>]>]>; + +// Identify whether an instruction is the 64-bit GP form based on its result. +def IsXFormPred : CheckAll<[CheckIsRegOperand<0>, + CheckAny<[CheckRegOperand<0, X0>, + CheckRegOperand<0, X1>, + CheckRegOperand<0, X2>, + CheckRegOperand<0, X3>, + CheckRegOperand<0, X4>, + CheckRegOperand<0, X5>, + CheckRegOperand<0, X6>, + CheckRegOperand<0, X7>, + CheckRegOperand<0, X8>, + CheckRegOperand<0, X9>, + CheckRegOperand<0, X10>, + CheckRegOperand<0, X11>, + CheckRegOperand<0, X12>, + CheckRegOperand<0, X13>, + CheckRegOperand<0, X14>, + CheckRegOperand<0, X15>, + CheckRegOperand<0, X16>, + CheckRegOperand<0, X17>, + CheckRegOperand<0, X18>, + CheckRegOperand<0, X19>, + CheckRegOperand<0, X20>, + CheckRegOperand<0, X21>, + CheckRegOperand<0, X22>, + CheckRegOperand<0, X23>, + CheckRegOperand<0, X24>, + CheckRegOperand<0, X25>, + CheckRegOperand<0, X26>, + CheckRegOperand<0, X27>, + CheckRegOperand<0, X28>, + CheckRegOperand<0, FP>, + CheckRegOperand<0, LR>, + CheckRegOperand<0, SP>, + CheckRegOperand<0, XZR>]>]>; + +// Identify whether an instruction is the 64-bit NEON form based on its result. +def IsDFormPred : CheckAll<[CheckIsRegOperand<0>, + CheckAny<[CheckRegOperand<0, D0>, + CheckRegOperand<0, D1>, + CheckRegOperand<0, D2>, + CheckRegOperand<0, D3>, + CheckRegOperand<0, D4>, + CheckRegOperand<0, D5>, + CheckRegOperand<0, D6>, + CheckRegOperand<0, D7>, + CheckRegOperand<0, D8>, + CheckRegOperand<0, D9>, + CheckRegOperand<0, D10>, + CheckRegOperand<0, D11>, + CheckRegOperand<0, D12>, + CheckRegOperand<0, D13>, + CheckRegOperand<0, D14>, + CheckRegOperand<0, D15>, + CheckRegOperand<0, D16>, + CheckRegOperand<0, D17>, + CheckRegOperand<0, D18>, + CheckRegOperand<0, D19>, + CheckRegOperand<0, D20>, + CheckRegOperand<0, D21>, + CheckRegOperand<0, D22>, + CheckRegOperand<0, D23>, + CheckRegOperand<0, D24>, + CheckRegOperand<0, D25>, + CheckRegOperand<0, D26>, + CheckRegOperand<0, D27>, + CheckRegOperand<0, D28>, + CheckRegOperand<0, D29>, + CheckRegOperand<0, D30>, + CheckRegOperand<0, D31>]>]>; + +// Identify whether an instruction is the 128-bit NEON form based on its result. +def IsQFormPred : CheckAll<[CheckIsRegOperand<0>, + CheckAny<[CheckRegOperand<0, Q0>, + CheckRegOperand<0, Q1>, + CheckRegOperand<0, Q2>, + CheckRegOperand<0, Q3>, + CheckRegOperand<0, Q4>, + CheckRegOperand<0, Q5>, + CheckRegOperand<0, Q6>, + CheckRegOperand<0, Q7>, + CheckRegOperand<0, Q8>, + CheckRegOperand<0, Q9>, + CheckRegOperand<0, Q10>, + CheckRegOperand<0, Q11>, + CheckRegOperand<0, Q12>, + CheckRegOperand<0, Q13>, + CheckRegOperand<0, Q14>, + CheckRegOperand<0, Q15>, + CheckRegOperand<0, Q16>, + CheckRegOperand<0, Q17>, + CheckRegOperand<0, Q18>, + CheckRegOperand<0, Q19>, + CheckRegOperand<0, Q20>, + CheckRegOperand<0, Q21>, + CheckRegOperand<0, Q22>, + CheckRegOperand<0, Q23>, + CheckRegOperand<0, Q24>, + CheckRegOperand<0, Q25>, + CheckRegOperand<0, Q26>, + CheckRegOperand<0, Q27>, + CheckRegOperand<0, Q28>, + CheckRegOperand<0, Q29>, + CheckRegOperand<0, Q30>, + CheckRegOperand<0, Q31>]>]>; + +// Identify arithmetic instructions with extend. +def IsArithExtPred : CheckOpcode<[ADDWrx, ADDXrx, ADDXrx64, ADDSWrx, ADDSXrx, ADDSXrx64, + SUBWrx, SUBXrx, SUBXrx64, SUBSWrx, SUBSXrx, SUBSXrx64]>; + +// Identify arithmetic immediate instructions with shift. +def IsArithImmPred : CheckOpcode<[ADDWri, ADDXri, ADDSWri, ADDSXri, + SUBWri, SUBXri, SUBSWri, SUBSXri]>; + +// Identify arithmetic instructions with shift. +def IsArithShiftPred : CheckOpcode<[ADDWrs, ADDXrs, ADDSWrs, ADDSXrs, + SUBWrs, SUBXrs, SUBSWrs, SUBSXrs]>; + +// Identify arithmetic instructions without shift. +def IsArithUnshiftPred : CheckOpcode<[ADDWrr, ADDXrr, ADDSWrr, ADDSXrr, + SUBWrr, SUBXrr, SUBSWrr, SUBSXrr]>; + +// Identify logic immediate instructions with shift. +def IsLogicImmPred : CheckOpcode<[ANDWri, ANDXri, + EORWri, EORXri, + ORRWri, ORRXri]>; + +// Identify logic instructions with shift. +def IsLogicShiftPred : CheckOpcode<[ANDWrs, ANDXrs, ANDSWrs, ANDSXrs, + BICWrs, BICXrs, BICSWrs, BICSXrs, + EONWrs, EONXrs, + EORWrs, EORXrs, + ORNWrs, ORNXrs, + ORRWrs, ORRXrs]>; + +// Identify logic instructions without shift. +def IsLogicUnshiftPred : CheckOpcode<[ANDWrr, ANDXrr, ANDSWrr, ANDSXrr, + BICWrr, BICXrr, BICSWrr, BICSXrr, + EONWrr, EONXrr, + EORWrr, EORXrr, + ORNWrr, ORNXrr, + ORRWrr, ORRXrr]>; + +// Identify arithmetic and logic immediate instructions with shift. +def IsArithLogicImmPred : CheckAny<[IsArithImmPred, + IsLogicImmPred]>; + +// Identify arithmetic and logic instructions with shift. +def IsArithLogicShiftPred : CheckAny<[IsArithShiftPred, IsArithUnshiftPred, + IsLogicShiftPred, IsLogicUnshiftPred]>; + +// Identify an instruction that effectively transfers a register to another. +def IsMoveIdiomPred : CheckAny<[// ADD Rd, SP, #0 + CheckAll<[CheckOpcode<[ADDWri, ADDXri]>, + CheckAny<[CheckRegOperand<1, WSP>, CheckRegOperand<1, SP>]>, + CheckZeroOperand<2>]>, + // ORR Rd, ZR, Rm, LSL #0 + CheckAll<[CheckOpcode<[ORRWrs, ORRXrs]>, + CheckAny<[CheckRegOperand<1, WZR>, CheckRegOperand<1, XZR>]>, + CheckZeroOperand<3>]>]>; + +// Identify an instruction that effectively resets a GP register to zero. +def IsZeroIdiomPred : // ORR Rd, ZR, #0 + CheckAll<[CheckOpcode<[ORRWri, ORRXri]>, + CheckAny<[CheckRegOperand<1, WZR>, CheckRegOperand<1, XZR>]>, + CheckZeroOperand<2>]>; + +// Identify an instruction that effectively resets a FP register to zero. +def IsZeroFPIdiomPred : CheckAny<[// MOVI Vd, #0 + CheckAll<[CheckOpcode<[MOVIv8b_ns, MOVIv16b_ns, MOVID, MOVIv2d_ns]>, + CheckZeroOperand<1>]>, + // MOVI Vd, #0, LSL #0 + CheckAll<[CheckOpcode<[MOVIv4i16, MOVIv8i16, MOVIv2i32, MOVIv4i32]>, + CheckZeroOperand<1>, + CheckZeroOperand<2>]>]>; + +// Identify whether an instruction whose result is a long vector +// operates on the upper half of the input registers. +def IsLongVectorUpperPred : CheckOpcode<[FCVTLv8i16, FCVTLv4i32, + FCVTNv8i16, FCVTNv4i32, + FCVTXNv4f32, + PMULLv16i8, PMULLv2i64, + RADDHNv8i16_v16i8, RADDHNv4i32_v8i16, RADDHNv2i64_v4i32, + RSHRNv16i8_shift, RSHRNv8i16_shift, RSHRNv4i32_shift, + RSUBHNv8i16_v16i8, RSUBHNv4i32_v8i16, RSUBHNv2i64_v4i32, + SABALv16i8_v8i16, SABALv8i16_v4i32, SABALv4i32_v2i64, + SABDLv16i8_v8i16, SABDLv8i16_v4i32, SABDLv4i32_v2i64, + SADDLv16i8_v8i16, SADDLv8i16_v4i32, SADDLv4i32_v2i64, + SADDWv16i8_v8i16, SADDWv8i16_v4i32, SADDWv4i32_v2i64, + SHLLv16i8, SHLLv8i16, SHLLv4i32, + SHRNv16i8_shift, SHRNv8i16_shift, SHRNv4i32_shift, + SMLALv16i8_v8i16, SMLALv8i16_v4i32, SMLALv4i32_v2i64, + SMLALv8i16_indexed, SMLALv4i32_indexed, + SMLSLv16i8_v8i16, SMLSLv8i16_v4i32, SMLSLv4i32_v2i64, + SMLSLv8i16_indexed, SMLSLv4i32_indexed, + SMULLv16i8_v8i16, SMULLv8i16_v4i32, SMULLv4i32_v2i64, + SMULLv8i16_indexed, SMULLv4i32_indexed, + SQDMLALv8i16_v4i32, SQDMLALv4i32_v2i64, + SQDMLALv8i16_indexed, SQDMLALv4i32_indexed, + SQDMLSLv8i16_v4i32, SQDMLSLv4i32_v2i64, + SQDMLSLv8i16_indexed, SQDMLSLv4i32_indexed, + SQDMULLv8i16_v4i32, SQDMULLv4i32_v2i64, + SQDMULLv8i16_indexed, SQDMULLv4i32_indexed, + SQRSHRNv16i8_shift, SQRSHRNv8i16_shift, SQRSHRNv4i32_shift, + SQRSHRUNv16i8_shift, SQRSHRUNv8i16_shift, SQRSHRUNv4i32_shift, + SQSHRNv16i8_shift, SQSHRNv8i16_shift, SQSHRNv4i32_shift, + SQSHRUNv16i8_shift, SQSHRUNv8i16_shift, SQSHRUNv4i32_shift, + SQXTNv16i8, SQXTNv8i16, SQXTNv4i32, + SQXTUNv16i8, SQXTUNv8i16, SQXTUNv4i32, + SSHLLv16i8_shift, SSHLLv8i16_shift, SSHLLv4i32_shift, + SSUBLv16i8_v8i16, SSUBLv8i16_v4i32, SSUBLv4i32_v2i64, + SSUBWv16i8_v8i16, SSUBWv8i16_v4i32, SSUBWv4i32_v2i64, + UABALv16i8_v8i16, UABALv8i16_v4i32, UABALv4i32_v2i64, + UABDLv16i8_v8i16, UABDLv8i16_v4i32, UABDLv4i32_v2i64, + UADDLv16i8_v8i16, UADDLv8i16_v4i32, UADDLv4i32_v2i64, + UADDWv16i8_v8i16, UADDWv8i16_v4i32, UADDWv4i32_v2i64, + UMLALv16i8_v8i16, UMLALv8i16_v4i32, UMLALv4i32_v2i64, + UMLALv8i16_indexed, UMLALv4i32_indexed, + UMLSLv16i8_v8i16, UMLSLv8i16_v4i32, UMLSLv4i32_v2i64, + UMLSLv8i16_indexed, UMLSLv4i32_indexed, + UMULLv16i8_v8i16, UMULLv8i16_v4i32, UMULLv4i32_v2i64, + UMULLv8i16_indexed, UMULLv4i32_indexed, + UQSHRNv16i8_shift, UQSHRNv8i16_shift, UQSHRNv4i32_shift, + UQXTNv16i8, UQXTNv8i16, UQXTNv4i32, + USHLLv16i8_shift, USHLLv8i16_shift, USHLLv4i32_shift, + USUBLv16i8_v8i16, USUBLv8i16_v4i32, USUBLv4i32_v2i64, + USUBWv16i8_v8i16, USUBWv8i16_v4i32, USUBWv4i32_v2i64, + XTNv16i8, XTNv8i16, XTNv4i32]>; + +// Identify whether an instruction is a load +// using the register offset addressing mode. +def IsLoadRegOffsetPred : CheckOpcode<[PRFMroW, PRFMroX, + LDRBBroW, LDRBBroX, + LDRSBWroW, LDRSBWroX, LDRSBXroW, LDRSBXroX, + LDRHHroW, LDRHHroX, + LDRSHWroW, LDRSHWroX, LDRSHXroW, LDRSHXroX, + LDRWroW, LDRWroX, + LDRSWroW, LDRSWroX, + LDRXroW, LDRXroX, + LDRBroW, LDRBroX, + LDRHroW, LDRHroX, + LDRSroW, LDRSroX, + LDRDroW, LDRDroX]>; + +// Identify whether an instruction is a load +// using the register offset addressing mode. +def IsStoreRegOffsetPred : CheckOpcode<[STRBBroW, STRBBroX, + STRHHroW, STRHHroX, + STRWroW, STRWroX, + STRXroW, STRXroX, + STRBroW, STRBroX, + STRHroW, STRHroX, + STRSroW, STRSroX, + STRDroW, STRDroX]>; + +// Target predicates. + +// Identify arithmetic instructions with an extended register. +def RegExtendedBody : CheckAll<[IsArithExtPred, + CheckNot>]>; +def RegExtendedPred : MCSchedPredicate; +def RegExtendedFn : TIIPredicate<"hasExtendedReg", + MCReturnStatement>; + +// Identify arithmetic and logic instructions with a shifted register. +def RegShiftedBody : CheckAll<[IsArithLogicShiftPred, + CheckNot>]>; +def RegShiftedPred : MCSchedPredicate; +def RegShiftedFn : TIIPredicate<"hasShiftedReg", + MCReturnStatement>; + +// Identify a load or store using the register offset addressing mode +// with an extended or scaled register. +def ScaledIdxBody : CheckAll<[CheckAny<[IsLoadRegOffsetPred, IsStoreRegOffsetPred]>, + CheckAny<[CheckImmOperand<3, 4>, // UXTW + CheckImmOperand<3, 5>, // Scaled + // LSL + CheckImmOperand<3, 7>, // Scaled + CheckImmOperand<3, 12>, // SXTW + CheckImmOperand<3, 13>, // Scaled + CheckImmOperand<3, 14>, // SXTX, + CheckImmOperand<3, 15> // Scaled + ]>]>; +def ScaledIdxPred : MCSchedPredicate; +def ScaledIdxFn : TIIPredicate<"isScaledAddr", + MCReturnStatement>; Index: llvm/lib/Target/AArch64/AArch64Schedule.td =================================================================== --- llvm/lib/Target/AArch64/AArch64Schedule.td +++ llvm/lib/Target/AArch64/AArch64Schedule.td @@ -50,17 +50,6 @@ def WriteSTIdx : SchedWrite; // Store to a register index (maybe scaled). def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST. -// Predicate for determining when a shiftable register is shifted. -def RegShiftedPred : SchedPredicate<[{TII->hasShiftedReg(*MI)}]>; - -// Predicate for determining when a extendedable register is extended. -def RegExtendedPred : SchedPredicate<[{TII->hasExtendedReg(*MI)}]>; - -// ScaledIdxPred is true if a WriteLDIdx operand will be -// scaled. Subtargets can use this to dynamically select resources and -// latency for WriteLDIdx and ReadAdrBase. -def ScaledIdxPred : SchedPredicate<[{TII->isScaledAddr(*MI)}]>; - // Serialized two-level address load. // EXAMPLE: LOADGot def WriteLDAdr : WriteSequence<[WriteAdr, WriteLD]>;