Index: include/llvm/Support/AArch64TargetParser.h =================================================================== --- include/llvm/Support/AArch64TargetParser.h +++ include/llvm/Support/AArch64TargetParser.h @@ -47,6 +47,7 @@ AEK_FP16FML = 1 << 17, AEK_RAND = 1 << 18, AEK_MTE = 1 << 19, + AEK_SSBS = 1 << 20, }; enum class ArchKind { Index: include/llvm/Support/AArch64TargetParser.def =================================================================== --- include/llvm/Support/AArch64TargetParser.def +++ include/llvm/Support/AArch64TargetParser.def @@ -72,6 +72,7 @@ AARCH64_ARCH_EXT_NAME("rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc") AARCH64_ARCH_EXT_NAME("rng", AArch64::AEK_RAND, "+rand", "-rand") AARCH64_ARCH_EXT_NAME("memtag", AArch64::AEK_MTE, "+mte", "-mte") +AARCH64_ARCH_EXT_NAME("ssbs", AArch64::AEK_SSBS, "+ssbs", "-ssbs") #undef AARCH64_ARCH_EXT_NAME #ifndef AARCH64_CPU_NAME Index: lib/Target/AArch64/AArch64.td =================================================================== --- lib/Target/AArch64/AArch64.td +++ lib/Target/AArch64/AArch64.td @@ -306,6 +306,9 @@ def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict", "true", "Enable architectural speculation restriction" >; +def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS", + "true", "Enable Speculative Store Bypass Safe bit" >; + def FeatureSpecCtrl : SubtargetFeature<"specctrl", "HasSpecCtrl", "true", "Enable speculation control barrier" >; @@ -349,7 +352,7 @@ def HasV8_5aOps : SubtargetFeature< "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions", [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict, - FeatureSpecCtrl, FeaturePredCtrl, FeatureCacheDeepPersist, + FeatureSSBS, FeatureSpecCtrl, FeaturePredCtrl, FeatureCacheDeepPersist, FeatureBranchTargetId] >; Index: lib/Target/AArch64/AArch64Subtarget.h =================================================================== --- lib/Target/AArch64/AArch64Subtarget.h +++ lib/Target/AArch64/AArch64Subtarget.h @@ -127,6 +127,7 @@ bool HasFRInt3264 = false; bool HasSpecRestrict = false; bool HasSpecCtrl = false; + bool HasSSBS = false; bool HasPredCtrl = false; bool HasCCDP = false; bool HasBTI = false; @@ -355,6 +356,7 @@ bool hasFRInt3264() const { return HasFRInt3264; } bool hasSpecRestrict() const { return HasSpecRestrict; } bool hasSpecCtrl() const { return HasSpecCtrl; } + bool hasSSBS() const { return HasSSBS; } bool hasPredCtrl() const { return HasPredCtrl; } bool hasCCDP() const { return HasCCDP; } bool hasBTI() const { return HasBTI; } Index: lib/Target/AArch64/AArch64SystemOperands.td =================================================================== --- lib/Target/AArch64/AArch64SystemOperands.td +++ lib/Target/AArch64/AArch64SystemOperands.td @@ -343,7 +343,7 @@ let Requires = [{ {AArch64::FeatureDIT} }] in def : PState<"DIT", 0b11010>; // v8.5a Spectre Mitigation -let Requires = [{ {AArch64::FeatureSpecRestrict} }] in +let Requires = [{ {AArch64::FeatureSSBS} }] in def : PState<"SSBS", 0b11001>; // v8.5a Memory Tagging Extension let Requires = [{ {AArch64::FeatureMTE} }] in @@ -1444,7 +1444,7 @@ // V8.5a Spectre mitigation SSBS register // Op0 Op1 CRn CRm Op2 -let Requires = [{ {AArch64::FeatureSpecRestrict} }] in +let Requires = [{ {AArch64::FeatureSSBS} }] in def : RWSysReg<"SSBS", 0b11, 0b011, 0b0100, 0b0010, 0b110>; // v8.5a Memory Tagging Extension Index: test/MC/AArch64/armv8.5a-specrestrict.s =================================================================== --- test/MC/AArch64/armv8.5a-specrestrict.s +++ test/MC/AArch64/armv8.5a-specrestrict.s @@ -51,19 +51,3 @@ // NOSPECID-NEXT: {{scxtnum_el3|SCXTNUM_EL3}} // NOSPECID: error: expected writable system register // NOSPECID-NEXT: {{scxtnum_el12|SCXTNUM_EL12}} - -mrs x2, SSBS - -// CHECK: mrs x2, {{ssbs|SSBS}} // encoding: [0xc2,0x42,0x3b,0xd5] -// NOSPECID: error: expected readable system register -// NOSPECID-NEXT: mrs x2, {{ssbs|SSBS}} - -msr SSBS, x3 -msr SSBS, #1 - -// CHECK: msr {{ssbs|SSBS}}, x3 // encoding: [0xc3,0x42,0x1b,0xd5] -// CHECK: msr {{ssbs|SSBS}}, #1 // encoding: [0x3f,0x41,0x03,0xd5] -// NOSPECID: error: expected writable system register or pstate -// NOSPECID-NEXT: msr {{ssbs|SSBS}}, x3 -// NOSPECID: error: expected writable system register or pstate -// NOSPECID-NEXT: msr {{ssbs|SSBS}}, #1 Index: test/MC/AArch64/armv8.5a-ssbs-error.s =================================================================== --- test/MC/AArch64/armv8.5a-ssbs-error.s +++ test/MC/AArch64/armv8.5a-ssbs-error.s @@ -1,6 +1,6 @@ -// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+specrestrict < %s 2>&1 | FileCheck %s -// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1 | FileCheck %s -// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-specrestrict < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID +// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+ssbs < %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-ssbs < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID msr SSBS, #2 Index: test/MC/AArch64/armv8.5a-ssbs.s =================================================================== --- /dev/null +++ test/MC/AArch64/armv8.5a-ssbs.s @@ -0,0 +1,19 @@ +// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+ssbs < %s | FileCheck %s +// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s | FileCheck %s +// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-ssbs < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID + +mrs x2, SSBS + +// CHECK: mrs x2, {{ssbs|SSBS}} // encoding: [0xc2,0x42,0x3b,0xd5] +// NOSPECID: error: expected readable system register +// NOSPECID-NEXT: mrs x2, {{ssbs|SSBS}} + +msr SSBS, x3 +msr SSBS, #1 + +// CHECK: msr {{ssbs|SSBS}}, x3 // encoding: [0xc3,0x42,0x1b,0xd5] +// CHECK: msr {{ssbs|SSBS}}, #1 // encoding: [0x3f,0x41,0x03,0xd5] +// NOSPECID: error: expected writable system register or pstate +// NOSPECID-NEXT: msr {{ssbs|SSBS}}, x3 +// NOSPECID: error: expected writable system register or pstate +// NOSPECID-NEXT: msr {{ssbs|SSBS}}, #1 Index: test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt =================================================================== --- test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt +++ test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt @@ -40,13 +40,3 @@ # NOSPECID: msr S3_4_C13_C0_7, x6 # NOSPECID: msr S3_6_C13_C0_7, x5 # NOSPECID: msr S3_5_C13_C0_7, x4 - -[0x3f 0x41 0x03 0xd5] -[0xc3 0x42 0x1b 0xd5] -[0xc2 0x42 0x3b 0xd5] -# CHECK: msr SSBS, #1 -# CHECK: msr SSBS, x3 -# CHECK: mrs x2, SSBS -# NOSPECID: msr S0_3_C4_C1_1, xzr -# NOSPECID: msr S3_3_C4_C2_6, x3 -# NOSPECID: mrs x2, S3_3_C4_C2_6 Index: test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt =================================================================== --- /dev/null +++ test/MC/Disassembler/AArch64/armv8.5a-ssbs.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple=aarch64 -mattr=+ssbs -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=-ssbs -disassemble < %s | FileCheck %s --check-prefix=NOSPECID + +[0x3f 0x41 0x03 0xd5] +[0xc3 0x42 0x1b 0xd5] +[0xc2 0x42 0x3b 0xd5] +# CHECK: msr SSBS, #1 +# CHECK: msr SSBS, x3 +# CHECK: mrs x2, SSBS +# NOSPECID: msr S0_3_C4_C1_1, xzr +# NOSPECID: msr S3_3_C4_C2_6, x3 +# NOSPECID: mrs x2, S3_3_C4_C2_6 Index: unittests/Support/TargetParserTest.cpp =================================================================== --- unittests/Support/TargetParserTest.cpp +++ unittests/Support/TargetParserTest.cpp @@ -508,7 +508,7 @@ } TEST(TargetParserTest, ARMFPUVersion) { - for (ARM::FPUKind FK = static_cast(0); + for (ARM::FPUKind FK = static_cast(0); FK <= ARM::FPUKind::FK_LAST; FK = static_cast(static_cast(FK) + 1)) if (FK == ARM::FK_LAST || ARM::getFPUName(FK) == "invalid" || @@ -992,7 +992,8 @@ {"dotprod", "nodotprod", "+dotprod", "-dotprod"}, {"rcpc", "norcpc", "+rcpc", "-rcpc" }, {"rng", "norng", "+rand", "-rand"}, - {"memtag", "nomemtag", "+mte", "-mte"}}; + {"memtag", "nomemtag", "+mte", "-mte"}, + {"ssbs", "nossbs", "+ssbs", "-ssbs"}}; for (unsigned i = 0; i < array_lengthof(ArchExt); i++) { EXPECT_EQ(StringRef(ArchExt[i][2]),