This is a fixed version of rL208992 - all known bugs should be fixed and it passes all the tests I'm running.
For Thumb1, the load/store optimizer will currently only merge LDRs/STRs if the base register is dead after the merged LDM/STM, or if there is no writeback to the base register.
However, this is overly conservative. If the condition flags aren't live at the location where we want to merge, we can do a few other things:
- Reset the base register writeback with a SUBS.
- Try to update future instructions such as ADDS/SUBS with the base register (as long as their definition of the CPSR is also dead).
This patch adds a function that will try to go forward in the basic block and modify any instructions that use the new value of the base register with writeback applied. If it encounters any hazards, it resets the base register to the old value.
I'll try to find a test case for rL217881 as a follow-up commit.