Index: lib/Target/RISCV/RISCVInstrInfo.td =================================================================== --- lib/Target/RISCV/RISCVInstrInfo.td +++ lib/Target/RISCV/RISCVInstrInfo.td @@ -400,6 +400,15 @@ let rd = 0; let imm12 = 1; } + +// This is a de facto standard (as set by GNU binutils) 32-bit unimplemented +// instruction (i.e., it should always trap, if your implementation has invalid +// instruction traps). +def UNIMP : RVInstI<0b001, OPC_SYSTEM, (outs), (ins), "unimp", ""> { + let rs1 = 0; + let rd = 0; + let imm12 = 0b110000000000; +} } // hasSideEffects = 1, mayLoad = 0, mayStore = 0 def CSRRW : CSR_ir<0b001, "csrrw">; Index: lib/Target/RISCV/RISCVInstrInfoC.td =================================================================== --- lib/Target/RISCV/RISCVInstrInfoC.td +++ lib/Target/RISCV/RISCVInstrInfoC.td @@ -517,6 +517,13 @@ let Inst{9-7} = imm{8-6}; } +// The all zeros pattern isn't a valid RISC-V instruction. It's used by GNU +// binutils as 16-bit instruction known to be unimplemented (i.e., trapping). +let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in +def C_UNIMP : RVInst16<(outs), (ins), "c.unimp", "", [], InstFormatOther> { + let Inst{15-0} = 0; +} + } // Predicates = [HasStdExtC] //===----------------------------------------------------------------------===// @@ -680,6 +687,7 @@ def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, 0), (C_MV GPRNoX0:$rs1, GPRNoX0:$rs2)>; def : CompressPat<(EBREAK), (C_EBREAK)>; +def : CompressPat<(UNIMP), (C_UNIMP)>; def : CompressPat<(JALR X1, GPRNoX0:$rs1, 0), (C_JALR GPRNoX0:$rs1)>; def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2), Index: test/MC/RISCV/compress-rv32i.s =================================================================== --- test/MC/RISCV/compress-rv32i.s +++ test/MC/RISCV/compress-rv32i.s @@ -211,3 +211,9 @@ # CHECK-INST: c.swsp zero, 252(sp) # CHECK: # encoding: [0x82,0xdf] sw zero, 252(sp) + +# CHECK-BYTES: 00 00 +# CHECK-ALIAS: unimp +# CHECK-INST: c.unimp +# CHECK: # encoding: [0x00,0x00] +unimp Index: test/MC/RISCV/rv32c-valid.s =================================================================== --- test/MC/RISCV/rv32c-valid.s +++ test/MC/RISCV/rv32c-valid.s @@ -103,3 +103,6 @@ # CHECK-ASM-AND-OBJ: c.lui s0, 1048575 # CHECK-ASM: encoding: [0x7d,0x74] c.lui s0, 0xfffff +# CHECK-ASM-AND-OBJ: c.unimp +# CHECK-ASM: encoding: [0x00,0x00] +c.unimp Index: test/MC/RISCV/rv32i-valid.s =================================================================== --- test/MC/RISCV/rv32i-valid.s +++ test/MC/RISCV/rv32i-valid.s @@ -248,6 +248,9 @@ # CHECK-ASM-AND-OBJ: ebreak # CHECK-ASM: encoding: [0x73,0x00,0x10,0x00] ebreak +# CHECK-ASM-AND-OBJ: unimp +# CHECK-ASM: encoding: [0x73,0x10,0x00,0xc0] +unimp # CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1 # CHECK-ASM: encoding: [0xf3,0x12,0xf3,0xff]