Index: lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- lib/Target/RISCV/RISCVISelLowering.cpp
+++ lib/Target/RISCV/RISCVISelLowering.cpp
@@ -114,7 +114,7 @@
   // TODO: add proper support for the various FMA variants
   // (FMADD.S, FMSUB.S, FNMSUB.S, FNMADD.S).
   ISD::NodeType FPOpToExtend[] = {
-      ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FMA};
+      ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FMA, ISD::FREM};
 
   if (Subtarget.hasStdExtF()) {
     setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
Index: test/CodeGen/RISCV/double-frem.ll
===================================================================
--- /dev/null
+++ test/CodeGen/RISCV/double-frem.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32ID %s
+
+define double @frem_f64(double %a, double %b) nounwind {
+; RV32ID-LABEL: frem_f64:
+; RV32ID:       # %bb.0:
+; RV32ID-NEXT:    addi sp, sp, -16
+; RV32ID-NEXT:    sw ra, 12(sp)
+; RV32ID-NEXT:    call fmod
+; RV32ID-NEXT:    lw ra, 12(sp)
+; RV32ID-NEXT:    addi sp, sp, 16
+; RV32ID-NEXT:    ret
+  %1 = frem double %a, %b
+  ret double %1
+}
Index: test/CodeGen/RISCV/float-frem.ll
===================================================================
--- /dev/null
+++ test/CodeGen/RISCV/float-frem.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32IF %s
+
+define float @frem_f32(float %a, float %b) nounwind {
+; RV32IF-LABEL: frem_f32:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    addi sp, sp, -16
+; RV32IF-NEXT:    sw ra, 12(sp)
+; RV32IF-NEXT:    call fmodf
+; RV32IF-NEXT:    lw ra, 12(sp)
+; RV32IF-NEXT:    addi sp, sp, 16
+; RV32IF-NEXT:    ret
+  %1 = frem float %a, %b
+  ret float %1
+}