Index: lib/CodeGen/MachineInstr.cpp =================================================================== --- lib/CodeGen/MachineInstr.cpp +++ lib/CodeGen/MachineInstr.cpp @@ -933,9 +933,7 @@ unsigned MOReg = MO.getReg(); if (!MOReg) continue; - if (MOReg == Reg || (TRI && TargetRegisterInfo::isPhysicalRegister(MOReg) && - TargetRegisterInfo::isPhysicalRegister(Reg) && - TRI->isSubRegister(MOReg, Reg))) + if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg))) if (!isKill || MO.isKill()) return i; } Index: test/CodeGen/AMDGPU/optimize-if-exec-masking.mir =================================================================== --- test/CodeGen/AMDGPU/optimize-if-exec-masking.mir +++ test/CodeGen/AMDGPU/optimize-if-exec-masking.mir @@ -131,6 +131,26 @@ ret void } + define amdgpu_kernel void @if_and_xor_read_exec_copy_subreg(i32 %z, i32 %v) #0 { + main_body: + %id = call i32 @llvm.amdgcn.workitem.id.x() + %cc = icmp eq i32 %id, 0 + %0 = call { i1, i64 } @llvm.amdgcn.if(i1 %cc) + %1 = extractvalue { i1, i64 } %0, 0 + %2 = extractvalue { i1, i64 } %0, 1 + br i1 %1, label %if, label %end + + if: ; preds = %main_body + %v.if = load volatile i32, i32 addrspace(1)* undef + br label %end + + end: ; preds = %if, %main_body + %r = phi i32 [ 4, %main_body ], [ %v.if, %if ] + call void @llvm.amdgcn.end.cf(i64 %2) + store i32 %r, i32 addrspace(1)* undef + ret void + } + ; Function Attrs: nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() #1 @@ -731,3 +751,61 @@ S_ENDPGM ... +--- +# A read from exec copy subreg prevents optimization +# CHECK-LABEL: name: if_and_xor_read_exec_copy_subreg{{$}} +# CHECK: $sgpr0_sgpr1 = COPY $exec +# CHECK-NEXT: $sgpr4 = S_MOV_B32 $sgpr1 +name: if_and_xor_read_exec_copy_subreg +alignment: 0 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +tracksRegLiveness: true +liveins: + - { reg: '$vgpr0' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +body: | + bb.0.main_body: + liveins: $vgpr0 + + $sgpr0_sgpr1 = COPY $exec + $sgpr4 = S_MOV_B32 $sgpr1 + $vcc = V_CMP_EQ_I32_e64 0, killed $vgpr0, implicit $exec + $vgpr0 = V_MOV_B32_e32 4, implicit $exec + $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc + $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc + $exec = S_MOV_B64_term killed $sgpr2_sgpr3 + SI_MASK_BRANCH %bb.2, implicit $exec + S_BRANCH %bb.1 + + bb.1.if: + liveins: $sgpr0_sgpr1 + + $sgpr7 = S_MOV_B32 61440 + $sgpr6 = S_MOV_B32 -1 + $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `i32 addrspace(1)* undef`) + + bb.2.end: + liveins: $vgpr0, $sgpr0_sgpr1 + + $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc + $sgpr3 = S_MOV_B32 61440 + $sgpr2 = S_MOV_B32 -1 + BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into `i32 addrspace(1)* undef`) + S_ENDPGM +...