Index: include/llvm/MC/MCExpr.h =================================================================== --- include/llvm/MC/MCExpr.h +++ include/llvm/MC/MCExpr.h @@ -250,6 +250,7 @@ VK_PPC_GOT_TLSLD_HI, // symbol@got@tlsld@h VK_PPC_GOT_TLSLD_HA, // symbol@got@tlsld@ha VK_PPC_TLSLD, // symbol@tlsld + VK_PPC_LOCAL, // symbol@local VK_Mips_GPREL, VK_Mips_GOT_CALL, Index: include/llvm/Support/ELF.h =================================================================== --- include/llvm/Support/ELF.h +++ include/llvm/Support/ELF.h @@ -460,6 +460,7 @@ R_PPC_GOT16_HA = 17, R_PPC_PLTREL24 = 18, R_PPC_JMP_SLOT = 21, + R_PPC_LOCAL24PC = 23, R_PPC_REL32 = 26, R_PPC_TLS = 67, R_PPC_DTPMOD32 = 68, Index: lib/MC/MCExpr.cpp =================================================================== --- lib/MC/MCExpr.cpp +++ lib/MC/MCExpr.cpp @@ -252,6 +252,7 @@ case VK_PPC_GOT_TLSLD_HI: return "got@tlsld@h"; case VK_PPC_GOT_TLSLD_HA: return "got@tlsld@ha"; case VK_PPC_TLSLD: return "tlsld"; + case VK_PPC_LOCAL: return "local"; case VK_Mips_GPREL: return "GPREL"; case VK_Mips_GOT_CALL: return "GOT_CALL"; case VK_Mips_GOT16: return "GOT16"; Index: lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp =================================================================== --- lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp +++ lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp @@ -87,6 +87,9 @@ case MCSymbolRefExpr::VK_PLT: Type = ELF::R_PPC_PLTREL24; break; + case MCSymbolRefExpr::VK_PPC_LOCAL: + Type = ELF::R_PPC_LOCAL24PC; + break; } break; case PPC::fixup_ppc_brcond14: Index: lib/Target/PowerPC/PPCAsmPrinter.cpp =================================================================== --- lib/Target/PowerPC/PPCAsmPrinter.cpp +++ lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -323,12 +323,33 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { MCInst TmpInst; bool isPPC64 = Subtarget.isPPC64(); + bool isDarwin = Subtarget.isDarwin(); + const Module *M = MF->getFunction()->getParent(); + PICLevel::Level PL = M->getPICLevel(); // Lower multi-instruction pseudo operations. switch (MI->getOpcode()) { default: break; case TargetOpcode::DBG_VALUE: llvm_unreachable("Should be handled target independently"); + case PPC::MoveGOTtoLR: { + // Transform %LR = MoveGOTtoLR + // Into this: bl _GLOBAL_OFFSET_TABLE_@local-4 + // _GLOBAL_OFFSET_TABLE_@local-4 (instruction preceding + // _GLOBAL_OFFSET_TABLE_) has exactly one instruction: + // blrl + // This will return the pointer to _GLOBAL_OFFSET_TABLE_@local + MCSymbol *GOTSymbol = OutContext.GetOrCreateSymbol(StringRef("_GLOBAL_OFFSET_TABLE_")); + const MCExpr *OffsExpr = + MCBinaryExpr::CreateSub(MCSymbolRefExpr::Create(GOTSymbol, MCSymbolRefExpr::VK_PPC_LOCAL, + OutContext), + MCConstantExpr::Create(4, OutContext), + OutContext); + + // Emit the 'bl'. + EmitToStreamer(OutStreamer, MCInstBuilder(PPC::BL).addExpr(OffsExpr)); + return; + } case PPC::MovePCtoLR: case PPC::MovePCtoLR8: { // Transform %LR = MovePCtoLR @@ -347,10 +368,14 @@ OutStreamer.EmitLabel(PICBase); return; } - case PPC::GetGBRO: { + case PPC::UpdateGBR: { + // Transform %Rd = UpdateGBR(%Rt, %Ri) + // Into: lwz %Rt, .L0$poff - .L0$pb(%Ri) + // add %Rd, %Rt, %Ri // Get the offset from the GOT Base Register to the GOT - LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin()); - MCSymbol *PICOffset = MF->getInfo()->getPICOffsetSymbol(); + LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin); + MCSymbol *PICOffset = + MF->getInfo()->getPICOffsetSymbol(); TmpInst.setOpcode(PPC::LWZ); const MCExpr *Exp = MCSymbolRefExpr::Create(PICOffset, MCSymbolRefExpr::VK_None, OutContext); @@ -358,26 +383,30 @@ MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), MCSymbolRefExpr::VK_None, OutContext); - const MCOperand MO = TmpInst.getOperand(1); - TmpInst.getOperand(1) = MCOperand::CreateExpr(MCBinaryExpr::CreateSub(Exp, - PB, - OutContext)); - TmpInst.addOperand(MO); + const MCOperand TR = TmpInst.getOperand(1); + const MCOperand PICR = TmpInst.getOperand(0); + + // Step 1: lwz %Rt, .L$poff - .L$pb(%Ri) + TmpInst.getOperand(1) = + MCOperand::CreateExpr(MCBinaryExpr::CreateSub(Exp, + PB, + OutContext)); + TmpInst.getOperand(0) = TR; + TmpInst.getOperand(2) = PICR; EmitToStreamer(OutStreamer, TmpInst); - return; - } - case PPC::UpdateGBR: { + // Update the GOT Base Register to point to the GOT. It may be possible to // merge this with the PPC::GetGBRO, doing it all in one step. - LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin()); TmpInst.setOpcode(PPC::ADD4); - TmpInst.addOperand(TmpInst.getOperand(0)); + TmpInst.getOperand(0) = PICR; + TmpInst.getOperand(1) = TR; + TmpInst.getOperand(2) = PICR; EmitToStreamer(OutStreamer, TmpInst); return; } case PPC::LWZtoc: { - // Transform %X3 = LWZtoc , %X2 - LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin()); + // Transform %R3 = LWZtoc , %R2 + LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin); // Change the opcode to LWZ, and the global address operand to be a // reference to the GOT entry we will synthesize later. @@ -394,16 +423,23 @@ else if (MO.isJTI()) MOSymbol = GetJTISymbol(MO.getIndex()); - MCSymbol *TOCEntry = lookUpOrCreateTOCEntry(MOSymbol); - - const MCExpr *Exp = - MCSymbolRefExpr::Create(TOCEntry, MCSymbolRefExpr::VK_None, - OutContext); - const MCExpr *PB = - MCSymbolRefExpr::Create(OutContext.GetOrCreateSymbol(Twine(".L.TOC.")), - OutContext); - Exp = MCBinaryExpr::CreateSub(Exp, PB, OutContext); - TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp); + if (PL == PICLevel::Large) { + MCSymbol *TOCEntry = lookUpOrCreateTOCEntry(MOSymbol); + + const MCExpr *Exp = + MCSymbolRefExpr::Create(TOCEntry, MCSymbolRefExpr::VK_None, + OutContext); + const MCExpr *PB = + MCSymbolRefExpr::Create(OutContext.GetOrCreateSymbol(Twine(".LTOC.")), + OutContext); + Exp = MCBinaryExpr::CreateSub(Exp, PB, OutContext); + TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp); + } else { + const MCExpr *Exp = + MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_GOT, + OutContext); + TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp); + } EmitToStreamer(OutStreamer, TmpInst); return; } @@ -411,7 +447,7 @@ case PPC::LDtocCPT: case PPC::LDtoc: { // Transform %X3 = LDtoc , %X2 - LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin()); + LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin); // Change the opcode to LD, and the global address operand to be a // reference to the TOC entry we will synthesize later. @@ -440,7 +476,7 @@ case PPC::ADDIStocHA: { // Transform %Xd = ADDIStocHA %X2, - LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin()); + LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin); // Change the opcode to ADDIS8. If the global address is external, has // common linkage, is a non-local function address, or is a jump table @@ -482,7 +518,7 @@ } case PPC::LDtocL: { // Transform %Xd = LDtocL , %Xs - LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin()); + LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin); // Change the opcode to LD. If the global address is external, has // common linkage, or is a jump table address, then reference the @@ -519,7 +555,7 @@ } case PPC::ADDItocL: { // Transform %Xd = ADDItocL %Xs, - LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin()); + LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin); // Change the opcode to ADDI8. If the global address is external, then // generate a TOC entry and reference that. Otherwise reference the @@ -570,7 +606,7 @@ case PPC::LDgotTprelL: case PPC::LDgotTprelL32: { // Transform %Xd = LDgotTprelL , %Xs - LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin()); + LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin); // Change the opcode to LD. TmpInst.setOpcode(isPPC64 ? PPC::LD : PPC::LWZ); @@ -853,7 +889,7 @@ } } - LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin()); + LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin); EmitToStreamer(OutStreamer, TmpInst); } @@ -869,16 +905,14 @@ if (Subtarget.isPPC64() || TM.getRelocationModel() != Reloc::PIC_) return AsmPrinter::EmitStartOfAsmFile(M); - // FIXME: The use of .got2 assumes large GOT model (-fPIC), which is not - // optimal for some cases. We should consider supporting small model (-fpic) - // as well in the future. - assert(TM.getCodeModel() != CodeModel::Small && - "Small code model PIC is currently unsupported."); + if (M.getPICLevel() != PICLevel::Large) + return AsmPrinter::EmitStartOfAsmFile(M); + OutStreamer.SwitchSection(OutContext.getELFSection(".got2", ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC, SectionKind::getReadOnly())); - MCSymbol *TOCSym = OutContext.GetOrCreateSymbol(Twine(".L.TOC.")); + MCSymbol *TOCSym = OutContext.GetOrCreateSymbol(Twine(".LTOC.")); MCSymbol *CurrentPos = OutContext.CreateTempSymbol(); OutStreamer.EmitLabel(CurrentPos); @@ -897,7 +931,9 @@ void PPCLinuxAsmPrinter::EmitFunctionEntryLabel() { // linux/ppc32 - Normal entry label. - if (!Subtarget.isPPC64() && TM.getRelocationModel() != Reloc::PIC_) + if (!Subtarget.isPPC64() && + (TM.getRelocationModel() != Reloc::PIC_ || + MF->getFunction()->getParent()->getPICLevel() != PICLevel::Large)) return AsmPrinter::EmitFunctionEntryLabel(); if (!Subtarget.isPPC64()) { @@ -909,7 +945,7 @@ const MCExpr *OffsExpr = MCBinaryExpr::CreateSub( - MCSymbolRefExpr::Create(OutContext.GetOrCreateSymbol(Twine(".L.TOC.")), + MCSymbolRefExpr::Create(OutContext.GetOrCreateSymbol(Twine(".LTOC.")), OutContext), MCSymbolRefExpr::Create(PICBase, OutContext), OutContext); Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp =================================================================== --- lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -27,6 +27,7 @@ #include "llvm/IR/GlobalValue.h" #include "llvm/IR/GlobalVariable.h" #include "llvm/IR/Intrinsics.h" +#include "llvm/IR/Module.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" @@ -273,6 +274,7 @@ // Insert the set of GlobalBaseReg into the first MBB of the function MachineBasicBlock &FirstMBB = MF->front(); MachineBasicBlock::iterator MBBI = FirstMBB.begin(); + const Module *M = MF->getFunction()->getParent(); DebugLoc dl; if (PPCLowering->getPointerTy() == MVT::i32) { @@ -281,14 +283,18 @@ else GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::GPRC_NOR0RegClass); - BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR)); + if (PPCSubTarget->isTargetELF() && + M->getPICLevel() == PICLevel::Small) + BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR)); + else + BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR)); BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); - if (PPCSubTarget->isTargetELF()) { + if (PPCSubTarget->isTargetELF() && + M->getPICLevel() == PICLevel::Large) { unsigned TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); BuildMI(FirstMBB, MBBI, dl, - TII.get(PPC::GetGBRO), TempReg).addReg(GlobalBaseReg); - BuildMI(FirstMBB, MBBI, dl, - TII.get(PPC::UpdateGBR)).addReg(GlobalBaseReg).addReg(TempReg); + TII.get(PPC::UpdateGBR)).addReg(GlobalBaseReg) + .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg); MF->getInfo()->setUsesPICBase(true); } } else { @@ -1436,13 +1442,13 @@ return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain); } case PPCISD::TOC_ENTRY: { + assert ((PPCSubTarget->isPPC64() || PPCSubTarget->isSVR4ABI()) && + "Only supported for 64-bit ABI and 32-bit SVR4"); if (PPCSubTarget->isSVR4ABI() && !PPCSubTarget->isPPC64()) { SDValue GA = N->getOperand(0); return CurDAG->getMachineNode(PPC::LWZtoc, dl, MVT::i32, GA, N->getOperand(1)); } - assert (PPCSubTarget->isPPC64() && - "Only supported for 64-bit ABI and 32-bit SVR4"); // For medium and large code model, we generate two instructions as // described below. Otherwise we allow SelectCodeCommon to handle this, Index: lib/Target/PowerPC/PPCISelLowering.cpp =================================================================== --- lib/Target/PowerPC/PPCISelLowering.cpp +++ lib/Target/PowerPC/PPCISelLowering.cpp @@ -1660,6 +1660,8 @@ const GlobalValue *GV = GA->getGlobal(); EVT PtrVT = getPointerTy(); bool is64bit = Subtarget.isPPC64(); + const Module *M = DAG.getMachineFunction().getFunction()->getParent(); + PICLevel::Level picLevel = M->getPICLevel(); TLSModel::Model Model = getTargetMachine().getTLSModel(GV); @@ -1698,7 +1700,10 @@ GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT, GOTReg, TGA); } else { - GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT); + if (picLevel == PICLevel::Large) + GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT); + else + GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT); } SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT, GOTPtr, TGA); @@ -1728,7 +1733,10 @@ GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT, GOTReg, TGA); } else { - GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT); + if (picLevel == PICLevel::Large) + GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT); + else + GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT); } SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT, GOTPtr, TGA); Index: lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- lib/Target/PowerPC/PPCInstrInfo.td +++ lib/Target/PowerPC/PPCInstrInfo.td @@ -1027,6 +1027,9 @@ let Defs = [LR] in def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>, PPC970_Unit_BRU; +let Defs = [LR] in + def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>, + PPC970_Unit_BRU; let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { let isBarrier = 1 in { @@ -2504,15 +2507,13 @@ tglobaltlsaddr:$disp))]>; // Support for Position-independent code -def LWZtoc: Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), - "#LWZtoc", - [(set i32:$rD, - (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; +def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), + "#LWZtoc", + [(set i32:$rD, + (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; // Get Global (GOT) Base Register offset, from the word immediately preceding // the function label. -def GetGBRO: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#GetGBRO", []>; -// Update the Global(GOT) Base Register with the above offset. -def UpdateGBR: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>; +def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>; // Standard shifts. These are represented separately from the real shifts above Index: test/CodeGen/PowerPC/ppc32-pic.ll =================================================================== --- test/CodeGen/PowerPC/ppc32-pic.ll +++ test/CodeGen/PowerPC/ppc32-pic.ll @@ -1,21 +1,27 @@ -; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -relocation-model=pic | FileCheck %s -@foobar = common global i32 0, align 4 +; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -relocation-model=pic -pic-level=small | FileCheck -check-prefix=SMALL-BSS %s +; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -relocation-model=pic -pic-level=large | FileCheck -check-prefix=LARGE-BSS %s +@bar = common global i32 0, align 4 define i32 @foo() { entry: - %0 = load i32* @foobar, align 4 + %0 = load i32* @bar, align 4 ret i32 %0 } -; CHECK: [[POFF:\.L[0-9]+\$poff]]: -; CHECK-NEXT: .long .L.TOC.-[[PB:\.L[0-9]+\$pb]] -; CHECK-NEXT: foo: -; CHECK: bl [[PB]] -; CHECK-NEXT: [[PB]]: -; CHECK: mflr 30 -; CHECK: lwz [[REG:[0-9]+]], [[POFF]]-[[PB]](30) -; CHECK-NEXT: add 30, [[REG]], 30 -; CHECK: lwz [[VREG:[0-9]+]], [[VREF:\.LC[0-9]+]]-.L.TOC.(30) -; CHECK: lwz {{[0-9]+}}, 0([[VREG]]) -; CHECK: [[VREF]]: -; CHECK-NEXT: .long foobar +; SMALL-BSS-LABEL:foo: +; SMALL-BSS: bl _GLOBAL_OFFSET_TABLE_@local-4 +; SMALL-BSS: mflr 30 +; SMALL-BSS: lwz [[VREG:[0-9]+]], bar@GOT(30) +; SMALL-BSS: lwz {{[0-9]+}}, 0([[VREG]]) +; LARGE-BSS: [[POFF:\.L[0-9]+\$poff]]: +; LARGE-BSS-NEXT: .long .LTOC.-[[PB:\.L[0-9]+\$pb]] +; LARGE-BSS-NEXT: foo: +; LARGE-BSS: bl [[PB]] +; LARGE-BSS-NEXT: [[PB]]: +; LARGE-BSS: mflr 30 +; LARGE-BSS: lwz [[REG:[0-9]+]], [[POFF]]-[[PB]](30) +; LARGE-BSS-NEXT: add 30, [[REG]], 30 +; LARGE-BSS: lwz [[VREG:[0-9]+]], [[VREF:\.LC[0-9]+]]-.LTOC.(30) +; LARGE-BSS: lwz {{[0-9]+}}, 0([[VREG]]) +; LARGE-BSS: [[VREF]]: +; LARGE-BSS-NEXT: .long bar Index: test/CodeGen/PowerPC/sections.ll =================================================================== --- test/CodeGen/PowerPC/sections.ll +++ test/CodeGen/PowerPC/sections.ll @@ -1,12 +1,14 @@ ; Test to make sure that bss sections are printed with '.section' directive. ; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s -; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -relocation-model=pic | FileCheck %s -check-prefix=PIC +; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -relocation-model=pic -pic-level=small | FileCheck %s -check-prefix=PIC +; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -relocation-model=pic -pic-level=large | FileCheck %s -check-prefix=LARGE-PIC @A = global i32 0 ; CHECK: .section .bss,"aw",@nobits ; CHECK: .globl A - -; PIC: .section .got2,"aw",@progbits ; PIC: .section .bss,"aw",@nobits ; PIC: .globl A +; LARGE-PIC: .section .got2,"aw",@progbits +; LARGE-PIC: .section .bss,"aw",@nobits +; LARGE-PIC: .globl A Index: test/CodeGen/PowerPC/tls-pic.ll =================================================================== --- test/CodeGen/PowerPC/tls-pic.ll +++ test/CodeGen/PowerPC/tls-pic.ll @@ -25,7 +25,7 @@ ; OPT0: addis [[REG2:[0-9]+]], 3, a@dtprel@ha ; OPT0-NEXT: addi {{[0-9]+}}, [[REG2]], a@dtprel@l ; OPT0-32-LABEL: main -; OPT0-32: addi {{[0-9]+}}, {{[0-9]+}}, a@got@tlsld +; OPT0-32: addi 3, {{[0-9]+}}, a@got@tlsld ; OPT0-32: bl __tls_get_addr(a@tlsld)@PLT ; OPT0-32: addis [[REG:[0-9]+]], 3, a@dtprel@ha ; OPT0-32-NEXT: addi {{[0-9]+}}, [[REG]], a@dtprel@l