Index: lib/Target/AMDGPU/SIISelLowering.cpp =================================================================== --- lib/Target/AMDGPU/SIISelLowering.cpp +++ lib/Target/AMDGPU/SIISelLowering.cpp @@ -4727,9 +4727,11 @@ // Check for 16 bit addresses and pack if true. unsigned DimIdx = AddrIdx + BaseOpcode->NumExtraArgs; MVT VAddrVT = Op.getOperand(DimIdx).getSimpleValueType(); - if (VAddrVT.getScalarType() == MVT::f16 && + const MVT VAddrScalarVT = VAddrVT.getScalarType(); + if (((VAddrScalarVT == MVT::f16) || (VAddrScalarVT == MVT::i16)) && ST->hasFeature(AMDGPU::FeatureR128A16)) { IsA16 = true; + const MVT VectorVT = VAddrScalarVT == MVT::f16 ? MVT::v2f16 : MVT::v2i16; for (unsigned i = AddrIdx; i < (AddrIdx + NumMIVAddrs); ++i) { SDValue AddrLo, AddrHi; // Push back extra arguments. @@ -4748,7 +4750,7 @@ AddrHi = Op.getOperand(i + 1); i++; } - AddrLo = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f16, + AddrLo = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VectorVT, {AddrLo, AddrHi}); AddrLo = DAG.getBitcast(MVT::i32, AddrLo); } Index: test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll =================================================================== --- /dev/null +++ test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll @@ -0,0 +1,128 @@ +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s + +; GCN-LABEL: {{^}}load.f32.1d: +; GCN: image_load v[0:1], v0, s[0:7] dmask:0x1 unorm a16 d16 +define amdgpu_ps <4 x half> @load.f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %v = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32 1, i16 %x, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x half> %v +} + +; GCN-LABEL: {{^}}load.v2f32.1d: +; GCN: image_load v[0:1], v0, s[0:7] dmask:0x3 unorm a16 d16 +define amdgpu_ps <4 x half> @load.v2f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %v = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32 3, i16 %x, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x half> %v +} + +; GCN-LABEL: {{^}}load.v3f32.1d: +; GCN: image_load v[0:1], v0, s[0:7] dmask:0x7 unorm a16 d16 +define amdgpu_ps <4 x half> @load.v3f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %v = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32 7, i16 %x, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x half> %v +} + +; GCN-LABEL: {{^}}load.v4f32.1d: +; GCN: image_load v[0:1], v0, s[0:7] dmask:0xf unorm a16 d16 +define amdgpu_ps <4 x half> @load.v4f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %v = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32 15, i16 %x, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x half> %v +} + +; GCN-LABEL: {{^}}load.f32.2d: +; GCN: image_load v[0:1], v0, s[0:7] dmask:0x1 unorm a16 d16 +define amdgpu_ps <4 x half> @load.f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %y = extractelement <2 x i16> %coords, i32 1 + %v = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32 1, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x half> %v +} + +; GCN-LABEL: {{^}}load.v2f32.2d: +; GCN: image_load v[0:1], v0, s[0:7] dmask:0x3 unorm a16 d16 +define amdgpu_ps <4 x half> @load.v2f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %y = extractelement <2 x i16> %coords, i32 1 + %v = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32 3, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x half> %v +} + +; GCN-LABEL: {{^}}load.v3f32.2d: +; GCN: image_load v[0:1], v0, s[0:7] dmask:0x7 unorm a16 d16 +define amdgpu_ps <4 x half> @load.v3f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %y = extractelement <2 x i16> %coords, i32 1 + %v = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32 7, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x half> %v +} + +; GCN-LABEL: {{^}}load.v4f32.2d: +; GCN: image_load v[0:1], v0, s[0:7] dmask:0xf unorm a16 d16 +define amdgpu_ps <4 x half> @load.v4f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %y = extractelement <2 x i16> %coords, i32 1 + %v = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32 15, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x half> %v +} + +; GCN-LABEL: {{^}}load.f32.3d: +; GCN: image_load v[0:1], v[0:1], s[0:7] dmask:0x1 unorm a16 d16 +define amdgpu_ps <4 x half> @load.f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) { +main_body: + %x = extractelement <2 x i16> %coords_lo, i32 0 + %y = extractelement <2 x i16> %coords_lo, i32 1 + %z = extractelement <2 x i16> %coords_hi, i32 0 + %v = call <4 x half> @llvm.amdgcn.image.load.3d.v4f16.i16(i32 1, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x half> %v +} + +; GCN-LABEL: {{^}}load.v2f32.3d: +; GCN: image_load v[0:1], v[0:1], s[0:7] dmask:0x3 unorm a16 d16 +define amdgpu_ps <4 x half> @load.v2f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) { +main_body: + %x = extractelement <2 x i16> %coords_lo, i32 0 + %y = extractelement <2 x i16> %coords_lo, i32 1 + %z = extractelement <2 x i16> %coords_hi, i32 0 + %v = call <4 x half> @llvm.amdgcn.image.load.3d.v4f16.i16(i32 3, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x half> %v +} + +; GCN-LABEL: {{^}}load.v3f32.3d: +; GCN: image_load v[0:1], v[0:1], s[0:7] dmask:0x7 unorm a16 d16 +define amdgpu_ps <4 x half> @load.v3f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) { +main_body: + %x = extractelement <2 x i16> %coords_lo, i32 0 + %y = extractelement <2 x i16> %coords_lo, i32 1 + %z = extractelement <2 x i16> %coords_hi, i32 0 + %v = call <4 x half> @llvm.amdgcn.image.load.3d.v4f16.i16(i32 7, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x half> %v +} + +; GCN-LABEL: {{^}}load.v4f32.3d: +; GCN: image_load v[0:1], v[0:1], s[0:7] dmask:0xf unorm a16 d16 +define amdgpu_ps <4 x half> @load.v4f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) { +main_body: + %x = extractelement <2 x i16> %coords_lo, i32 0 + %y = extractelement <2 x i16> %coords_lo, i32 1 + %z = extractelement <2 x i16> %coords_hi, i32 0 + %v = call <4 x half> @llvm.amdgcn.image.load.3d.v4f16.i16(i32 15, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x half> %v +} + +declare <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32, i16, <8 x i32>, i32, i32) #2 +declare <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32, i16, i16, <8 x i32>, i32, i32) #2 +declare <4 x half> @llvm.amdgcn.image.load.3d.v4f16.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #2 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readonly } Index: test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll =================================================================== --- /dev/null +++ test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll @@ -0,0 +1,128 @@ +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s + +; GCN-LABEL: {{^}}load.f32.1d: +; GCN: image_load v[0:3], v0, s[0:7] dmask:0x1 unorm a16 +define amdgpu_ps <4 x float> @load.f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 1, i16 %x, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x float> %v +} + +; GCN-LABEL: {{^}}load.v2f32.1d: +; GCN: image_load v[0:3], v0, s[0:7] dmask:0x3 unorm a16 +define amdgpu_ps <4 x float> @load.v2f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 3, i16 %x, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x float> %v +} + +; GCN-LABEL: {{^}}load.v3f32.1d: +; GCN: image_load v[0:3], v0, s[0:7] dmask:0x7 unorm a16 +define amdgpu_ps <4 x float> @load.v3f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 7, i16 %x, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x float> %v +} + +; GCN-LABEL: {{^}}load.v4f32.1d: +; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm a16 +define amdgpu_ps <4 x float> @load.v4f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %x, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x float> %v +} + +; GCN-LABEL: {{^}}load.f32.2d: +; GCN: image_load v[0:3], v0, s[0:7] dmask:0x1 unorm a16 +define amdgpu_ps <4 x float> @load.f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %y = extractelement <2 x i16> %coords, i32 1 + %v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 1, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x float> %v +} + +; GCN-LABEL: {{^}}load.v2f32.2d: +; GCN: image_load v[0:3], v0, s[0:7] dmask:0x3 unorm a16 +define amdgpu_ps <4 x float> @load.v2f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %y = extractelement <2 x i16> %coords, i32 1 + %v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 3, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x float> %v +} + +; GCN-LABEL: {{^}}load.v3f32.2d: +; GCN: image_load v[0:3], v0, s[0:7] dmask:0x7 unorm a16 +define amdgpu_ps <4 x float> @load.v3f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %y = extractelement <2 x i16> %coords, i32 1 + %v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 7, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x float> %v +} + +; GCN-LABEL: {{^}}load.v4f32.2d: +; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm a16 +define amdgpu_ps <4 x float> @load.v4f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %y = extractelement <2 x i16> %coords, i32 1 + %v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 15, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x float> %v +} + +; GCN-LABEL: {{^}}load.f32.3d: +; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0x1 unorm a16 +define amdgpu_ps <4 x float> @load.f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) { +main_body: + %x = extractelement <2 x i16> %coords_lo, i32 0 + %y = extractelement <2 x i16> %coords_lo, i32 1 + %z = extractelement <2 x i16> %coords_hi, i32 0 + %v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 1, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x float> %v +} + +; GCN-LABEL: {{^}}load.v2f32.3d: +; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0x3 unorm a16 +define amdgpu_ps <4 x float> @load.v2f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) { +main_body: + %x = extractelement <2 x i16> %coords_lo, i32 0 + %y = extractelement <2 x i16> %coords_lo, i32 1 + %z = extractelement <2 x i16> %coords_hi, i32 0 + %v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 3, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x float> %v +} + +; GCN-LABEL: {{^}}load.v3f32.3d: +; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0x7 unorm a16 +define amdgpu_ps <4 x float> @load.v3f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) { +main_body: + %x = extractelement <2 x i16> %coords_lo, i32 0 + %y = extractelement <2 x i16> %coords_lo, i32 1 + %z = extractelement <2 x i16> %coords_hi, i32 0 + %v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 7, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x float> %v +} + +; GCN-LABEL: {{^}}load.v4f32.3d: +; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 +define amdgpu_ps <4 x float> @load.v4f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) { +main_body: + %x = extractelement <2 x i16> %coords_lo, i32 0 + %y = extractelement <2 x i16> %coords_lo, i32 1 + %z = extractelement <2 x i16> %coords_hi, i32 0 + %v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 15, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x float> %v +} + +declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2 +declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32, i16, i16, <8 x i32>, i32, i32) #2 +declare <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #2 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readonly } Index: test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll =================================================================== --- /dev/null +++ test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll @@ -0,0 +1,140 @@ +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s + +; GCN-LABEL: {{^}}store.f32.1d: +; GCN: image_store v[1:2], v0, s[0:7] dmask:0x1 unorm a16 d16 +define amdgpu_ps void @store.f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %bitcast = bitcast <2 x i32> %val to <4 x half> + call void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half> %bitcast, i32 1, i16 %x, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +; GCN-LABEL: {{^}}store.v2f32.1d: +; GCN: image_store v[1:2], v0, s[0:7] dmask:0x3 unorm a16 d16 +define amdgpu_ps void @store.v2f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %bitcast = bitcast <2 x i32> %val to <4 x half> + call void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half> %bitcast, i32 3, i16 %x, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +; GCN-LABEL: {{^}}store.v3f32.1d: +; GCN: image_store v[1:2], v0, s[0:7] dmask:0x7 unorm a16 d16 +define amdgpu_ps void @store.v3f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %bitcast = bitcast <2 x i32> %val to <4 x half> + call void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half> %bitcast, i32 7, i16 %x, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +; GCN-LABEL: {{^}}store.v4f32.1d: +; GCN: image_store v[1:2], v0, s[0:7] dmask:0xf unorm a16 d16 +define amdgpu_ps void @store.v4f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %bitcast = bitcast <2 x i32> %val to <4 x half> + call void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half> %bitcast, i32 15, i16 %x, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +; GCN-LABEL: {{^}}store.f32.2d: +; GCN: image_store v[1:2], v0, s[0:7] dmask:0x1 unorm a16 d16 +define amdgpu_ps void @store.f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %y = extractelement <2 x i16> %coords, i32 1 + %bitcast = bitcast <2 x i32> %val to <4 x half> + call void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half> %bitcast, i32 1, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +; GCN-LABEL: {{^}}store.v2f32.2d: +; GCN: image_store v[1:2], v0, s[0:7] dmask:0x3 unorm a16 d16 +define amdgpu_ps void @store.v2f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %y = extractelement <2 x i16> %coords, i32 1 + %bitcast = bitcast <2 x i32> %val to <4 x half> + call void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half> %bitcast, i32 3, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +; GCN-LABEL: {{^}}store.v3f32.2d: +; GCN: image_store v[1:2], v0, s[0:7] dmask:0x7 unorm a16 d16 +define amdgpu_ps void @store.v3f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %y = extractelement <2 x i16> %coords, i32 1 + %bitcast = bitcast <2 x i32> %val to <4 x half> + call void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half> %bitcast, i32 7, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +; GCN-LABEL: {{^}}store.v4f32.2d: +; GCN: image_store v[1:2], v0, s[0:7] dmask:0xf unorm a16 d16 +define amdgpu_ps void @store.v4f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %y = extractelement <2 x i16> %coords, i32 1 + %bitcast = bitcast <2 x i32> %val to <4 x half> + call void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half> %bitcast, i32 15, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +; GCN-LABEL: {{^}}store.f32.3d: +; GCN: image_store v[2:3], v[0:1], s[0:7] dmask:0x1 unorm a16 d16 +define amdgpu_ps void @store.f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <2 x i32> %val) { +main_body: + %x = extractelement <2 x i16> %coords_lo, i32 0 + %y = extractelement <2 x i16> %coords_lo, i32 1 + %z = extractelement <2 x i16> %coords_hi, i32 0 + %bitcast = bitcast <2 x i32> %val to <4 x half> + call void @llvm.amdgcn.image.store.3d.v4f16.i16(<4 x half> %bitcast, i32 1, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +; GCN-LABEL: {{^}}store.v2f32.3d: +; GCN: image_store v[2:3], v[0:1], s[0:7] dmask:0x3 unorm a16 d16 +define amdgpu_ps void @store.v2f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <2 x i32> %val) { +main_body: + %x = extractelement <2 x i16> %coords_lo, i32 0 + %y = extractelement <2 x i16> %coords_lo, i32 1 + %z = extractelement <2 x i16> %coords_hi, i32 0 + %bitcast = bitcast <2 x i32> %val to <4 x half> + call void @llvm.amdgcn.image.store.3d.v4f16.i16(<4 x half> %bitcast, i32 3, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +; GCN-LABEL: {{^}}store.v3f32.3d: +; GCN: image_store v[2:3], v[0:1], s[0:7] dmask:0x7 unorm a16 d16 +define amdgpu_ps void @store.v3f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <2 x i32> %val) { +main_body: + %x = extractelement <2 x i16> %coords_lo, i32 0 + %y = extractelement <2 x i16> %coords_lo, i32 1 + %z = extractelement <2 x i16> %coords_hi, i32 0 + %bitcast = bitcast <2 x i32> %val to <4 x half> + call void @llvm.amdgcn.image.store.3d.v4f16.i16(<4 x half> %bitcast, i32 7, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +; GCN-LABEL: {{^}}store.v4f32.3d: +; GCN: image_store v[2:3], v[0:1], s[0:7] dmask:0xf unorm a16 d16 +define amdgpu_ps void @store.v4f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <2 x i32> %val) { +main_body: + %x = extractelement <2 x i16> %coords_lo, i32 0 + %y = extractelement <2 x i16> %coords_lo, i32 1 + %z = extractelement <2 x i16> %coords_hi, i32 0 + %bitcast = bitcast <2 x i32> %val to <4 x half> + call void @llvm.amdgcn.image.store.3d.v4f16.i16(<4 x half> %bitcast, i32 15, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +declare void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half>, i32, i16, <8 x i32>, i32, i32) #2 +declare void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half>, i32, i16, i16, <8 x i32>, i32, i32) #2 +declare void @llvm.amdgcn.image.store.3d.v4f16.i16(<4 x half>, i32, i16, i16, i16, <8 x i32>, i32, i32) #2 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readonly } Index: test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll =================================================================== --- /dev/null +++ test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll @@ -0,0 +1,128 @@ +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s + +; GCN-LABEL: {{^}}store.f32.1d: +; GCN: image_store v[1:4], v0, s[0:7] dmask:0x1 unorm a16 +define amdgpu_ps void @store.f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %val, i32 1, i16 %x, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +; GCN-LABEL: {{^}}store.v2f32.1d: +; GCN: image_store v[1:4], v0, s[0:7] dmask:0x3 unorm a16 +define amdgpu_ps void @store.v2f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %val, i32 3, i16 %x, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +; GCN-LABEL: {{^}}store.v3f32.1d: +; GCN: image_store v[1:4], v0, s[0:7] dmask:0x7 unorm a16 +define amdgpu_ps void @store.v3f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %val, i32 7, i16 %x, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +; GCN-LABEL: {{^}}store.v4f32.1d: +; GCN: image_store v[1:4], v0, s[0:7] dmask:0xf unorm a16 +define amdgpu_ps void @store.v4f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %val, i32 15, i16 %x, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +; GCN-LABEL: {{^}}store.f32.2d: +; GCN: image_store v[1:4], v0, s[0:7] dmask:0x1 unorm a16 +define amdgpu_ps void @store.f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %y = extractelement <2 x i16> %coords, i32 1 + call void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float> %val, i32 1, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +; GCN-LABEL: {{^}}store.v2f32.2d: +; GCN: image_store v[1:4], v0, s[0:7] dmask:0x3 unorm a16 +define amdgpu_ps void @store.v2f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %y = extractelement <2 x i16> %coords, i32 1 + call void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float> %val, i32 3, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +; GCN-LABEL: {{^}}store.v3f32.2d: +; GCN: image_store v[1:4], v0, s[0:7] dmask:0x7 unorm a16 +define amdgpu_ps void @store.v3f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %y = extractelement <2 x i16> %coords, i32 1 + call void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float> %val, i32 7, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +; GCN-LABEL: {{^}}store.v4f32.2d: +; GCN: image_store v[1:4], v0, s[0:7] dmask:0xf unorm a16 +define amdgpu_ps void @store.v4f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) { +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %y = extractelement <2 x i16> %coords, i32 1 + call void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float> %val, i32 15, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +; GCN-LABEL: {{^}}store.f32.3d: +; GCN: image_store v[2:5], v[0:1], s[0:7] dmask:0x1 unorm a16 +define amdgpu_ps void @store.f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <4 x float> %val) { +main_body: + %x = extractelement <2 x i16> %coords_lo, i32 0 + %y = extractelement <2 x i16> %coords_lo, i32 1 + %z = extractelement <2 x i16> %coords_hi, i32 0 + call void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float> %val, i32 1, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +; GCN-LABEL: {{^}}store.v2f32.3d: +; GCN: image_store v[2:5], v[0:1], s[0:7] dmask:0x3 unorm a16 +define amdgpu_ps void @store.v2f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <4 x float> %val) { +main_body: + %x = extractelement <2 x i16> %coords_lo, i32 0 + %y = extractelement <2 x i16> %coords_lo, i32 1 + %z = extractelement <2 x i16> %coords_hi, i32 0 + call void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float> %val, i32 3, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +; GCN-LABEL: {{^}}store.v3f32.3d: +; GCN: image_store v[2:5], v[0:1], s[0:7] dmask:0x7 unorm a16 +define amdgpu_ps void @store.v3f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <4 x float> %val) { +main_body: + %x = extractelement <2 x i16> %coords_lo, i32 0 + %y = extractelement <2 x i16> %coords_lo, i32 1 + %z = extractelement <2 x i16> %coords_hi, i32 0 + call void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float> %val, i32 7, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +; GCN-LABEL: {{^}}store.v4f32.3d: +; GCN: image_store v[2:5], v[0:1], s[0:7] dmask:0xf unorm a16 +define amdgpu_ps void @store.v4f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <4 x float> %val) { +main_body: + %x = extractelement <2 x i16> %coords_lo, i32 0 + %y = extractelement <2 x i16> %coords_lo, i32 1 + %z = extractelement <2 x i16> %coords_hi, i32 0 + call void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float> %val, i32 15, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +declare void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float>, i32, i16, <8 x i32>, i32, i32) #2 +declare void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float>, i32, i16, i16, <8 x i32>, i32, i32) #2 +declare void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #2 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readonly } Index: test/MC/AMDGPU/mimg.s =================================================================== --- test/MC/AMDGPU/mimg.s +++ test/MC/AMDGPU/mimg.s @@ -157,6 +157,84 @@ // GFX8_1: image_load v[5:7], v[1:4], s[8:15] dmask:0xf tfe d16 ; encoding: [0x00,0x0f,0x01,0xf0,0x01,0x05,0x02,0x80] // GFX9: image_load v[5:7], v[1:4], s[8:15] dmask:0xf tfe d16 ; encoding: [0x00,0x0f,0x01,0xf0,0x01,0x05,0x02,0x80] +//===----------------------------------------------------------------------===// +// Image Load/Store: a16 +//===----------------------------------------------------------------------===// + +image_load v5, v[1:2], s[8:15] unorm a16 +// GFX9: image_load v5, v[1:2], s[8:15] unorm a16 ; encoding: [0x00,0x90,0x00,0xf0,0x01,0x05,0x02,0x00] +// NOSICI: error: a16 modifier is not supported on this GPU +// NOVI: error: a16 modifier is not supported on this GPU + +image_load v[5:6], v[1:2], s[8:15] dmask:0x3 unorm a16 +// GFX9: image_load v[5:6], v[1:2], s[8:15] dmask:0x3 unorm a16 ; encoding: [0x00,0x93,0x00,0xf0,0x01,0x05,0x02,0x00] +// NOSICI: error: a16 modifier is not supported on this GPU +// NOVI: error: a16 modifier is not supported on this GPU + +image_load v[5:7], v[1:2], s[8:15] dmask:0x7 unorm a16 +// GFX9: image_load v[5:7], v[1:2], s[8:15] dmask:0x7 unorm a16 ; encoding: [0x00,0x97,0x00,0xf0,0x01,0x05,0x02,0x00] +// NOSICI: error: a16 modifier is not supported on this GPU +// NOVI: error: a16 modifier is not supported on this GPU + +image_load v[5:8], v[1:2], s[8:15] dmask:0xf unorm a16 +// GFX9: image_load v[5:8], v[1:2], s[8:15] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x00,0xf0,0x01,0x05,0x02,0x00] +// NOSICI: error: a16 modifier is not supported on this GPU +// NOVI: error: a16 modifier is not supported on this GPU + +image_store v5, v[1:2], s[8:15] unorm a16 +// GFX9: image_store v5, v[1:2], s[8:15] unorm a16 ; encoding: [0x00,0x90,0x20,0xf0,0x01,0x05,0x02,0x00] +// NOSICI: error: a16 modifier is not supported on this GPU +// NOVI: error: a16 modifier is not supported on this GPU + +image_store v[5:6], v[1:2], s[8:15] dmask:0x3 unorm a16 +// GFX9: image_store v[5:6], v[1:2], s[8:15] dmask:0x3 unorm a16 ; encoding: [0x00,0x93,0x20,0xf0,0x01,0x05,0x02,0x00] +// NOSICI: error: a16 modifier is not supported on this GPU +// NOVI: error: a16 modifier is not supported on this GPU + +image_store v[5:7], v[1:2], s[8:15] dmask:0x7 unorm a16 +// GFX9: image_store v[5:7], v[1:2], s[8:15] dmask:0x7 unorm a16 ; encoding: [0x00,0x97,0x20,0xf0,0x01,0x05,0x02,0x00] +// NOSICI: error: a16 modifier is not supported on this GPU +// NOVI: error: a16 modifier is not supported on this GPU + +image_store v[5:8], v[1:2], s[8:15] dmask:0xf unorm a16 +// GFX9: image_store v[5:8], v[1:2], s[8:15] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x20,0xf0,0x01,0x05,0x02,0x00] +// NOSICI: error: a16 modifier is not supported on this GPU +// NOVI: error: a16 modifier is not supported on this GPU + +/===----------------------------------------------------------------------===// +// Image Load/Store: a16 & d16 +//===----------------------------------------------------------------------===// + +image_load v5, v[1:2], s[8:15] dmask:0x3 unorm a16 d16 +// GFX9: image_load v5, v[1:2], s[8:15] dmask:0x3 unorm a16 d16 ; encoding: [0x00,0x93,0x00,0xf0,0x01,0x05,0x02,0x80] +// NOSICI: error: a16 modifier is not supported on this GPU +// NOVI: error: a16 modifier is not supported on this GPU + +image_load v[5:6], v[1:2], s[8:15] dmask:0x7 unorm a16 d16 +// GFX9: image_load v[5:6], v[1:2], s[8:15] dmask:0x7 unorm a16 d16 ; encoding: [0x00,0x97,0x00,0xf0,0x01,0x05,0x02,0x80] +// NOSICI: error: a16 modifier is not supported on this GPU +// NOVI: error: a16 modifier is not supported on this GPU + +image_load v[5:6], v[1:2], s[8:15] dmask:0xf unorm a16 d16 +// GFX9: image_load v[5:6], v[1:2], s[8:15] dmask:0xf unorm a16 d16 ; encoding: [0x00,0x9f,0x00,0xf0,0x01,0x05,0x02,0x80] +// NOSICI: error: a16 modifier is not supported on this GPU +// NOVI: error: a16 modifier is not supported on this GPU + +image_store v5, v[1:2], s[8:15] dmask:0x3 unorm a16 d16 +// GFX9: image_store v5, v[1:2], s[8:15] dmask:0x3 unorm a16 d16 ; encoding: [0x00,0x93,0x20,0xf0,0x01,0x05,0x02,0x80] +// NOSICI: error: a16 modifier is not supported on this GPU +// NOVI: error: a16 modifier is not supported on this GPU + +image_store v[5:6], v[1:2], s[8:15] dmask:0x7 unorm a16 d16 +// GFX9: image_store v[5:6], v[1:2], s[8:15] dmask:0x7 unorm a16 d16 ; encoding: [0x00,0x97,0x20,0xf0,0x01,0x05,0x02,0x80] +// NOSICI: error: a16 modifier is not supported on this GPU +// NOVI: error: a16 modifier is not supported on this GPU + +image_store v[5:6], v[1:2], s[8:15] dmask:0xf unorm a16 d16 +// GFX9: image_store v[5:6], v[1:2], s[8:15] dmask:0xf unorm a16 d16 ; encoding: [0x00,0x9f,0x20,0xf0,0x01,0x05,0x02,0x80] +// NOSICI: error: a16 modifier is not supported on this GPU +// NOVI: error: a16 modifier is not supported on this GPU + //===----------------------------------------------------------------------===// // Image Load/Store: PCK variants //===----------------------------------------------------------------------===// @@ -193,6 +271,11 @@ // NOVI: error: invalid operand for instruction // NOGFX9: error: invalid operand for instruction +image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 a16 +// GFX9: image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 a16 ; encoding: [0x00,0x81,0x10,0xf0,0x01,0x05,0x02,0x00] +// NOSICI: error: a16 modifier is not supported on this GPU +// NOVI: error: a16 modifier is not supported on this GPU + image_store_mip_pck v252, v2, s[12:19] dmask:0x1 unorm // GCN: image_store_mip_pck v252, v2, s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x2c,0xf0,0x02,0xfc,0x03,0x00] @@ -216,6 +299,11 @@ // NOVI: error: invalid operand for instruction // NOGFX9: error: invalid operand for instruction +image_store_mip_pck v252, v[2:3], s[12:19] dmask:0x1 a16 +// GFX9: image_store_mip_pck v252, v[2:3], s[12:19] dmask:0x1 a16 ; encoding: [0x00,0x81,0x2c,0xf0,0x02,0xfc,0x03,0x00] +// NOSICI: error: a16 modifier is not supported on this GPU +// NOVI: error: a16 modifier is not supported on this GPU + //===----------------------------------------------------------------------===// // Image Sample //===----------------------------------------------------------------------===//