Index: test/CodeGen/ARM/inlineasm-X-allocation.ll
===================================================================
--- test/CodeGen/ARM/inlineasm-X-allocation.ll
+++ test/CodeGen/ARM/inlineasm-X-allocation.ll
@@ -1,21 +1,20 @@
-; RUN: llc -mtriple=armv7-none-eabi -mattr=-neon,-vfpv2 %s -o - | FileCheck %s  -check-prefix=novfp
-; RUN: llc -mtriple=armv7-none-eabi -mattr=+neon %s -float-abi=hard -o - | FileCheck %s -check-prefix=vfp
+; RUN: llc -mtriple=armv7-none-eabi -mattr=-neon,-vfp2 %s -o - | FileCheck %s  -check-prefixes=COMMON,NOVFP
+; RUN: llc -mtriple=armv7-none-eabi -mattr=+neon %s -float-abi=hard -o - | FileCheck %s -check-prefixes=COMMON,VFP
 
-; vfp-LABEL: f1
-; vfp-CHECK: vadd.f32 s0, s0, s0
+; The intent here is to test "X", which says that any operand whatsoever is allowed.
+; Using this mechanism, we want to test toggling allocating GPR or SPR registers
+; depending on whether the float registers are available. Thus, the mnemonic is
+; totally irrelevant here, which is why we use FOO and also comment it out using "@"
+; to avoid assembler errors.
 
-; In the novfp case, the compiler is forced to assign a core register.
-; Although this register class can't be used with the vadd.f32 instruction,
-; the compiler behaved as expected since it is allowed to emit anything.
+; Note that this kind of IR can be generated by a function such as:
+;  void f1(float f) {asm volatile ("@FOO $0, $0" : : "X" (f));}
 
-; novfp-LABEL: f1
-; novfp-CHECK: vadd.f32 r0, r0, r0
-
-; This can be generated by a function such as:
-;  void f1(float f) {asm volatile ("add.f32 $0, $0, $0" : : "X" (f));}
-
-define arm_aapcs_vfpcc void @f1(float %f) {
+define arm_aapcs_vfpcc void @func(float %f) {
+; COMMON-LABEL: func
+; NOVFP:        FOO r0, r0
+; VFP:          FOO s0, s0
 entry:
-  call void asm sideeffect "vadd.f32 $0, $0, $0", "X" (float %f) nounwind
+  call void asm sideeffect "@FOO $0, $0", "X" (float %f) nounwind
   ret void
 }