Index: lib/Target/PowerPC/PPC.td
===================================================================
--- lib/Target/PowerPC/PPC.td
+++ lib/Target/PowerPC/PPC.td
@@ -296,7 +296,7 @@
                    FeatureFPRND, Feature64Bit,
                    DeprecatedMFTB, DeprecatedDST]>;
 def : ProcessorModel<"pwr7", P7Model,
-                  [DirectivePwr7, FeatureAltivec,
+                  [DirectivePwr7, FeatureAltivec, FeatureVSX,
                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
@@ -305,7 +305,7 @@
                    Feature64Bit /*, Feature64BitRegs */,
                    DeprecatedMFTB, DeprecatedDST]>;
 def : ProcessorModel<"pwr8", P7Model /* FIXME: Update to P8Model when available */,
-                  [DirectivePwr8, FeatureAltivec,
+                  [DirectivePwr8, FeatureAltivec, FeatureVSX,
                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
Index: lib/Target/PowerPC/PPCFastISel.cpp
===================================================================
--- lib/Target/PowerPC/PPCFastISel.cpp
+++ lib/Target/PowerPC/PPCFastISel.cpp
@@ -665,6 +665,10 @@
   SrcReg = getRegForValue(Op0);
   if (SrcReg == 0)
     return false;
+  // If a VSX register is chosen the FastISel code can't handle it.
+  // Just return and let the normal process take care of things.
+  if (MRI.getRegClass(SrcReg)->getID() == PPC::VSFRCRegClassID)
+    return false;
 
   // See if we can handle this address.
   Address Addr;
@@ -791,6 +795,10 @@
   unsigned SrcReg1 = getRegForValue(SrcValue1);
   if (SrcReg1 == 0)
     return false;
+  // If a VSX register is chosen the FastISel code can't handle it.
+  // Just return and let the normal process take care of things.
+  if (MRI.getRegClass(SrcReg1)->getID() == PPC::VSFRCRegClassID)
+    return false;
 
   unsigned SrcReg2 = 0;
   if (!UseImm) {
@@ -797,6 +805,10 @@
     SrcReg2 = getRegForValue(SrcValue2);
     if (SrcReg2 == 0)
       return false;
+    // If a VSX register is chosen the FastISel code can't handle it.
+    // Just return and let the normal process take care of things.
+    if (MRI.getRegClass(SrcReg2)->getID() == PPC::VSFRCRegClassID)
+      return false;
   }
 
   if (NeedsExt) {
@@ -835,6 +847,10 @@
   unsigned SrcReg = getRegForValue(Src);
   if (!SrcReg)
     return false;
+  // If a VSX register is chosen the FastISel code can't handle it.
+  // Just return and let the normal process take care of things.
+  if (MRI.getRegClass(SrcReg)->getID() == PPC::VSFRCRegClassID)
+    return false;
 
   // No code is generated for a FP extend.
   updateValueMap(I, SrcReg);
@@ -853,6 +869,10 @@
   unsigned SrcReg = getRegForValue(Src);
   if (!SrcReg)
     return false;
+  // If a VSX register is chosen the FastISel code can't handle it.
+  // Just return and let the normal process take care of things.
+  if (MRI.getRegClass(SrcReg)->getID() == PPC::VSFRCRegClassID)
+    return false;
 
   // Round the result to single precision.
   unsigned DestReg = createResultReg(&PPC::F4RCRegClass);
@@ -936,6 +956,10 @@
   unsigned SrcReg = getRegForValue(Src);
   if (SrcReg == 0)
     return false;
+  // If a VSX register is chosen the FastISel code can't handle it.
+  // Just return and let the normal process take care of things.
+  if (MRI.getRegClass(SrcReg)->getID() == PPC::VSFRCRegClassID)
+    return false;
 
   // We can only lower an unsigned convert if we have the newer
   // floating-point conversion operations.
@@ -1044,6 +1068,10 @@
   unsigned SrcReg = getRegForValue(Src);
   if (SrcReg == 0)
     return false;
+  // If a VSX register is chosen the FastISel code can't handle it.
+  // Just return and let the normal process take care of things.
+  if (MRI.getRegClass(SrcReg)->getID() == PPC::VSFRCRegClassID)
+    return false;
 
   // Convert f32 to f64 if necessary.  This is just a meaningless copy
   // to get the register class right.  COPY_TO_REGCLASS is needed since
@@ -1119,6 +1147,10 @@
   unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
   unsigned SrcReg1 = getRegForValue(I->getOperand(0));
   if (SrcReg1 == 0) return false;
+  // If a VSX register is chosen the FastISel code can't handle it.
+  // Just return and let the normal process take care of things.
+  if (MRI.getRegClass(SrcReg1)->getID() == PPC::VSFRCRegClassID)
+    return false;
 
   // Handle case of small immediate operand.
   if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(1))) {
@@ -1177,6 +1209,10 @@
   // Reg-reg case.
   unsigned SrcReg2 = getRegForValue(I->getOperand(1));
   if (SrcReg2 == 0) return false;
+  // If a VSX register is chosen the FastISel code can't handle it.
+  // Just return and let the normal process take care of things.
+  if (MRI.getRegClass(SrcReg2)->getID() == PPC::VSFRCRegClassID)
+    return false;
 
   // Reverse operands for subtract-from.
   if (ISDOpcode == ISD::SUB)
@@ -1465,6 +1501,10 @@
     unsigned Arg = getRegForValue(*II);
     if (Arg == 0)
       return false;
+    // If a VSX register is chosen the FastISel code can't handle it.
+    // Just return and let the normal process take care of things.
+    if (MRI.getRegClass(Arg)->getID() == PPC::VSFRCRegClassID)
+      return false;
 
     unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
     Flags.setOrigAlign(OriginalAlignment);
@@ -1561,6 +1601,10 @@
 
       if (Reg == 0)
         return false;
+      // If a VSX register is chosen the FastISel code can't handle it.
+      // Just return and let the normal process take care of things.
+      if (MRI.getRegClass(Reg)->getID() == PPC::VSFRCRegClassID)
+        return false;
 
       // Copy the result values into the output registers.
       for (unsigned i = 0; i < ValLocs.size(); ++i) {
@@ -1683,6 +1727,10 @@
   unsigned AddrReg = getRegForValue(I->getOperand(0));
   if (AddrReg == 0)
     return false;
+  // If a VSX register is chosen the FastISel code can't handle it.
+  // Just return and let the normal process take care of things.
+  if (MRI.getRegClass(AddrReg)->getID() == PPC::VSFRCRegClassID)
+    return false;
 
   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::MTCTR8))
     .addReg(AddrReg);
@@ -1710,6 +1758,10 @@
   unsigned SrcReg = getRegForValue(Src);
   if (!SrcReg)
     return false;
+  // If a VSX register is chosen the FastISel code can't handle it.
+  // Just return and let the normal process take care of things.
+  if (MRI.getRegClass(SrcReg)->getID() == PPC::VSFRCRegClassID)
+    return false;
 
   // The only interesting case is when we need to switch register classes.
   if (SrcVT == MVT::i64) {
@@ -1733,6 +1785,10 @@
   bool IsZExt = isa<ZExtInst>(I);
   unsigned SrcReg = getRegForValue(Src);
   if (!SrcReg) return false;
+  // If a VSX register is chosen the FastISel code can't handle it.
+  // Just return and let the normal process take care of things.
+  if (MRI.getRegClass(SrcReg)->getID() == PPC::VSFRCRegClassID)
+    return false;
 
   EVT SrcEVT, DestEVT;
   SrcEVT = TLI.getValueType(SrcTy, true);
Index: test/CodeGen/Generic/select-cc.ll
===================================================================
--- test/CodeGen/Generic/select-cc.ll
+++ test/CodeGen/Generic/select-cc.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s
+; RUN: llc -mattr=-vsx < %s
 ; PR2504
 ; XFAIL: hexagon
 define <2 x double> @vector_select(<2 x double> %x, <2 x double> %y) nounwind  {
Index: test/CodeGen/PowerPC/2007-09-08-unaligned.ll
===================================================================
--- test/CodeGen/PowerPC/2007-09-08-unaligned.ll
+++ test/CodeGen/PowerPC/2007-09-08-unaligned.ll
@@ -1,7 +1,11 @@
-; RUN: llc < %s | grep stfd | count 3
-; RUN: llc < %s | grep stfs | count 1
-; RUN: llc < %s | grep lfd | count 2
-; RUN: llc < %s | grep lfs | count 2
+; RUN: llc -mattr=-vsx < %s | grep stfd | count 3
+; RUN: llc -mattr=-vsx < %s | grep stfs | count 1
+; RUN: llc -mattr=-vsx < %s | grep lfd | count 2
+; RUN: llc -mattr=-vsx < %s | grep lfs | count 2
+; RUN: llc -mattr=+vsx < %s | grep stxsdx | count 3
+; RUN: llc -mattr=+vsx < %s | grep stfs | count 1
+; RUN: llc -mattr=+vsx < %s | grep lxsdx | count 2
+; RUN: llc -mattr=+vsx < %s | grep lfs | count 2
 ; ModuleID = 'foo.c'
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
 target triple = "powerpc-apple-darwin8"
Index: test/CodeGen/PowerPC/2012-10-12-bitcast.ll
===================================================================
--- test/CodeGen/PowerPC/2012-10-12-bitcast.ll
+++ test/CodeGen/PowerPC/2012-10-12-bitcast.ll
@@ -1,4 +1,5 @@
-; RUN: llc -mattr=+altivec < %s | FileCheck %s
+; RUN: llc -mattr=-vsx -mattr=+altivec < %s | FileCheck %s
+; RUN: llc -mattr=+vsx -mattr=+altivec < %s | FileCheck -check-prefix=VSX %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -18,3 +19,7 @@
 ; CHECK: lwz 3, -16(1)
 ; CHECK: blr
 
+; VSX: addi [[REGISTER:[0-9]+]], 1, -16
+; VSX: stxvd2x 34, 0, [[REGISTER]]
+; VSX: lwz 3, -16(1)
+; VSX: blr
Index: test/CodeGen/PowerPC/buildvec_canonicalize.ll
===================================================================
--- test/CodeGen/PowerPC/buildvec_canonicalize.ll
+++ test/CodeGen/PowerPC/buildvec_canonicalize.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -march=ppc32 -mattr=+altivec --enable-unsafe-fp-math | FileCheck %s
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mattr=+altivec --enable-unsafe-fp-math | FileCheck %s
+; RUN: llc < %s -mattr=+vsx -march=ppc32 -mattr=+altivec --enable-unsafe-fp-math | FileCheck -check-prefix=VSX %s
 
 define void @VXOR(<4 x float>* %P1, <4 x i32>* %P2, <4 x float>* %P3) {
         %tmp = load <4 x float>* %P3            ; <<4 x float>> [#uses=1]
@@ -14,6 +15,9 @@
 ; CHECK: @VXOR
 ; CHECK: vsplti
 ; CHECK: vxor
+; VSX: @VXOR
+; VSX: vxor
+; VSX: xvmulsp
 
 define void @VSPLTI(<4 x i32>* %P2, <8 x i16>* %P3) {
         store <4 x i32> bitcast (<16 x i8> < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > to <4 x i32>), <4 x i32>* %P2
@@ -22,3 +26,5 @@
 }
 ; CHECK: @VSPLTI
 ; CHECK: vsplti
+; VSX: @VSPLTI
+; VSX: vsplti
Index: test/CodeGen/PowerPC/copysignl.ll
===================================================================
--- test/CodeGen/PowerPC/copysignl.ll
+++ test/CodeGen/PowerPC/copysignl.ll
@@ -1,4 +1,5 @@
-; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=-vsx < %s | FileCheck %s -check-prefix=NOVSX
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck %s -check-prefix=VSX
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -8,9 +9,12 @@
   %conv = fptrunc ppc_fp128 %call to double
   ret double %conv
 
-; CHECK-LABEL: @foo_d_ll
-; CHECK: fcpsgn 1, 3, 1
-; CHECK: blr
+; NOVSX-LABEL: @foo_d_ll
+; NOVSX: fcpsgn 1, 3, 1
+; NOVSX: blr
+; VSX-LABEL: @foo_d_ll
+; VSX: xscpsgndp 1, 3, 1
+; VSX: blr
 }
 
 declare ppc_fp128 @copysignl(ppc_fp128, ppc_fp128) #0
@@ -21,9 +25,12 @@
   %call = tail call double @copysign(double %a, double %conv) #0
   ret double %call
 
-; CHECK-LABEL: @foo_dl
-; CHECK: fcpsgn 1, 2, 1
-; CHECK: blr
+; NOVSX-LABEL: @foo_dl
+; NOVSX: fcpsgn 1, 2, 1
+; NOVSX: blr
+; VSX-LABEL: @foo_dl
+; VSX: xscpsgndp 1, 2, 1
+; VSX: blr
 }
 
 declare double @copysign(double, double) #0
@@ -34,9 +41,12 @@
   %call = tail call ppc_fp128 @copysignl(ppc_fp128 %conv, ppc_fp128 %b) #0
   ret ppc_fp128 %call
 
-; CHECK-LABEL: @foo_ll
-; CHECK: bl copysignl
-; CHECK: blr
+; NOVSX-LABEL: @foo_ll
+; NOVSX: bl copysignl
+; NOVSX: blr
+; VSX-LABEL: @foo_ll
+; VSX: bl copysignl
+; VSX: blr
 }
 
 define ppc_fp128 @foo_ld(double %a, double %b) #0 {
@@ -46,9 +56,12 @@
   %call = tail call ppc_fp128 @copysignl(ppc_fp128 %conv, ppc_fp128 %conv1) #0
   ret ppc_fp128 %call
 
-; CHECK-LABEL: @foo_ld
-; CHECK: bl copysignl
-; CHECK: blr
+; NOVSX-LABEL: @foo_ld
+; NOVSX: bl copysignl
+; NOVSX: blr
+; VSX-LABEL: @foo_ld
+; VSX: bl copysignl
+; VSX: blr
 }
 
 define ppc_fp128 @foo_lf(double %a, float %b) #0 {
@@ -58,9 +71,12 @@
   %call = tail call ppc_fp128 @copysignl(ppc_fp128 %conv, ppc_fp128 %conv1) #0
   ret ppc_fp128 %call
 
-; CHECK-LABEL: @foo_lf
-; CHECK: bl copysignl
-; CHECK: blr
+; NOVSX-LABEL: @foo_lf
+; NOVSX: bl copysignl
+; NOVSX: blr
+; VSX-LABEL: @foo_lf
+; VSX: bl copysignl
+; VSX: blr
 }
 
 attributes #0 = { nounwind readnone }
Index: test/CodeGen/PowerPC/fabs.ll
===================================================================
--- test/CodeGen/PowerPC/fabs.ll
+++ test/CodeGen/PowerPC/fabs.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | grep "fabs f1, f1"
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin | grep "fabs f1, f1"
+; RUN: llc < %s -mattr=+vsx -march=ppc32 -mtriple=powerpc-apple-darwin | grep "xsabsdp f1, f1"
 
 define double @fabs(double %f) {
 entry:
Index: test/CodeGen/PowerPC/fast-isel-call.ll
===================================================================
--- test/CodeGen/PowerPC/fast-isel-call.ll
+++ test/CodeGen/PowerPC/fast-isel-call.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
 
 define i32 @t1(i8 signext %a) nounwind {
   %1 = sext i8 %a to i32
Index: test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
===================================================================
--- test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
+++ test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
 
 define void @t1a(float %a) uwtable ssp {
 entry:
Index: test/CodeGen/PowerPC/fast-isel-conversion.ll
===================================================================
--- test/CodeGen/PowerPC/fast-isel-conversion.ll
+++ test/CodeGen/PowerPC/fast-isel-conversion.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
-; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 | FileCheck %s --check-prefix=PPC970
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 -mattr=-vsx | FileCheck %s --check-prefix=PPC970
 
 ;; Tests for 970 don't use -fast-isel-abort because we intentionally punt
 ;; to SelectionDAG in some cases.
Index: test/CodeGen/PowerPC/fast-isel-load-store.ll
===================================================================
--- test/CodeGen/PowerPC/fast-isel-load-store.ll
+++ test/CodeGen/PowerPC/fast-isel-load-store.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
 
 ; This test verifies that load/store instructions are properly generated,
 ; and that they pass MI verification.
Index: test/CodeGen/PowerPC/fast-isel-ret.ll
===================================================================
--- test/CodeGen/PowerPC/fast-isel-ret.ll
+++ test/CodeGen/PowerPC/fast-isel-ret.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
 
 define signext i8 @ret2(i8 signext %a) nounwind uwtable ssp {
 entry:
Index: test/CodeGen/PowerPC/fcpsgn.ll
===================================================================
--- test/CodeGen/PowerPC/fcpsgn.ll
+++ test/CodeGen/PowerPC/fcpsgn.ll
@@ -1,4 +1,5 @@
-; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx < %s | FileCheck -check-prefix=NOVSX %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=VSX %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -7,9 +8,12 @@
   %call = tail call double @copysign(double %a, double %b) #0
   ret double %call
 
-; CHECK-LABEL: @foo_dd
-; CHECK: fcpsgn 1, 2, 1
-; CHECK: blr
+; NOVSX-LABEL: @foo_dd
+; NOVSX: fcpsgn 1, 2, 1
+; NOVSX: blr
+; VSX-LABEL: @foo_dd
+; VSX: xscpsgndp 1, 2, 1
+; VSX: blr
 }
 
 declare double @copysign(double, double) #0
@@ -19,9 +23,12 @@
   %call = tail call float @copysignf(float %a, float %b) #0
   ret float %call
 
-; CHECK-LABEL: @foo_ss
-; CHECK: fcpsgn 1, 2, 1
-; CHECK: blr
+; NOVSX-LABEL: @foo_ss
+; NOVSX: fcpsgn 1, 2, 1
+; NOVSX: blr
+; VSX-LABEL: @foo_ss
+; VSX: fcpsgn 1, 2, 1
+; VSX: blr
 }
 
 declare float @copysignf(float, float) #0
@@ -32,9 +39,12 @@
   %call = tail call float @copysignf(float %a, float %conv) #0
   ret float %call
 
-; CHECK-LABEL: @foo_sd
-; CHECK: fcpsgn 1, 2, 1
-; CHECK: blr
+; NOVSX-LABEL: @foo_sd
+; NOVSX: fcpsgn 1, 2, 1
+; NOVSX: blr
+; VSX-LABEL: @foo_sd
+; VSX: fcpsgn 1, 2, 1
+; VSX: blr
 }
 
 define double @foo_ds(double %a, float %b) #0 {
@@ -43,9 +53,12 @@
   %call = tail call double @copysign(double %a, double %conv) #0
   ret double %call
 
-; CHECK-LABEL: @foo_ds
-; CHECK: fcpsgn 1, 2, 1
-; CHECK: blr
+; NOVSX-LABEL: @foo_ds
+; NOVSX: fcpsgn 1, 2, 1
+; NOVSX: blr
+; VSX-LABEL: @foo_ds
+; VSX: fcpsgn 1, 2, 1
+; VSX: blr
 }
 
 attributes #0 = { nounwind readnone }
Index: test/CodeGen/PowerPC/fma.ll
===================================================================
--- test/CodeGen/PowerPC/fma.ll
+++ test/CodeGen/PowerPC/fma.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=ppc32 -fp-contract=fast | FileCheck %s
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -fp-contract=fast | FileCheck %s
 
 define double @test_FMADD1(double %A, double %B, double %C) {
 	%D = fmul double %A, %B		; <double> [#uses=1]
Index: test/CodeGen/PowerPC/fnabs.ll
===================================================================
--- test/CodeGen/PowerPC/fnabs.ll
+++ test/CodeGen/PowerPC/fnabs.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=ppc32 | grep fnabs
+; RUN: llc < %s -mattr=-vsx -march=ppc32 | grep fnabs
 
 declare double @fabs(double)
 
Index: test/CodeGen/PowerPC/fp-branch.ll
===================================================================
--- test/CodeGen/PowerPC/fp-branch.ll
+++ test/CodeGen/PowerPC/fp-branch.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=ppc32 | grep fcmp | count 1
+; RUN: llc < %s -mattr=-vsx -march=ppc32 | grep fcmp | count 1
 
 declare i1 @llvm.isunordered.f64(double, double)
 
Index: test/CodeGen/PowerPC/fp_to_uint.ll
===================================================================
--- test/CodeGen/PowerPC/fp_to_uint.ll
+++ test/CodeGen/PowerPC/fp_to_uint.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=ppc32 | grep fctiwz | count 1
+; RUN: llc < %s -mattr=-vsx -march=ppc32 | grep fctiwz | count 1
 
 define i16 @foo(float %a) {
 entry:
Index: test/CodeGen/PowerPC/fsel.ll
===================================================================
--- test/CodeGen/PowerPC/fsel.ll
+++ test/CodeGen/PowerPC/fsel.ll
@@ -1,5 +1,6 @@
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=CHECK-FM %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=-vsx | FileCheck -check-prefix=CHECK-FM %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=+vsx | FileCheck -check-prefix=CHECK-FM-VSX %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -16,6 +17,10 @@
 ; CHECK-FM: @zerocmp1
 ; CHECK-FM: fsel 1, 1, 2, 3
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @zerocmp1
+; CHECK-FM-VSX: fsel 1, 1, 2, 3
+; CHECK-FM-VSX: blr
 }
 
 define double @zerocmp2(double %a, double %y, double %z) #0 {
@@ -32,6 +37,11 @@
 ; CHECK-FM: fneg [[REG:[0-9]+]], 1
 ; CHECK-FM: fsel 1, [[REG]], 3, 2
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @zerocmp2
+; CHECK-FM-VSX: xsnegdp [[REG:[0-9]+]], 1
+; CHECK-FM-VSX: fsel 1, [[REG]], 3, 2
+; CHECK-FM-VSX: blr
 }
 
 define double @zerocmp3(double %a, double %y, double %z) #0 {
@@ -49,6 +59,12 @@
 ; CHECK-FM: fneg [[REG2:[0-9]+]], 1
 ; CHECK-FM: fsel 1, [[REG2]], [[REG]], 3
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @zerocmp3
+; CHECK-FM-VSX: xsnegdp [[REG2:[0-9]+]], 1
+; CHECK-FM-VSX: fsel [[REG:[0-9]+]], 1, 2, 3
+; CHECK-FM-VSX: fsel 1, [[REG2]], [[REG]], 3
+; CHECK-FM-VSX: blr
 }
 
 define double @min1(double %a, double %b) #0 {
@@ -65,6 +81,11 @@
 ; CHECK-FM: fsub [[REG:[0-9]+]], 2, 1
 ; CHECK-FM: fsel 1, [[REG]], 1, 2
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @min1
+; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 2, 1
+; CHECK-FM-VSX: fsel 1, [[REG]], 1, 2
+; CHECK-FM-VSX: blr
 }
 
 define double @max1(double %a, double %b) #0 {
@@ -81,6 +102,11 @@
 ; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2
 ; CHECK-FM: fsel 1, [[REG]], 1, 2
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @max1
+; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2
+; CHECK-FM-VSX: fsel 1, [[REG]], 1, 2
+; CHECK-FM-VSX: blr
 }
 
 define double @cmp1(double %a, double %b, double %y, double %z) #0 {
@@ -97,6 +123,11 @@
 ; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2
 ; CHECK-FM: fsel 1, [[REG]], 3, 4
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @cmp1
+; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2
+; CHECK-FM-VSX: fsel 1, [[REG]], 3, 4
+; CHECK-FM-VSX: blr
 }
 
 define double @cmp2(double %a, double %b, double %y, double %z) #0 {
@@ -113,6 +144,11 @@
 ; CHECK-FM: fsub [[REG:[0-9]+]], 2, 1
 ; CHECK-FM: fsel 1, [[REG]], 4, 3
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @cmp2
+; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 2, 1
+; CHECK-FM-VSX: fsel 1, [[REG]], 4, 3
+; CHECK-FM-VSX: blr
 }
 
 define double @cmp3(double %a, double %b, double %y, double %z) #0 {
@@ -131,6 +167,13 @@
 ; CHECK-FM: fneg [[REG3:[0-9]+]], [[REG]]
 ; CHECK-FM: fsel 1, [[REG3]], [[REG2]], 4
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @cmp3
+; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2
+; CHECK-FM-VSX: xsnegdp [[REG3:[0-9]+]], [[REG]]
+; CHECK-FM-VSX: fsel [[REG2:[0-9]+]], [[REG]], 3, 4
+; CHECK-FM-VSX: fsel 1, [[REG3]], [[REG2]], 4
+; CHECK-FM-VSX: blr
 }
 
 attributes #0 = { nounwind readnone }
Index: test/CodeGen/PowerPC/fsqrt.ll
===================================================================
--- test/CodeGen/PowerPC/fsqrt.ll
+++ test/CodeGen/PowerPC/fsqrt.ll
@@ -1,13 +1,13 @@
 ; fsqrt should be generated when the fsqrt feature is enabled, but not 
 ; otherwise.
 
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=+fsqrt | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=+fsqrt | \
 ; RUN:   grep "fsqrt f1, f1"
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \
 ; RUN:   grep "fsqrt f1, f1"
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-fsqrt | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-fsqrt | \
 ; RUN:   not grep "fsqrt f1, f1"
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g4 | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g4 | \
 ; RUN:   not grep "fsqrt f1, f1"
 
 declare double @llvm.sqrt.f64(double)
Index: test/CodeGen/PowerPC/i64_fp.ll
===================================================================
--- test/CodeGen/PowerPC/i64_fp.ll
+++ test/CodeGen/PowerPC/i64_fp.ll
@@ -1,21 +1,21 @@
 ; fcfid and fctid should be generated when the 64bit feature is enabled, but not
 ; otherwise.
 
-; RUN: llc < %s -march=ppc32 -mattr=+64bit | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mattr=+64bit | \
 ; RUN:   grep fcfid
-; RUN: llc < %s -march=ppc32 -mattr=+64bit | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mattr=+64bit | \
 ; RUN:   grep fctidz
-; RUN: llc < %s -march=ppc32 -mcpu=g5 | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mcpu=g5 | \
 ; RUN:   grep fcfid
-; RUN: llc < %s -march=ppc32 -mcpu=g5 | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mcpu=g5 | \
 ; RUN:   grep fctidz
-; RUN: llc < %s -march=ppc32 -mattr=-64bit | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mattr=-64bit | \
 ; RUN:   not grep fcfid
-; RUN: llc < %s -march=ppc32 -mattr=-64bit | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mattr=-64bit | \
 ; RUN:   not grep fctidz
-; RUN: llc < %s -march=ppc32 -mcpu=g4 | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mcpu=g4 | \
 ; RUN:   not grep fcfid
-; RUN: llc < %s -march=ppc32 -mcpu=g4 | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mcpu=g4 | \
 ; RUN:   not grep fctidz
 
 define double @X(double %Y) {
Index: test/CodeGen/PowerPC/mcm-12.ll
===================================================================
--- test/CodeGen/PowerPC/mcm-12.ll
+++ test/CodeGen/PowerPC/mcm-12.ll
@@ -1,4 +1,5 @@
-; RUN: llc -mcpu=pwr7 -O1 -code-model=medium <%s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O1 -code-model=medium -mattr=-vsx < %s | FileCheck -check-prefix=NOVSX %s
+; RUN: llc -mcpu=pwr7 -O1 -code-model=medium -mattr=+vsx < %s | FileCheck -check-prefix=VSX %s
 
 ; Test peephole optimization for medium code model (32-bit TOC offsets)
 ; for loading a value from the constant pool (TOC-relative).
@@ -11,8 +12,15 @@
   ret double 0x3F4FD4920B498CF0
 }
 
-; CHECK: [[VAR:[a-z0-9A-Z_.]+]]:
-; CHECK: .quad 4562098671269285104
-; CHECK-LABEL: test_double_const:
-; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
-; CHECK: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
+; NOVSX: [[VAR:[a-z0-9A-Z_.]+]]:
+; NOVSX: .quad 4562098671269285104
+; NOVSX-LABEL: test_double_const:
+; NOVSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
+; NOVSX: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
+
+; VSX: [[VAR:[a-z0-9A-Z_.]+]]:
+; VSX: .quad 4562098671269285104
+; VSX-LABEL: test_double_const:
+; VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
+; VSX: addi [[REG1]], {{[0-9]+}}, [[VAR]]@toc@l
+; VSX: lxsdx {{[0-9]+}}, 0, [[REG1]]
Index: test/CodeGen/PowerPC/mcm-4.ll
===================================================================
--- test/CodeGen/PowerPC/mcm-4.ll
+++ test/CodeGen/PowerPC/mcm-4.ll
@@ -1,5 +1,7 @@
-; RUN: llc -mcpu=pwr7 -O0 -code-model=medium -fast-isel=false <%s | FileCheck -check-prefix=MEDIUM %s
-; RUN: llc -mcpu=pwr7 -O0 -code-model=large -fast-isel=false <%s | FileCheck -check-prefix=LARGE %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=medium -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=MEDIUM %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=medium -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=MEDIUM-VSX %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=large -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=LARGE %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=large -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=LARGE-VSX %s
 
 ; Test correct code generation for medium and large code model
 ; for loading a value from the constant pool (TOC-relative).
@@ -19,6 +21,13 @@
 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
 ; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]])
 
+; MEDIUM-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
+; MEDIUM-VSX: .quad 4562098671269285104
+; MEDIUM-VSX-LABEL: test_double_const:
+; MEDIUM-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
+; MEDIUM-VSX: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
+; MEDIUM-VSX: lxsdx {{[0-9]+}}, 0, [[REG2]]
+
 ; LARGE: [[VAR:[a-z0-9A-Z_.]+]]:
 ; LARGE: .quad 4562098671269285104
 ; LARGE-LABEL: test_double_const:
@@ -25,3 +34,10 @@
 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
 ; LARGE: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
 ; LARGE: lfd {{[0-9]+}}, 0([[REG2]])
+
+; LARGE-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
+; LARGE-VSX: .quad 4562098671269285104
+; LARGE-VSX-LABEL: test_double_const:
+; LARGE-VSX: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
+; LARGE-VSX: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
+; LARGE-VSX: lxsdx {{[0-9]+}}, 0, [[REG2]]
Index: test/CodeGen/PowerPC/ppc64-align-long-double.ll
===================================================================
--- test/CodeGen/PowerPC/ppc64-align-long-double.ll
+++ test/CodeGen/PowerPC/ppc64-align-long-double.ll
@@ -1,4 +1,5 @@
-; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false -mattr=-vsx < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=VSX %s
 
 ; Verify internal alignment of long double in a struct.  The double
 ; argument comes in in GPR3; GPR4 is skipped; GPRs 5 and 6 contain
@@ -24,3 +25,12 @@
 ; CHECK: lfd 1, 64(1)
 ; CHECK: lfd 2, 72(1)
 
+; VSX: std 6, 72(1)
+; VSX: std 5, 64(1)
+; VSX: std 4, 56(1)
+; VSX: std 3, 48(1)
+; VSX: li 3, 16
+; VSX: addi 4, 1, 48
+; VSX: lxsdx 1, 4, 3
+; VSX: li 3, 24
+; VSX: lxsdx 2, 4, 3
Index: test/CodeGen/PowerPC/recipest.ll
===================================================================
--- test/CodeGen/PowerPC/recipest.ll
+++ test/CodeGen/PowerPC/recipest.ll
@@ -1,5 +1,7 @@
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-unsafe-fp-math | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck -check-prefix=CHECK-SAFE %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-unsafe-fp-math -mattr=-vsx | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck -check-prefix=CHECK-SAFE %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-unsafe-fp-math -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-SAFE-VSX %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -25,10 +27,27 @@
 ; CHECK: fmul
 ; CHECK: blr
 
+; CHECK-VSX: @foo
+; CHECK-DAG-VSX: xsrsqrtedp
+; CHECK-DAG-VSX: xsnmsubadp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: xsmaddmdp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: xsmaddadp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: blr
+
 ; CHECK-SAFE: @foo
 ; CHECK-SAFE: fsqrt
 ; CHECK-SAFE: fdiv
 ; CHECK-SAFE: blr
+
+; CHECK-SAFE-VSX: @foo
+; CHECK-SAFE-VSX: xssqrtdp
+; CHECK-SAFE-VSX: xsdivdp
+; CHECK-SAFE-VSX: blr
 }
 
 define double @foof(double %a, float %b) nounwind {
@@ -47,10 +66,24 @@
 ; CHECK: fmul
 ; CHECK: blr
 
+; CHECK-VSX: @foof
+; CHECK-DAG-VSX: frsqrtes
+; CHECK-DAG-VSX: fnmsubs
+; CHECK-VSX: fmuls
+; CHECK-VSX: fmadds
+; CHECK-VSX: fmuls
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: blr
+
 ; CHECK-SAFE: @foof
 ; CHECK-SAFE: fsqrts
 ; CHECK-SAFE: fdiv
 ; CHECK-SAFE: blr
+
+; CHECK-SAFE-VSX: @foof
+; CHECK-SAFE-VSX: fsqrts
+; CHECK-SAFE-VSX: xsdivdp
+; CHECK-SAFE-VSX: blr
 }
 
 define float @food(float %a, double %b) nounwind {
@@ -60,7 +93,7 @@
   %r = fdiv float %a, %y
   ret float %r
 
-; CHECK: @foo
+; CHECK: @food
 ; CHECK-DAG: frsqrte
 ; CHECK-DAG: fnmsub
 ; CHECK: fmul
@@ -73,10 +106,28 @@
 ; CHECK: fmuls
 ; CHECK: blr
 
-; CHECK-SAFE: @foo
+; CHECK-VSX: @food
+; CHECK-DAG-VSX: xsrsqrtedp
+; CHECK-DAG-VSX: xsnmsubadp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: xsmaddmdp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: xsmaddadp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: frsp
+; CHECK-VSX: fmuls
+; CHECK-VSX: blr
+
+; CHECK-SAFE: @food
 ; CHECK-SAFE: fsqrt
 ; CHECK-SAFE: fdivs
 ; CHECK-SAFE: blr
+
+; CHECK-SAFE-VSX: @food
+; CHECK-SAFE-VSX: xssqrtdp
+; CHECK-SAFE-VSX: fdivs
+; CHECK-SAFE-VSX: blr
 }
 
 define float @goo(float %a, float %b) nounwind {
@@ -94,10 +145,24 @@
 ; CHECK: fmuls
 ; CHECK: blr
 
+; CHECK-VSX: @goo
+; CHECK-DAG-VSX: frsqrtes
+; CHECK-DAG-VSX: fnmsubs
+; CHECK-VSX: fmuls
+; CHECK-VSX: fmadds
+; CHECK-VSX: fmuls
+; CHECK-VSX: fmuls
+; CHECK-VSX: blr
+
 ; CHECK-SAFE: @goo
 ; CHECK-SAFE: fsqrts
 ; CHECK-SAFE: fdivs
 ; CHECK-SAFE: blr
+
+; CHECK-SAFE-VSX: @goo
+; CHECK-SAFE-VSX: fsqrts
+; CHECK-SAFE-VSX: fdivs
+; CHECK-SAFE-VSX: blr
 }
 
 define <4 x float> @hoo(<4 x float> %a, <4 x float> %b) nounwind {
@@ -109,9 +174,17 @@
 ; CHECK: @hoo
 ; CHECK: vrsqrtefp
 
+; CHECK-VSX: @hoo
+; CHECK-VSX: xvrsqrtesp
+
 ; CHECK-SAFE: @hoo
 ; CHECK-SAFE-NOT: vrsqrtefp
 ; CHECK-SAFE: blr
+
+; CHECK-SAFE-VSX: @hoo
+; CHECK-SAFE-VSX: xvsqrtsp
+; CHECK-SAFE-VSX: xvdivsp
+; CHECK-SAFE-VSX: blr
 }
 
 define double @foo2(double %a, double %b) nounwind {
@@ -128,9 +201,22 @@
 ; CHECK: fmul
 ; CHECK: blr
 
+; CHECK-VSX: @foo2
+; CHECK-DAG-VSX: xsredp
+; CHECK-DAG-VSX: xsnmsubadp
+; CHECK-VSX: xsmaddadp
+; CHECK-VSX: xsnmsubadp
+; CHECK-VSX: xsmaddadp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: blr
+
 ; CHECK-SAFE: @foo2
 ; CHECK-SAFE: fdiv
 ; CHECK-SAFE: blr
+
+; CHECK-SAFE-VSX: @foo2
+; CHECK-SAFE-VSX: xsdivdp
+; CHECK-SAFE-VSX: blr
 }
 
 define float @goo2(float %a, float %b) nounwind {
@@ -145,9 +231,20 @@
 ; CHECK: fmuls
 ; CHECK: blr
 
+; CHECK-VSX: @goo2
+; CHECK-DAG-VSX: fres
+; CHECK-DAG-VSX: fnmsubs
+; CHECK-VSX: fmadds
+; CHECK-VSX: fmuls
+; CHECK-VSX: blr
+
 ; CHECK-SAFE: @goo2
 ; CHECK-SAFE: fdivs
 ; CHECK-SAFE: blr
+
+; CHECK-SAFE-VSX: @goo2
+; CHECK-SAFE-VSX: fdivs
+; CHECK-SAFE-VSX: blr
 }
 
 define <4 x float> @hoo2(<4 x float> %a, <4 x float> %b) nounwind {
@@ -158,9 +255,16 @@
 ; CHECK: @hoo2
 ; CHECK: vrefp
 
+; CHECK-VSX: @hoo2
+; CHECK-VSX: xvresp
+
 ; CHECK-SAFE: @hoo2
 ; CHECK-SAFE-NOT: vrefp
 ; CHECK-SAFE: blr
+
+; CHECK-SAFE-VSX: @hoo2
+; CHECK-SAFEVSX: xvdivsp
+; CHECK-SAFE-VSX: blr
 }
 
 define double @foo3(double %a) nounwind {
@@ -167,7 +271,7 @@
 entry:
   %r = call double @llvm.sqrt.f64(double %a)
   ret double %r
-
+  
 ; CHECK: @foo3
 ; CHECK: fcmpu
 ; CHECK-DAG: frsqrte
@@ -185,9 +289,31 @@
 ; CHECK: fmadd
 ; CHECK: blr
 
+; CHECK-VSX: @foo3
+; CHECK-VSX: xscmpudp
+; CHECK-DAG-VSX: xsrsqrtedp
+; CHECK-DAG-VSX: xsnmsubadp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: fmr
+; CHECK-VSX: xsmaddmdp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: xsmaddadp
+; CHECK-VSX: xsmuldp
+; CHECK-VSX: xsredp
+; CHECK-VSX: xsnmsubadp
+; CHECK-VSX: xsmaddadp
+; CHECK-VSX: xsnmsubadp
+; CHECK-VSX: xsmaddadp
+; CHECK-VSX: blr
+
 ; CHECK-SAFE: @foo3
 ; CHECK-SAFE: fsqrt
 ; CHECK-SAFE: blr
+
+; CHECK-SAFE-VSX: @foo3
+; CHECK-SAFE-VSX: xssqrtdp
+; CHECK-SAFE-VSX: blr
 }
 
 define float @goo3(float %a) nounwind {
@@ -207,9 +333,25 @@
 ; CHECK: fmadds
 ; CHECK: blr
 
+; CHECK-VSX: @goo3
+; CHECK-VSX: fcmpu
+; CHECK-DAG-VSX: frsqrtes
+; CHECK-DAG-VSX: fnmsubs
+; CHECK-VSX: fmuls
+; CHECK-VSX: fmadds
+; CHECK-VSX: fmuls
+; CHECK-VSX: fres
+; CHECK-VSX: fnmsubs
+; CHECK-VSX: fmadds
+; CHECK-VSX: blr
+
 ; CHECK-SAFE: @goo3
 ; CHECK-SAFE: fsqrts
 ; CHECK-SAFE: blr
+
+; CHECK-SAFE-VSX: @goo3
+; CHECK-SAFE-VSX: fsqrts
+; CHECK-SAFE-VSX: blr
 }
 
 define <4 x float> @hoo3(<4 x float> %a) nounwind {
@@ -222,8 +364,17 @@
 ; CHECK-DAG: vrefp
 ; CHECK-DAG: vcmpeqfp
 
+; CHECK-VSX: @hoo3
+; CHECK-VSX: xvrsqrtesp
+; CHECK-DAG-VSX: xvresp
+; CHECK-DAG-VSX: xvcmpeqsp
+
 ; CHECK-SAFE: @hoo3
 ; CHECK-SAFE-NOT: vrsqrtefp
 ; CHECK-SAFE: blr
+
+; CHECK-SAFE-VSX: @hoo3
+; CHECK-SAFE-VSX: xvsqrtsp
+; CHECK-SAFE-VSX: blr
 }
 
Index: test/CodeGen/PowerPC/rounding-ops.ll
===================================================================
--- test/CodeGen/PowerPC/rounding-ops.ll
+++ test/CodeGen/PowerPC/rounding-ops.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx < %s | FileCheck -check-prefix=NOVSX %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=VSX %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -6,8 +7,10 @@
   %call = tail call float @floorf(float %x) nounwind readnone
   ret float %call
 
-; CHECK-LABEL: test1:
-; CHECK: frim 1, 1
+; NOVSX-LABEL: test1:
+; NOVSX: frim 1, 1
+; VSX-LABEL: test1:
+; VSX: frim 1, 1
 }
 
 declare float @floorf(float) nounwind readnone
@@ -16,8 +19,10 @@
   %call = tail call double @floor(double %x) nounwind readnone
   ret double %call
 
-; CHECK-LABEL: test2:
-; CHECK: frim 1, 1
+; NOVSX-LABEL: test2:
+; NOVSX: frim 1, 1
+; VSX-LABEL: test2:
+; VSX: xsrdpim 1, 1
 }
 
 declare double @floor(double) nounwind readnone
@@ -26,8 +31,10 @@
   %call = tail call float @roundf(float %x) nounwind readnone
   ret float %call
 
-; CHECK-LABEL: test3:
-; CHECK: frin 1, 1
+; NOVSX-LABEL: test3:
+; NOVSX: frin 1, 1
+; VSX-LABEL: test3:
+; VSX: frin 1, 1
 }
 
 declare float @roundf(float) nounwind readnone
@@ -36,8 +43,10 @@
   %call = tail call double @round(double %x) nounwind readnone
   ret double %call
 
-; CHECK-LABEL: test4:
-; CHECK: frin 1, 1
+; NOVSX-LABEL: test4:
+; NOVSX: frin 1, 1
+; VSX-LABEL: test4:
+; VSX: xsrdpi 1, 1
 }
 
 declare double @round(double) nounwind readnone
@@ -46,8 +55,10 @@
   %call = tail call float @ceilf(float %x) nounwind readnone
   ret float %call
 
-; CHECK-LABEL: test5:
-; CHECK: frip 1, 1
+; NOVSX-LABEL: test5:
+; NOVSX: frip 1, 1
+; VSX-LABEL: test5:
+; VSX: frip 1, 1
 }
 
 declare float @ceilf(float) nounwind readnone
@@ -56,8 +67,10 @@
   %call = tail call double @ceil(double %x) nounwind readnone
   ret double %call
 
-; CHECK-LABEL: test6:
-; CHECK: frip 1, 1
+; NOVSX-LABEL: test6:
+; NOVSX: frip 1, 1
+; VSX-LABEL: test6:
+; VSX: xsrdpip 1, 1
 }
 
 declare double @ceil(double) nounwind readnone
@@ -66,8 +79,10 @@
   %call = tail call float @truncf(float %x) nounwind readnone
   ret float %call
 
-; CHECK-LABEL: test9:
-; CHECK: friz 1, 1
+; NOVSX-LABEL: test9:
+; NOVSX: friz 1, 1
+; VSX-LABEL: test9:
+; VSX: friz 1, 1
 }
 
 declare float @truncf(float) nounwind readnone
@@ -76,8 +91,10 @@
   %call = tail call double @trunc(double %x) nounwind readnone
   ret double %call
 
-; CHECK-LABEL: test10:
-; CHECK: friz 1, 1
+; NOVSX-LABEL: test10:
+; NOVSX: friz 1, 1
+; VSX-LABEL: test10:
+; VSX: xsrdpiz 1, 1
 }
 
 declare double @trunc(double) nounwind readnone
Index: test/CodeGen/PowerPC/select-cc.ll
===================================================================
--- test/CodeGen/PowerPC/select-cc.ll
+++ test/CodeGen/PowerPC/select-cc.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=ppc32
+; RUN: llc < %s -mattr=-vsx -march=ppc32
 ; PR3011
 
 define <2 x double> @vector_select(<2 x double> %x, <2 x double> %y) nounwind  {
Index: test/CodeGen/PowerPC/unaligned.ll
===================================================================
--- test/CodeGen/PowerPC/unaligned.ll
+++ test/CodeGen/PowerPC/unaligned.ll
@@ -1,5 +1,7 @@
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=VSX %s
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
 
 define void @foo1(i16* %p, i16* %r) nounwind {
 entry:
@@ -10,6 +12,10 @@
 ; CHECK: @foo1
 ; CHECK: lhz
 ; CHECK: sth
+
+; VSX: @foo1
+; VSX: lhz
+; VSX: sth
 }
 
 define void @foo2(i32* %p, i32* %r) nounwind {
@@ -21,6 +27,10 @@
 ; CHECK: @foo2
 ; CHECK: lwz
 ; CHECK: stw
+
+; VSX: @foo2
+; VSX: lwz
+; VSX: stw
 }
 
 define void @foo3(i64* %p, i64* %r) nounwind {
@@ -32,6 +42,10 @@
 ; CHECK: @foo3
 ; CHECK: ld
 ; CHECK: std
+
+; VSX: @foo3
+; VSX: ld
+; VSX: std
 }
 
 define void @foo4(float* %p, float* %r) nounwind {
@@ -43,6 +57,10 @@
 ; CHECK: @foo4
 ; CHECK: lfs
 ; CHECK: stfs
+
+; VSX: @foo4
+; VSX: lfs
+; VSX: stfs
 }
 
 define void @foo5(double* %p, double* %r) nounwind {
@@ -54,6 +72,10 @@
 ; CHECK: @foo5
 ; CHECK: lfd
 ; CHECK: stfd
+
+; VSX: @foo5
+; VSX: lxsdx
+; VSX: stxsdx
 }
 
 define void @foo6(<4 x float>* %p, <4 x float>* %r) nounwind {
@@ -69,5 +91,11 @@
 ; CHECK-DAG: ld
 ; CHECK-DAG: stdx
 ; CHECK: stdx
+
+; VSX: @foo6
+; VSX-DAG: ld
+; VSX-DAG: ld
+; VSX-DAG: stdx
+; VSX: stdx
 }
 
Index: test/CodeGen/PowerPC/unsafe-math.ll
===================================================================
--- test/CodeGen/PowerPC/unsafe-math.ll
+++ test/CodeGen/PowerPC/unsafe-math.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=ppc32 | grep fmul | count 2
-; RUN: llc < %s -march=ppc32 -enable-unsafe-fp-math | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 | grep fmul | count 2
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -enable-unsafe-fp-math | \
 ; RUN:   grep fmul | count 1
 
 define double @foo(double %X) nounwind {
Index: test/CodeGen/PowerPC/vec_mul.ll
===================================================================
--- test/CodeGen/PowerPC/vec_mul.ll
+++ test/CodeGen/PowerPC/vec_mul.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -march=ppc32 -mattr=+altivec | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec | FileCheck %s -check-prefix=CHECK-LE
+; RUN: llc < %s -mattr=-vsx -mtriple=powerpc-unknown-linux-gnu -march=ppc32 -mattr=+altivec -mattr=-vsx | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx | FileCheck %s -check-prefix=CHECK-LE
 
 define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) {
 	%tmp = load <4 x i32>* %X		; <<4 x i32>> [#uses=1]