Index: /home/seurer/llvm/llvm-oneoff/include/llvm/CodeGen/FastISel.h =================================================================== --- /home/seurer/llvm/llvm-oneoff/include/llvm/CodeGen/FastISel.h +++ /home/seurer/llvm/llvm-oneoff/include/llvm/CodeGen/FastISel.h @@ -480,6 +480,12 @@ return 0; } + /// \brief Verify that a type is valid for FastISel. Should be overriden + /// by targets with more restrictive type legality in FastIsel. + virtual bool isTypeLegal(EVT Evt) const { + return TLI.isTypeLegal(Evt); + } + /// \brief Check if \c Add is an add that can be safely folded into \c GEP. /// /// \c Add can be folded into \c GEP if: Index: /home/seurer/llvm/llvm-oneoff/lib/CodeGen/SelectionDAG/FastISel.cpp =================================================================== --- /home/seurer/llvm/llvm-oneoff/lib/CodeGen/SelectionDAG/FastISel.cpp +++ /home/seurer/llvm/llvm-oneoff/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -173,7 +173,7 @@ // in ValueMap because Arguments are given virtual registers regardless // of whether FastISel can handle them. MVT VT = RealVT.getSimpleVT(); - if (!TLI.isTypeLegal(VT)) { + if (!isTypeLegal(VT)) { // Handle integer promotions, though, because they're common and easy. if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); @@ -387,7 +387,7 @@ // selector contains all of the 64-bit instructions from x86-64, // under the assumption that i64 won't be used if the target doesn't // support it. - if (!TLI.isTypeLegal(VT)) { + if (!isTypeLegal(VT)) { // MVT::i1 is special. Allow AND, OR, or XOR because they // don't require additional zeroing, which makes them easy. if (VT == MVT::i1 && (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || @@ -1221,11 +1221,11 @@ return false; // Check if the destination type is legal. - if (!TLI.isTypeLegal(DstVT)) + if (!isTypeLegal(DstVT)) return false; // Check if the source operand is legal. - if (!TLI.isTypeLegal(SrcVT)) + if (!isTypeLegal(SrcVT)) return false; unsigned InputReg = getRegForValue(I->getOperand(0)); @@ -1258,7 +1258,7 @@ EVT SrcEVT = TLI.getValueType(I->getOperand(0)->getType()); EVT DstEVT = TLI.getValueType(I->getType()); if (SrcEVT == MVT::Other || DstEVT == MVT::Other || - !TLI.isTypeLegal(SrcEVT) || !TLI.isTypeLegal(DstEVT)) + !isTypeLegal(SrcEVT) || !isTypeLegal(DstEVT)) // Unhandled type. Halt "fast" selection and bail. return false; @@ -1393,7 +1393,7 @@ if (VT.getSizeInBits() > 64) return false; EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); - if (!TLI.isTypeLegal(IntVT)) + if (!isTypeLegal(IntVT)) return false; unsigned IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), @@ -1427,7 +1427,7 @@ if (!RealVT.isSimple()) return false; MVT VT = RealVT.getSimpleVT(); - if (!TLI.isTypeLegal(VT) && VT != MVT::i1) + if (!isTypeLegal(VT) && VT != MVT::i1) return false; const Value *Op0 = EVI->getOperand(0); @@ -1998,7 +1998,7 @@ // use CreateRegs to create registers, so it always creates // exactly one register for each non-void instruction. EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true); - if (VT == MVT::Other || !TLI.isTypeLegal(VT)) { + if (VT == MVT::Other || !isTypeLegal(VT)) { // Handle integer promotions, though, because they're common and easy. if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) VT = TLI.getTypeToTransformTo(LLVMBB->getContext(), VT); Index: /home/seurer/llvm/llvm-oneoff/lib/Target/PowerPC/PPCFastISel.cpp =================================================================== --- /home/seurer/llvm/llvm-oneoff/lib/Target/PowerPC/PPCFastISel.cpp +++ /home/seurer/llvm/llvm-oneoff/lib/Target/PowerPC/PPCFastISel.cpp @@ -118,6 +118,7 @@ const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill); + bool isTypeLegal(EVT VT) const override; // Instruction selection routines. private: @@ -137,7 +138,8 @@ // Utility routines. private: - bool isTypeLegal(Type *Ty, MVT &VT); + bool isTypeLegalCommon(EVT Evt, MVT &VT) const; + bool isTypeLegal(Type *Ty, MVT &VT) const; bool isLoadTypeLegal(Type *Ty, MVT &VT); bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value, bool isZExt, unsigned DestReg); @@ -248,22 +250,41 @@ } } -// Determine whether the type Ty is simple enough to be handled by -// fast-isel, and return its equivalent machine type in VT. -// FIXME: Copied directly from ARM -- factor into base class? -bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) { - EVT Evt = TLI.getValueType(Ty, true); - +// Utility function for the following two functions that determines +// whether the extended value type Evt is simple enough to be handled +// by fast-isel. The equivalent machine type is returned in VT. +bool PPCFastISel::isTypeLegalCommon(EVT Evt, MVT &VT) const { // Only handle simple types. if (Evt == MVT::Other || !Evt.isSimple()) return false; + // Note: overwrites VT's (second parameter's) value VT = Evt.getSimpleVT(); + // FastISel can't handle VSX registers (yet). + // FIXME: remove when VSX support is added. + if (PPCSubTarget->hasVSX() && (VT.isVector() || VT == MVT::f64)) { + return false; + } + // Handle all legal types, i.e. a register that will directly hold this // value. return TLI.isTypeLegal(VT); } // Determine whether the type Ty is simple enough to be handled by +// fast-isel, and return its equivalent machine type in VT. +bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) const { + EVT Evt = TLI.getValueType(Ty, true); + return isTypeLegalCommon(Evt, VT); +} + +// Determine whether the extended value type Evt is simple enough to be handled +// by fast-isel. +bool PPCFastISel::isTypeLegal(EVT Evt) const { + MVT VT; + return isTypeLegalCommon(Evt, VT); +} + +// Determine whether the type Ty is simple enough to be handled by // fast-isel as a load target, and return its equivalent machine type in VT. bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { if (isTypeLegal(Ty, VT)) return true; @@ -1568,7 +1589,6 @@ } else { unsigned Reg = getRegForValue(RV); - if (Reg == 0) return false;