Index: lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
===================================================================
--- lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
+++ lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
@@ -182,19 +182,27 @@
     return;
   }
 
-  if (Imm == FloatToBits(1.0f) ||
-      Imm == FloatToBits(-1.0f) ||
-      Imm == FloatToBits(0.5f) ||
-      Imm == FloatToBits(-0.5f) ||
-      Imm == FloatToBits(2.0f) ||
-      Imm == FloatToBits(-2.0f) ||
-      Imm == FloatToBits(4.0f) ||
-      Imm == FloatToBits(-4.0f)) {
-    O << BitsToFloat(Imm);
-    return;
+  if (Imm == FloatToBits(0.0f))
+    O << "0.0";
+  else if (Imm == FloatToBits(1.0f))
+    O << "1.0";
+  else if (Imm == FloatToBits(-1.0f))
+    O << "-1.0";
+  else if (Imm == FloatToBits(0.5f))
+    O << "0.5";
+  else if (Imm == FloatToBits(-0.5f))
+    O << "-0.5";
+  else if (Imm == FloatToBits(2.0f))
+    O << "2.0";
+  else if (Imm == FloatToBits(-2.0f))
+    O << "-2.0";
+  else if (Imm == FloatToBits(4.0f))
+    O << "4.0";
+  else if (Imm == FloatToBits(-4.0f))
+    O << "-4.0";
+  else {
+    O << formatHex(static_cast<uint64_t>(Imm));
   }
-
-  O << formatHex(static_cast<uint64_t>(Imm));
 }
 
 void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
@@ -214,7 +222,12 @@
   } else if (Op.isImm()) {
     printImmediate(Op.getImm(), O);
   } else if (Op.isFPImm()) {
-    O << Op.getFPImm();
+
+    // We special case 0.0 because otherwise it will be printed as an integer.
+    if (Op.getFPImm() == 0.0)
+      O << "0.0";
+    else
+      printImmediate(FloatToBits(Op.getFPImm()), O);
   } else if (Op.isExpr()) {
     const MCExpr *Exp = Op.getExpr();
     Exp->print(O);
Index: test/CodeGen/R600/imm.ll
===================================================================
--- test/CodeGen/R600/imm.ll
+++ test/CodeGen/R600/imm.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
+; RUN: llc -march=r600 -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
 
 ; Use a 64-bit value with lo bits that can be represented as an inline constant
-; CHECK: @i64_imm_inline_lo
+; CHECK-LABEL: @i64_imm_inline_lo
 ; CHECK: S_MOV_B32 [[LO:s[0-9]+]], 5
 ; CHECK: V_MOV_B32_e32 v[[LO_VGPR:[0-9]+]], [[LO]]
 ; CHECK: BUFFER_STORE_DWORDX2 v{{\[}}[[LO_VGPR]]:
@@ -12,7 +12,7 @@
 }
 
 ; Use a 64-bit value with hi bits that can be represented as an inline constant
-; CHECK: @i64_imm_inline_hi
+; CHECK-LABEL: @i64_imm_inline_hi
 ; CHECK: S_MOV_B32 [[HI:s[0-9]+]], 5
 ; CHECK: V_MOV_B32_e32 v[[HI_VGPR:[0-9]+]], [[HI]]
 ; CHECK: BUFFER_STORE_DWORDX2 v{{\[[0-9]+:}}[[HI_VGPR]]
@@ -21,3 +21,173 @@
   store i64 21780256376, i64 addrspace(1) *%out ; 0x0000000512345678
   ret void
 }
+
+; CHECK-LABEL: @store_inline_imm_0.0_f32
+; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 0{{$}}
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @store_inline_imm_0.0_f32(float addrspace(1)* %out) {
+  store float 0.0, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @store_inline_imm_0.5_f32
+; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 0.5{{$}}
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @store_inline_imm_0.5_f32(float addrspace(1)* %out) {
+  store float 0.5, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @store_inline_imm_m_0.5_f32
+; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], -0.5{{$}}
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @store_inline_imm_m_0.5_f32(float addrspace(1)* %out) {
+  store float -0.5, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @store_inline_imm_1.0_f32
+; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 1.0{{$}}
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @store_inline_imm_1.0_f32(float addrspace(1)* %out) {
+  store float 1.0, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @store_inline_imm_m_1.0_f32
+; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], -1.0{{$}}
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @store_inline_imm_m_1.0_f32(float addrspace(1)* %out) {
+  store float -1.0, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @store_inline_imm_2.0_f32
+; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 2.0{{$}}
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @store_inline_imm_2.0_f32(float addrspace(1)* %out) {
+  store float 2.0, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @store_inline_imm_m_2.0_f32
+; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], -2.0{{$}}
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @store_inline_imm_m_2.0_f32(float addrspace(1)* %out) {
+  store float -2.0, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @store_inline_imm_4.0_f32
+; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 4.0{{$}}
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @store_inline_imm_4.0_f32(float addrspace(1)* %out) {
+  store float 4.0, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @store_inline_imm_m_4.0_f32
+; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], -4.0{{$}}
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @store_inline_imm_m_4.0_f32(float addrspace(1)* %out) {
+  store float -4.0, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @store_literal_imm_f32
+; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 0x45800000
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @store_literal_imm_f32(float addrspace(1)* %out) {
+  store float 4096.0, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @add_inline_imm_0.0_f32
+; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
+; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 0.0,
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @add_inline_imm_0.0_f32(float addrspace(1)* %out, float %x) {
+  %y = fadd float %x, 0.0
+  store float %y, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @add_inline_imm_0.5_f32
+; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
+; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 0.5,
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @add_inline_imm_0.5_f32(float addrspace(1)* %out, float %x) {
+  %y = fadd float %x, 0.5
+  store float %y, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @add_inline_imm_neg_0.5_f32
+; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
+; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -0.5,
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @add_inline_imm_neg_0.5_f32(float addrspace(1)* %out, float %x) {
+  %y = fadd float %x, -0.5
+  store float %y, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @add_inline_imm_1.0_f32
+; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
+; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 1.0,
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @add_inline_imm_1.0_f32(float addrspace(1)* %out, float %x) {
+  %y = fadd float %x, 1.0
+  store float %y, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @add_inline_imm_neg_1.0_f32
+; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
+; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -1.0,
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @add_inline_imm_neg_1.0_f32(float addrspace(1)* %out, float %x) {
+  %y = fadd float %x, -1.0
+  store float %y, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @add_inline_imm_2.0_f32
+; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
+; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 2.0,
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @add_inline_imm_2.0_f32(float addrspace(1)* %out, float %x) {
+  %y = fadd float %x, 2.0
+  store float %y, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @add_inline_imm_neg_2.0_f32
+; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
+; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -2.0,
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @add_inline_imm_neg_2.0_f32(float addrspace(1)* %out, float %x) {
+  %y = fadd float %x, -2.0
+  store float %y, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @add_inline_imm_4.0_f32
+; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
+; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], 4.0,
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @add_inline_imm_4.0_f32(float addrspace(1)* %out, float %x) {
+  %y = fadd float %x, 4.0
+  store float %y, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK-LABEL: @add_inline_imm_neg_4.0_f32
+; CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]]
+; CHECK: V_ADD_F32_e64 [[REG:v[0-9]+]], [[VAL]], -4.0,
+; CHECK-NEXT: BUFFER_STORE_DWORD [[REG]]
+define void @add_inline_imm_neg_4.0_f32(float addrspace(1)* %out, float %x) {
+  %y = fadd float %x, -4.0
+  store float %y, float addrspace(1)* %out
+  ret void
+}
Index: test/CodeGen/R600/uint_to_fp.ll
===================================================================
--- test/CodeGen/R600/uint_to_fp.ll
+++ test/CodeGen/R600/uint_to_fp.ll
@@ -49,7 +49,7 @@
 
 ; FUNC-LABEL: @uint_to_fp_i1_f32:
 ; SI: V_CMP_EQ_I32_e64 [[CMP:s\[[0-9]+:[0-9]\]]],
-; SI-NEXT: V_CNDMASK_B32_e64 [[RESULT:v[0-9]+]], 0, 1.000000e+00, [[CMP]]
+; SI-NEXT: V_CNDMASK_B32_e64 [[RESULT:v[0-9]+]], 0, 1.0, [[CMP]]
 ; SI: BUFFER_STORE_DWORD [[RESULT]],
 ; SI: S_ENDPGM
 define void @uint_to_fp_i1_f32(float addrspace(1)* %out, i32 %in) {