Index: llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -1010,7 +1010,7 @@
     }
   }
 
-  return DAG.getNode(WebAssemblyISD::SHUFFLE, DL, MVT::v16i8, Ops);
+  return DAG.getNode(WebAssemblyISD::SHUFFLE, DL, Op.getValueType(), Ops);
 }
 
 SDValue WebAssemblyTargetLowering::LowerShift(SDValue Op,
Index: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
===================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -350,7 +350,7 @@
             (v2f64 (SPLAT_v2f64 (f64 F64:$x0))), 1, F64:$x1))>;
 
 // Shuffle lanes: shuffle
-defm SHUFFLE_v16i8 :
+defm SHUFFLE :
   SIMD_I<(outs V128:$dst),
          (ins V128:$x, V128:$y,
            vec_i8imm_op:$m0, vec_i8imm_op:$m1,
@@ -384,7 +384,7 @@
 def wasm_shuffle_t : SDTypeProfile<1, 18, []>;
 def wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>;
 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
-def : Pat<(v16i8 (wasm_shuffle (vec_t V128:$x), (vec_t V128:$y),
+def : Pat<(vec_t (wasm_shuffle (vec_t V128:$x), (vec_t V128:$y),
             (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1),
             (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3),
             (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5),
@@ -393,7 +393,7 @@
             (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB),
             (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD),
             (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF))),
-          (v16i8 (SHUFFLE_v16i8 (vec_t V128:$x), (vec_t V128:$y),
+          (vec_t (SHUFFLE (vec_t V128:$x), (vec_t V128:$y),
             (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1),
             (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3),
             (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5),
Index: llvm/trunk/test/CodeGen/WebAssembly/simd-nested-shuffles.ll
===================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/simd-nested-shuffles.ll
+++ llvm/trunk/test/CodeGen/WebAssembly/simd-nested-shuffles.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -mattr=+simd128 | FileCheck %s --check-prefixes CHECK
+
+; Check that shuffles maintain their type when being custom
+; lowered. Regression test for bug 39275.
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
+target triple = "wasm32-unknown-unknown"
+
+; CHECK: v8x16.shuffle
+define <4 x i32> @foo(<4 x i32> %x) {
+  %1 = shufflevector <4 x i32> %x, <4 x i32> undef,
+    <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
+  %2 = shufflevector <4 x i32> %1, <4 x i32> undef,
+    <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
+  %3 = add <4 x i32> %2, %2
+  ret <4 x i32> %3
+}