Index: include/llvm/IR/IntrinsicsRISCV.td
===================================================================
--- include/llvm/IR/IntrinsicsRISCV.td
+++ include/llvm/IR/IntrinsicsRISCV.td
@@ -36,4 +36,24 @@
 def int_riscv_masked_atomicrmw_umax_i32 : MaskedAtomicRMW32Intrinsic;
 def int_riscv_masked_atomicrmw_umin_i32 : MaskedAtomicRMW32Intrinsic;
 
+class MaskedAtomicRMW64Intrinsic
+    : Intrinsic<[llvm_i64_ty],
+                [llvm_anyptr_ty, llvm_i64_ty, llvm_i64_ty, llvm_i64_ty],
+                [IntrArgMemOnly, NoCapture<0>]>;
+
+class MaskedAtomicRMW64WithSextIntrinsic
+    : Intrinsic<[llvm_i64_ty],
+                [llvm_anyptr_ty, llvm_i64_ty, llvm_i64_ty, llvm_i64_ty,
+                 llvm_i64_ty],
+                [IntrArgMemOnly, NoCapture<0>]>;
+
+def int_riscv_masked_atomicrmw_xchg_i64 : MaskedAtomicRMW64Intrinsic;
+def int_riscv_masked_atomicrmw_add_i64  : MaskedAtomicRMW64Intrinsic;
+def int_riscv_masked_atomicrmw_sub_i64  : MaskedAtomicRMW64Intrinsic;
+def int_riscv_masked_atomicrmw_nand_i64 : MaskedAtomicRMW64Intrinsic;
+def int_riscv_masked_atomicrmw_max_i64  : MaskedAtomicRMW64WithSextIntrinsic;
+def int_riscv_masked_atomicrmw_min_i64  : MaskedAtomicRMW64WithSextIntrinsic;
+def int_riscv_masked_atomicrmw_umax_i64 : MaskedAtomicRMW64Intrinsic;
+def int_riscv_masked_atomicrmw_umin_i64 : MaskedAtomicRMW64Intrinsic;
+
 } // TargetPrefix = "riscv"
Index: lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
===================================================================
--- lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -84,6 +84,9 @@
   case RISCV::PseudoAtomicLoadNand32:
     return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Nand, false, 32,
                              NextMBBI);
+  case RISCV::PseudoAtomicLoadNand64:
+    return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Nand, false, 64,
+                             NextMBBI);
   case RISCV::PseudoMaskedAtomicSwap32:
     return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Xchg, true, 32,
                              NextMBBI);
@@ -145,12 +148,61 @@
   }
 }
 
+static unsigned getLRForRMW64(AtomicOrdering Ordering) {
+  switch (Ordering) {
+  default:
+    llvm_unreachable("Unexpected AtomicOrdering");
+  case AtomicOrdering::Monotonic:
+    return RISCV::LR_D;
+  case AtomicOrdering::Acquire:
+    return RISCV::LR_D_AQ;
+  case AtomicOrdering::Release:
+    return RISCV::LR_D;
+  case AtomicOrdering::AcquireRelease:
+    return RISCV::LR_D_AQ;
+  case AtomicOrdering::SequentiallyConsistent:
+    return RISCV::LR_D_AQ_RL;
+  }
+}
+
+static unsigned getSCForRMW64(AtomicOrdering Ordering) {
+  switch (Ordering) {
+  default:
+    llvm_unreachable("Unexpected AtomicOrdering");
+  case AtomicOrdering::Monotonic:
+    return RISCV::SC_D;
+  case AtomicOrdering::Acquire:
+    return RISCV::SC_D;
+  case AtomicOrdering::Release:
+    return RISCV::SC_D_RL;
+  case AtomicOrdering::AcquireRelease:
+    return RISCV::SC_D_RL;
+  case AtomicOrdering::SequentiallyConsistent:
+    return RISCV::SC_D_AQ_RL;
+  }
+}
+
+static unsigned getLRForRMW(AtomicOrdering Ordering, int Width) {
+  if (Width == 32)
+    return getLRForRMW32(Ordering);
+  if (Width == 64)
+    return getLRForRMW64(Ordering);
+  llvm_unreachable("Unexpected LR width\n");
+}
+
+static unsigned getSCForRMW(AtomicOrdering Ordering, int Width) {
+  if (Width == 32)
+    return getSCForRMW32(Ordering);
+  if (Width == 64)
+    return getSCForRMW64(Ordering);
+  llvm_unreachable("Unexpected SC width\n");
+}
+
 static void doAtomicBinOpExpansion(const RISCVInstrInfo *TII, MachineInstr &MI,
                                    DebugLoc DL, MachineBasicBlock *ThisMBB,
                                    MachineBasicBlock *LoopMBB,
                                    MachineBasicBlock *DoneMBB,
                                    AtomicRMWInst::BinOp BinOp, int Width) {
-  assert(Width == 32 && "RV64 atomic expansion currently unsupported");
   unsigned DestReg = MI.getOperand(0).getReg();
   unsigned ScratchReg = MI.getOperand(1).getReg();
   unsigned AddrReg = MI.getOperand(2).getReg();
@@ -159,11 +211,11 @@
       static_cast<AtomicOrdering>(MI.getOperand(4).getImm());
 
   // .loop:
-  //   lr.w dest, (addr)
+  //   lr.[w|d] dest, (addr)
   //   binop scratch, dest, val
-  //   sc.w scratch, scratch, (addr)
+  //   sc.[w|d] scratch, scratch, (addr)
   //   bnez scratch, loop
-  BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg)
+  BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg)
       .addReg(AddrReg);
   switch (BinOp) {
   default:
@@ -177,7 +229,7 @@
         .addImm(-1);
     break;
   }
-  BuildMI(LoopMBB, DL, TII->get(getSCForRMW32(Ordering)), ScratchReg)
+  BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg)
       .addReg(AddrReg)
       .addReg(ScratchReg);
   BuildMI(LoopMBB, DL, TII->get(RISCV::BNE))
Index: lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- lib/Target/RISCV/RISCVISelLowering.cpp
+++ lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1653,37 +1653,74 @@
 }
 
 static Intrinsic::ID
-getIntrinsicForMaskedAtomicRMWBinOp32(AtomicRMWInst::BinOp BinOp) {
-  switch (BinOp) {
-  default:
-    llvm_unreachable("Unexpected AtomicRMW BinOp");
-  case AtomicRMWInst::Xchg:
-    return Intrinsic::riscv_masked_atomicrmw_xchg_i32;
-  case AtomicRMWInst::Add:
-    return Intrinsic::riscv_masked_atomicrmw_add_i32;
-  case AtomicRMWInst::Sub:
-    return Intrinsic::riscv_masked_atomicrmw_sub_i32;
-  case AtomicRMWInst::Nand:
-    return Intrinsic::riscv_masked_atomicrmw_nand_i32;
-  case AtomicRMWInst::Max:
-    return Intrinsic::riscv_masked_atomicrmw_max_i32;
-  case AtomicRMWInst::Min:
-    return Intrinsic::riscv_masked_atomicrmw_min_i32;
-  case AtomicRMWInst::UMax:
-    return Intrinsic::riscv_masked_atomicrmw_umax_i32;
-  case AtomicRMWInst::UMin:
-    return Intrinsic::riscv_masked_atomicrmw_umin_i32;
+getIntrinsicForMaskedAtomicRMWBinOp(unsigned XLen, AtomicRMWInst::BinOp BinOp) {
+  if (XLen == 32) {
+    switch (BinOp) {
+    default:
+      llvm_unreachable("Unexpected AtomicRMW BinOp");
+    case AtomicRMWInst::Xchg:
+      return Intrinsic::riscv_masked_atomicrmw_xchg_i32;
+    case AtomicRMWInst::Add:
+      return Intrinsic::riscv_masked_atomicrmw_add_i32;
+    case AtomicRMWInst::Sub:
+      return Intrinsic::riscv_masked_atomicrmw_sub_i32;
+    case AtomicRMWInst::Nand:
+      return Intrinsic::riscv_masked_atomicrmw_nand_i32;
+    case AtomicRMWInst::Max:
+      return Intrinsic::riscv_masked_atomicrmw_max_i32;
+    case AtomicRMWInst::Min:
+      return Intrinsic::riscv_masked_atomicrmw_min_i32;
+    case AtomicRMWInst::UMax:
+      return Intrinsic::riscv_masked_atomicrmw_umax_i32;
+    case AtomicRMWInst::UMin:
+      return Intrinsic::riscv_masked_atomicrmw_umin_i32;
+    }
+  }
+
+  if (XLen == 64) {
+    switch (BinOp) {
+    default:
+      llvm_unreachable("Unexpected AtomicRMW BinOp");
+    case AtomicRMWInst::Xchg:
+      return Intrinsic::riscv_masked_atomicrmw_xchg_i64;
+    case AtomicRMWInst::Add:
+      return Intrinsic::riscv_masked_atomicrmw_add_i64;
+    case AtomicRMWInst::Sub:
+      return Intrinsic::riscv_masked_atomicrmw_sub_i64;
+    case AtomicRMWInst::Nand:
+      return Intrinsic::riscv_masked_atomicrmw_nand_i64;
+    case AtomicRMWInst::Max:
+      return Intrinsic::riscv_masked_atomicrmw_max_i64;
+    case AtomicRMWInst::Min:
+      return Intrinsic::riscv_masked_atomicrmw_min_i64;
+    case AtomicRMWInst::UMax:
+      return Intrinsic::riscv_masked_atomicrmw_umax_i64;
+    case AtomicRMWInst::UMin:
+      return Intrinsic::riscv_masked_atomicrmw_umin_i64;
+    }
   }
+
+  llvm_unreachable("Unexpected XLen\n");
 }
 
 Value *RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(
     IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr,
     Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const {
-  Value *Ordering = Builder.getInt32(static_cast<uint32_t>(AI->getOrdering()));
+  unsigned XLen = Subtarget.getXLen();
+  Value *Ordering =
+      Builder.getIntN(XLen, static_cast<uint64_t>(AI->getOrdering()));
   Type *Tys[] = {AlignedAddr->getType()};
   Function *LrwOpScwLoop = Intrinsic::getDeclaration(
       AI->getModule(),
-      getIntrinsicForMaskedAtomicRMWBinOp32(AI->getOperation()), Tys);
+      getIntrinsicForMaskedAtomicRMWBinOp(XLen, AI->getOperation()), Tys);
+
+  if (XLen == 64) {
+    Incr = Builder.CreateSExt(Incr, Builder.getInt64Ty());
+    Mask = Builder.CreateSExt(Mask, Builder.getInt64Ty());
+    ShiftAmt = Builder.CreateSExt(ShiftAmt, Builder.getInt64Ty());
+  }
+
+  Value *Result;
 
   // Must pass the shift amount needed to sign extend the loaded value prior
   // to performing a signed comparison for min/max. ShiftAmt is the number of
@@ -1695,11 +1732,16 @@
     const DataLayout &DL = AI->getModule()->getDataLayout();
     unsigned ValWidth =
         DL.getTypeStoreSizeInBits(AI->getValOperand()->getType());
-    Value *SextShamt = Builder.CreateSub(
-        Builder.getInt32(Subtarget.getXLen() - ValWidth), ShiftAmt);
-    return Builder.CreateCall(LrwOpScwLoop,
-                              {AlignedAddr, Incr, Mask, SextShamt, Ordering});
+    Value *SextShamt =
+        Builder.CreateSub(Builder.getIntN(XLen, XLen - ValWidth), ShiftAmt);
+    Result = Builder.CreateCall(LrwOpScwLoop,
+                                {AlignedAddr, Incr, Mask, SextShamt, Ordering});
+  } else {
+    Result =
+        Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, Ordering});
   }
 
-  return Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, Ordering});
+  if (XLen == 64)
+    Result = Builder.CreateTrunc(Result, Builder.getInt32Ty());
+  return Result;
 }
Index: lib/Target/RISCV/RISCVInstrInfoA.td
===================================================================
--- lib/Target/RISCV/RISCVInstrInfoA.td
+++ lib/Target/RISCV/RISCVInstrInfoA.td
@@ -153,7 +153,7 @@
 }
 
 def PseudoAtomicLoadNand32 : PseudoAMO;
-// Ordering constants must be kept in sync with the AtomicOrdering enum in 
+// Ordering constants must be kept in sync with the AtomicOrdering enum in
 // AtomicOrdering.h.
 def : Pat<(atomic_load_nand_32_monotonic GPR:$addr, GPR:$incr),
           (PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 2)>;
@@ -231,3 +231,60 @@
 def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umin_i32,
                          PseudoMaskedAtomicLoadUMin32>;
 } // Predicates = [HasStdExtA]
+
+let Predicates = [HasStdExtA, IsRV64] in {
+defm : LdPat<atomic_load_64, LD>;
+defm : AtomicStPat<atomic_store_64, SD, GPR>;
+
+defm : AMOPat<"atomic_swap_64", "AMOSWAP_D">;
+defm : AMOPat<"atomic_load_add_64", "AMOADD_D">;
+defm : AMOPat<"atomic_load_and_64", "AMOAND_D">;
+defm : AMOPat<"atomic_load_or_64", "AMOOR_D">;
+defm : AMOPat<"atomic_load_xor_64", "AMOXOR_D">;
+defm : AMOPat<"atomic_load_max_64", "AMOMAX_D">;
+defm : AMOPat<"atomic_load_min_64", "AMOMIN_D">;
+defm : AMOPat<"atomic_load_umax_64", "AMOMAXU_D">;
+defm : AMOPat<"atomic_load_umin_64", "AMOMINU_D">;
+
+def : Pat<(atomic_load_sub_64_monotonic GPR:$addr, GPR:$incr),
+          (AMOADD_D GPR:$addr, (SUB X0, GPR:$incr))>;
+def : Pat<(atomic_load_sub_64_acquire GPR:$addr, GPR:$incr),
+          (AMOADD_D_AQ GPR:$addr, (SUB X0, GPR:$incr))>;
+def : Pat<(atomic_load_sub_64_release GPR:$addr, GPR:$incr),
+          (AMOADD_D_RL GPR:$addr, (SUB X0, GPR:$incr))>;
+def : Pat<(atomic_load_sub_64_acq_rel GPR:$addr, GPR:$incr),
+          (AMOADD_D_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
+def : Pat<(atomic_load_sub_64_seq_cst GPR:$addr, GPR:$incr),
+          (AMOADD_D_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
+
+def PseudoAtomicLoadNand64 : PseudoAMO;
+// Ordering constants must be kept in sync with the AtomicOrdering enum in
+// AtomicOrdering.h.
+def : Pat<(atomic_load_nand_64_monotonic GPR:$addr, GPR:$incr),
+          (PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 2)>;
+def : Pat<(atomic_load_nand_64_acquire GPR:$addr, GPR:$incr),
+          (PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 4)>;
+def : Pat<(atomic_load_nand_64_release GPR:$addr, GPR:$incr),
+          (PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 5)>;
+def : Pat<(atomic_load_nand_64_acq_rel GPR:$addr, GPR:$incr),
+          (PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 6)>;
+def : Pat<(atomic_load_nand_64_seq_cst GPR:$addr, GPR:$incr),
+          (PseudoAtomicLoadNand64 GPR:$addr, GPR:$incr, 7)>;
+
+def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_xchg_i64,
+                         PseudoMaskedAtomicSwap32>;
+def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_add_i64,
+                         PseudoMaskedAtomicLoadAdd32>;
+def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_sub_i64,
+                         PseudoMaskedAtomicLoadSub32>;
+def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_nand_i64,
+                         PseudoMaskedAtomicLoadNand32>;
+def : PseudoMaskedAMOMinMaxPat<int_riscv_masked_atomicrmw_max_i64,
+                               PseudoMaskedAtomicLoadMax32>;
+def : PseudoMaskedAMOMinMaxPat<int_riscv_masked_atomicrmw_min_i64,
+                               PseudoMaskedAtomicLoadMin32>;
+def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umax_i64,
+                         PseudoMaskedAtomicLoadUMax32>;
+def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umin_i64,
+                         PseudoMaskedAtomicLoadUMin32>;
+} // Predicates = [HasStdExtA, IsRV64]
Index: test/CodeGen/RISCV/atomic-load-store.ll
===================================================================
--- test/CodeGen/RISCV/atomic-load-store.ll
+++ test/CodeGen/RISCV/atomic-load-store.ll
@@ -3,6 +3,10 @@
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IA %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64I %s
+; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64IA %s
 
 define i8 @atomic_load_i8_unordered(i8 *%a) nounwind {
 ; RV32I-LABEL: atomic_load_i8_unordered:
@@ -19,6 +23,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    lb a0, 0(a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_load_i8_unordered:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a1, zero
+; RV64I-NEXT:    call __atomic_load_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_load_i8_unordered:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lb a0, 0(a0)
+; RV64IA-NEXT:    ret
   %1 = load atomic i8, i8* %a unordered, align 1
   ret i8 %1
 }
@@ -38,6 +57,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    lb a0, 0(a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_load_i8_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a1, zero
+; RV64I-NEXT:    call __atomic_load_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_load_i8_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lb a0, 0(a0)
+; RV64IA-NEXT:    ret
   %1 = load atomic i8, i8* %a monotonic, align 1
   ret i8 %1
 }
@@ -58,6 +92,22 @@
 ; RV32IA-NEXT:    lb a0, 0(a0)
 ; RV32IA-NEXT:    fence r, rw
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_load_i8_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a1, zero, 2
+; RV64I-NEXT:    call __atomic_load_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_load_i8_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lb a0, 0(a0)
+; RV64IA-NEXT:    fence r, rw
+; RV64IA-NEXT:    ret
   %1 = load atomic i8, i8* %a acquire, align 1
   ret i8 %1
 }
@@ -79,6 +129,23 @@
 ; RV32IA-NEXT:    lb a0, 0(a0)
 ; RV32IA-NEXT:    fence r, rw
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_load_i8_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a1, zero, 5
+; RV64I-NEXT:    call __atomic_load_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_load_i8_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    fence rw, rw
+; RV64IA-NEXT:    lb a0, 0(a0)
+; RV64IA-NEXT:    fence r, rw
+; RV64IA-NEXT:    ret
   %1 = load atomic i8, i8* %a seq_cst, align 1
   ret i8 %1
 }
@@ -98,6 +165,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    lh a0, 0(a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_load_i16_unordered:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a1, zero
+; RV64I-NEXT:    call __atomic_load_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_load_i16_unordered:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lh a0, 0(a0)
+; RV64IA-NEXT:    ret
   %1 = load atomic i16, i16* %a unordered, align 2
   ret i16 %1
 }
@@ -117,6 +199,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    lh a0, 0(a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_load_i16_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a1, zero
+; RV64I-NEXT:    call __atomic_load_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_load_i16_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lh a0, 0(a0)
+; RV64IA-NEXT:    ret
   %1 = load atomic i16, i16* %a monotonic, align 2
   ret i16 %1
 }
@@ -137,6 +234,22 @@
 ; RV32IA-NEXT:    lh a0, 0(a0)
 ; RV32IA-NEXT:    fence r, rw
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_load_i16_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a1, zero, 2
+; RV64I-NEXT:    call __atomic_load_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_load_i16_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lh a0, 0(a0)
+; RV64IA-NEXT:    fence r, rw
+; RV64IA-NEXT:    ret
   %1 = load atomic i16, i16* %a acquire, align 2
   ret i16 %1
 }
@@ -158,6 +271,23 @@
 ; RV32IA-NEXT:    lh a0, 0(a0)
 ; RV32IA-NEXT:    fence r, rw
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_load_i16_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a1, zero, 5
+; RV64I-NEXT:    call __atomic_load_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_load_i16_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    fence rw, rw
+; RV64IA-NEXT:    lh a0, 0(a0)
+; RV64IA-NEXT:    fence r, rw
+; RV64IA-NEXT:    ret
   %1 = load atomic i16, i16* %a seq_cst, align 2
   ret i16 %1
 }
@@ -177,6 +307,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    lw a0, 0(a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_load_i32_unordered:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a1, zero
+; RV64I-NEXT:    call __atomic_load_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_load_i32_unordered:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lw a0, 0(a0)
+; RV64IA-NEXT:    ret
   %1 = load atomic i32, i32* %a unordered, align 4
   ret i32 %1
 }
@@ -196,6 +341,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    lw a0, 0(a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_load_i32_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a1, zero
+; RV64I-NEXT:    call __atomic_load_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_load_i32_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lw a0, 0(a0)
+; RV64IA-NEXT:    ret
   %1 = load atomic i32, i32* %a monotonic, align 4
   ret i32 %1
 }
@@ -216,6 +376,22 @@
 ; RV32IA-NEXT:    lw a0, 0(a0)
 ; RV32IA-NEXT:    fence r, rw
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_load_i32_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a1, zero, 2
+; RV64I-NEXT:    call __atomic_load_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_load_i32_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lw a0, 0(a0)
+; RV64IA-NEXT:    fence r, rw
+; RV64IA-NEXT:    ret
   %1 = load atomic i32, i32* %a acquire, align 4
   ret i32 %1
 }
@@ -237,6 +413,23 @@
 ; RV32IA-NEXT:    lw a0, 0(a0)
 ; RV32IA-NEXT:    fence r, rw
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_load_i32_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a1, zero, 5
+; RV64I-NEXT:    call __atomic_load_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_load_i32_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    fence rw, rw
+; RV64IA-NEXT:    lw a0, 0(a0)
+; RV64IA-NEXT:    fence r, rw
+; RV64IA-NEXT:    ret
   %1 = load atomic i32, i32* %a seq_cst, align 4
   ret i32 %1
 }
@@ -261,6 +454,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_load_i64_unordered:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a1, zero
+; RV64I-NEXT:    call __atomic_load_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_load_i64_unordered:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    ld a0, 0(a0)
+; RV64IA-NEXT:    ret
   %1 = load atomic i64, i64* %a unordered, align 8
   ret i64 %1
 }
@@ -285,6 +493,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_load_i64_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a1, zero
+; RV64I-NEXT:    call __atomic_load_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_load_i64_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    ld a0, 0(a0)
+; RV64IA-NEXT:    ret
   %1 = load atomic i64, i64* %a monotonic, align 8
   ret i64 %1
 }
@@ -309,6 +532,22 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_load_i64_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a1, zero, 2
+; RV64I-NEXT:    call __atomic_load_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_load_i64_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    ld a0, 0(a0)
+; RV64IA-NEXT:    fence r, rw
+; RV64IA-NEXT:    ret
   %1 = load atomic i64, i64* %a acquire, align 8
   ret i64 %1
 }
@@ -333,6 +572,23 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_load_i64_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a1, zero, 5
+; RV64I-NEXT:    call __atomic_load_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_load_i64_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    fence rw, rw
+; RV64IA-NEXT:    ld a0, 0(a0)
+; RV64IA-NEXT:    fence r, rw
+; RV64IA-NEXT:    ret
   %1 = load atomic i64, i64* %a seq_cst, align 8
   ret i64 %1
 }
@@ -352,6 +608,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    sb a1, 0(a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_store_i8_unordered:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_store_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_store_i8_unordered:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    sb a1, 0(a0)
+; RV64IA-NEXT:    ret
   store atomic i8 %b, i8* %a unordered, align 1
   ret void
 }
@@ -371,6 +642,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    sb a1, 0(a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_store_i8_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_store_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_store_i8_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    sb a1, 0(a0)
+; RV64IA-NEXT:    ret
   store atomic i8 %b, i8* %a monotonic, align 1
   ret void
 }
@@ -391,6 +677,22 @@
 ; RV32IA-NEXT:    fence rw, w
 ; RV32IA-NEXT:    sb a1, 0(a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_store_i8_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_store_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_store_i8_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    fence rw, w
+; RV64IA-NEXT:    sb a1, 0(a0)
+; RV64IA-NEXT:    ret
   store atomic i8 %b, i8* %a release, align 1
   ret void
 }
@@ -411,6 +713,22 @@
 ; RV32IA-NEXT:    fence rw, w
 ; RV32IA-NEXT:    sb a1, 0(a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_store_i8_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_store_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_store_i8_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    fence rw, w
+; RV64IA-NEXT:    sb a1, 0(a0)
+; RV64IA-NEXT:    ret
   store atomic i8 %b, i8* %a seq_cst, align 1
   ret void
 }
@@ -430,6 +748,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    sh a1, 0(a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_store_i16_unordered:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_store_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_store_i16_unordered:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    sh a1, 0(a0)
+; RV64IA-NEXT:    ret
   store atomic i16 %b, i16* %a unordered, align 2
   ret void
 }
@@ -449,6 +782,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    sh a1, 0(a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_store_i16_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_store_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_store_i16_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    sh a1, 0(a0)
+; RV64IA-NEXT:    ret
   store atomic i16 %b, i16* %a monotonic, align 2
   ret void
 }
@@ -469,6 +817,22 @@
 ; RV32IA-NEXT:    fence rw, w
 ; RV32IA-NEXT:    sh a1, 0(a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_store_i16_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_store_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_store_i16_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    fence rw, w
+; RV64IA-NEXT:    sh a1, 0(a0)
+; RV64IA-NEXT:    ret
   store atomic i16 %b, i16* %a release, align 2
   ret void
 }
@@ -489,6 +853,22 @@
 ; RV32IA-NEXT:    fence rw, w
 ; RV32IA-NEXT:    sh a1, 0(a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_store_i16_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_store_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_store_i16_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    fence rw, w
+; RV64IA-NEXT:    sh a1, 0(a0)
+; RV64IA-NEXT:    ret
   store atomic i16 %b, i16* %a seq_cst, align 2
   ret void
 }
@@ -508,6 +888,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    sw a1, 0(a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_store_i32_unordered:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_store_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_store_i32_unordered:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    sw a1, 0(a0)
+; RV64IA-NEXT:    ret
   store atomic i32 %b, i32* %a unordered, align 4
   ret void
 }
@@ -527,6 +922,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    sw a1, 0(a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_store_i32_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_store_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_store_i32_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    sw a1, 0(a0)
+; RV64IA-NEXT:    ret
   store atomic i32 %b, i32* %a monotonic, align 4
   ret void
 }
@@ -547,6 +957,22 @@
 ; RV32IA-NEXT:    fence rw, w
 ; RV32IA-NEXT:    sw a1, 0(a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_store_i32_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_store_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_store_i32_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    fence rw, w
+; RV64IA-NEXT:    sw a1, 0(a0)
+; RV64IA-NEXT:    ret
   store atomic i32 %b, i32* %a release, align 4
   ret void
 }
@@ -567,6 +993,22 @@
 ; RV32IA-NEXT:    fence rw, w
 ; RV32IA-NEXT:    sw a1, 0(a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_store_i32_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_store_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_store_i32_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    fence rw, w
+; RV64IA-NEXT:    sw a1, 0(a0)
+; RV64IA-NEXT:    ret
   store atomic i32 %b, i32* %a seq_cst, align 4
   ret void
 }
@@ -591,6 +1033,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_store_i64_unordered:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_store_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_store_i64_unordered:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    sd a1, 0(a0)
+; RV64IA-NEXT:    ret
   store atomic i64 %b, i64* %a unordered, align 8
   ret void
 }
@@ -615,6 +1072,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_store_i64_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_store_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_store_i64_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    sd a1, 0(a0)
+; RV64IA-NEXT:    ret
   store atomic i64 %b, i64* %a monotonic, align 8
   ret void
 }
@@ -639,6 +1111,22 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_store_i64_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_store_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_store_i64_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    fence rw, w
+; RV64IA-NEXT:    sd a1, 0(a0)
+; RV64IA-NEXT:    ret
   store atomic i64 %b, i64* %a release, align 8
   ret void
 }
@@ -663,6 +1151,22 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomic_store_i64_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_store_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomic_store_i64_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    fence rw, w
+; RV64IA-NEXT:    sd a1, 0(a0)
+; RV64IA-NEXT:    ret
   store atomic i64 %b, i64* %a seq_cst, align 8
   ret void
 }
Index: test/CodeGen/RISCV/atomic-rmw.ll
===================================================================
--- test/CodeGen/RISCV/atomic-rmw.ll
+++ test/CodeGen/RISCV/atomic-rmw.ll
@@ -3,6 +3,10 @@
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IA %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64I %s
+; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64IA %s
 
 define i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) {
 ; RV32I-LABEL: atomicrmw_xchg_i8_monotonic:
@@ -35,6 +39,37 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xchg_i8_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_exchange_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xchg_i8_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a3, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB0_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    add a5, zero, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a3
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB0_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i8* %a, i8 %b monotonic
   ret i8 %1
 }
@@ -70,6 +105,37 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xchg_i8_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_exchange_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xchg_i8_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a3, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB1_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    add a5, zero, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a3
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB1_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i8* %a, i8 %b acquire
   ret i8 %1
 }
@@ -105,6 +171,37 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xchg_i8_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_exchange_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xchg_i8_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a3, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB2_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    add a5, zero, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a3
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB2_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i8* %a, i8 %b release
   ret i8 %1
 }
@@ -140,6 +237,37 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xchg_i8_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_exchange_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xchg_i8_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a3, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB3_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    add a5, zero, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a3
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB3_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i8* %a, i8 %b acq_rel
   ret i8 %1
 }
@@ -175,6 +303,37 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xchg_i8_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_exchange_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xchg_i8_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a3, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB4_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aqrl a4, (a0)
+; RV64IA-NEXT:    add a5, zero, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a3
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB4_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i8* %a, i8 %b seq_cst
   ret i8 %1
 }
@@ -210,6 +369,37 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_add_i8_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_add_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_add_i8_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a3, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB5_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    add a5, a4, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a3
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB5_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw add i8* %a, i8 %b monotonic
   ret i8 %1
 }
@@ -245,6 +435,37 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_add_i8_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_add_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_add_i8_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a3, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB6_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    add a5, a4, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a3
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB6_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw add i8* %a, i8 %b acquire
   ret i8 %1
 }
@@ -280,6 +501,37 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_add_i8_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_add_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_add_i8_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a3, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB7_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    add a5, a4, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a3
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB7_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw add i8* %a, i8 %b release
   ret i8 %1
 }
@@ -315,6 +567,37 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_add_i8_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_add_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_add_i8_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a3, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB8_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    add a5, a4, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a3
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB8_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw add i8* %a, i8 %b acq_rel
   ret i8 %1
 }
@@ -350,6 +633,37 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_add_i8_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_add_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_add_i8_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a3, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB9_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aqrl a4, (a0)
+; RV64IA-NEXT:    add a5, a4, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a3
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB9_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw add i8* %a, i8 %b seq_cst
   ret i8 %1
 }
@@ -385,6 +699,37 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_sub_i8_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_sub_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_sub_i8_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a3, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB10_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    sub a5, a4, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a3
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB10_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i8* %a, i8 %b monotonic
   ret i8 %1
 }
@@ -420,6 +765,37 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_sub_i8_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_sub_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_sub_i8_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a3, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB11_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    sub a5, a4, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a3
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB11_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i8* %a, i8 %b acquire
   ret i8 %1
 }
@@ -455,6 +831,37 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_sub_i8_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_sub_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_sub_i8_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a3, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB12_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    sub a5, a4, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a3
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB12_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i8* %a, i8 %b release
   ret i8 %1
 }
@@ -490,6 +897,37 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_sub_i8_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_sub_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_sub_i8_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a3, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB13_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    sub a5, a4, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a3
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB13_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i8* %a, i8 %b acq_rel
   ret i8 %1
 }
@@ -525,6 +963,37 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_sub_i8_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_sub_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_sub_i8_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a3, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB14_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aqrl a4, (a0)
+; RV64IA-NEXT:    sub a5, a4, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a3
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB14_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i8* %a, i8 %b seq_cst
   ret i8 %1
 }
@@ -554,6 +1023,31 @@
 ; RV32IA-NEXT:    amoand.w a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_and_i8_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_and_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_and_i8_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sll a3, a3, a2
+; RV64IA-NEXT:    not a3, a3
+; RV64IA-NEXT:    or a1, a3, a1
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoand.w a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw and i8* %a, i8 %b monotonic
   ret i8 %1
 }
@@ -583,6 +1077,31 @@
 ; RV32IA-NEXT:    amoand.w.aq a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_and_i8_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_and_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_and_i8_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sll a3, a3, a2
+; RV64IA-NEXT:    not a3, a3
+; RV64IA-NEXT:    or a1, a3, a1
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoand.w.aq a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw and i8* %a, i8 %b acquire
   ret i8 %1
 }
@@ -612,6 +1131,31 @@
 ; RV32IA-NEXT:    amoand.w.rl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_and_i8_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_and_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_and_i8_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sll a3, a3, a2
+; RV64IA-NEXT:    not a3, a3
+; RV64IA-NEXT:    or a1, a3, a1
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoand.w.rl a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw and i8* %a, i8 %b release
   ret i8 %1
 }
@@ -641,6 +1185,31 @@
 ; RV32IA-NEXT:    amoand.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_and_i8_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_and_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_and_i8_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sll a3, a3, a2
+; RV64IA-NEXT:    not a3, a3
+; RV64IA-NEXT:    or a1, a3, a1
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoand.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw and i8* %a, i8 %b acq_rel
   ret i8 %1
 }
@@ -670,6 +1239,31 @@
 ; RV32IA-NEXT:    amoand.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_and_i8_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_and_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_and_i8_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sll a3, a3, a2
+; RV64IA-NEXT:    not a3, a3
+; RV64IA-NEXT:    or a1, a3, a1
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoand.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw and i8* %a, i8 %b seq_cst
   ret i8 %1
 }
@@ -706,6 +1300,38 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_nand_i8_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_nand_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_nand_i8_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a3, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB20_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    and a5, a4, a1
+; RV64IA-NEXT:    not a5, a5
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a3
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB20_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i8* %a, i8 %b monotonic
   ret i8 %1
 }
@@ -742,6 +1368,38 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_nand_i8_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_nand_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_nand_i8_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a3, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB21_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    and a5, a4, a1
+; RV64IA-NEXT:    not a5, a5
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a3
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB21_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i8* %a, i8 %b acquire
   ret i8 %1
 }
@@ -778,6 +1436,38 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_nand_i8_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_nand_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_nand_i8_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a3, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB22_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    and a5, a4, a1
+; RV64IA-NEXT:    not a5, a5
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a3
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB22_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i8* %a, i8 %b release
   ret i8 %1
 }
@@ -814,6 +1504,38 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_nand_i8_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_nand_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_nand_i8_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a3, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB23_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    and a5, a4, a1
+; RV64IA-NEXT:    not a5, a5
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a3
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB23_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i8* %a, i8 %b acq_rel
   ret i8 %1
 }
@@ -850,6 +1572,38 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_nand_i8_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_nand_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_nand_i8_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a3, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB24_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aqrl a4, (a0)
+; RV64IA-NEXT:    and a5, a4, a1
+; RV64IA-NEXT:    not a5, a5
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a3
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB24_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i8* %a, i8 %b seq_cst
   ret i8 %1
 }
@@ -875,6 +1629,27 @@
 ; RV32IA-NEXT:    amoor.w a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_or_i8_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_or_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_or_i8_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoor.w a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw or i8* %a, i8 %b monotonic
   ret i8 %1
 }
@@ -900,6 +1675,27 @@
 ; RV32IA-NEXT:    amoor.w.aq a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_or_i8_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_or_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_or_i8_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoor.w.aq a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw or i8* %a, i8 %b acquire
   ret i8 %1
 }
@@ -925,6 +1721,27 @@
 ; RV32IA-NEXT:    amoor.w.rl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_or_i8_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_or_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_or_i8_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoor.w.rl a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw or i8* %a, i8 %b release
   ret i8 %1
 }
@@ -950,6 +1767,27 @@
 ; RV32IA-NEXT:    amoor.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_or_i8_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_or_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_or_i8_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoor.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw or i8* %a, i8 %b acq_rel
   ret i8 %1
 }
@@ -975,6 +1813,27 @@
 ; RV32IA-NEXT:    amoor.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_or_i8_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_or_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_or_i8_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoor.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw or i8* %a, i8 %b seq_cst
   ret i8 %1
 }
@@ -1000,6 +1859,27 @@
 ; RV32IA-NEXT:    amoxor.w a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xor_i8_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_xor_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xor_i8_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoxor.w a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i8* %a, i8 %b monotonic
   ret i8 %1
 }
@@ -1025,6 +1905,27 @@
 ; RV32IA-NEXT:    amoxor.w.aq a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xor_i8_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_xor_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xor_i8_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoxor.w.aq a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i8* %a, i8 %b acquire
   ret i8 %1
 }
@@ -1050,6 +1951,27 @@
 ; RV32IA-NEXT:    amoxor.w.rl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xor_i8_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_xor_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xor_i8_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoxor.w.rl a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i8* %a, i8 %b release
   ret i8 %1
 }
@@ -1075,6 +1997,27 @@
 ; RV32IA-NEXT:    amoxor.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xor_i8_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_xor_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xor_i8_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoxor.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i8* %a, i8 %b acq_rel
   ret i8 %1
 }
@@ -1100,6 +2043,27 @@
 ; RV32IA-NEXT:    amoxor.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xor_i8_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_xor_1
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xor_i8_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoxor.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i8* %a, i8 %b seq_cst
   ret i8 %1
 }
@@ -1177,6 +2141,79 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_max_i8_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    slli a1, a1, 56
+; RV64I-NEXT:    srai s1, a1, 56
+; RV64I-NEXT:    addi s3, sp, 7
+; RV64I-NEXT:  .LBB35_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    slli a1, a0, 56
+; RV64I-NEXT:    srai a1, a1, 56
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    blt s1, a1, .LBB35_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB35_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB35_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB35_1 Depth=1
+; RV64I-NEXT:    sb a0, 7(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, zero
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_1
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lb a0, 7(sp)
+; RV64I-NEXT:    beqz a1, .LBB35_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_max_i8_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 56
+; RV64IA-NEXT:    sub a6, a3, a2
+; RV64IA-NEXT:    addi a4, zero, 255
+; RV64IA-NEXT:    sllw a7, a4, a2
+; RV64IA-NEXT:    slli a1, a1, 56
+; RV64IA-NEXT:    srai a1, a1, 56
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB35_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a5, (a0)
+; RV64IA-NEXT:    and a4, a5, a7
+; RV64IA-NEXT:    mv a3, a5
+; RV64IA-NEXT:    sll a4, a4, a6
+; RV64IA-NEXT:    sra a4, a4, a6
+; RV64IA-NEXT:    bge a4, a1, .LBB35_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB35_1 Depth=1
+; RV64IA-NEXT:    xor a3, a5, a1
+; RV64IA-NEXT:    and a3, a3, a7
+; RV64IA-NEXT:    xor a3, a5, a3
+; RV64IA-NEXT:  .LBB35_3: # in Loop: Header=BB35_1 Depth=1
+; RV64IA-NEXT:    sc.w a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB35_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a5, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw max i8* %a, i8 %b monotonic
   ret i8 %1
 }
@@ -1257,6 +2294,82 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_max_i8_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    slli a1, a1, 56
+; RV64I-NEXT:    srai s5, a1, 56
+; RV64I-NEXT:    addi s3, sp, 15
+; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:  .LBB36_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    slli a1, a0, 56
+; RV64I-NEXT:    srai a1, a1, 56
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    blt s5, a1, .LBB36_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB36_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB36_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB36_1 Depth=1
+; RV64I-NEXT:    sb a0, 15(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_1
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    beqz a1, .LBB36_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_max_i8_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 56
+; RV64IA-NEXT:    sub a6, a3, a2
+; RV64IA-NEXT:    addi a4, zero, 255
+; RV64IA-NEXT:    sllw a7, a4, a2
+; RV64IA-NEXT:    slli a1, a1, 56
+; RV64IA-NEXT:    srai a1, a1, 56
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB36_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a5, (a0)
+; RV64IA-NEXT:    and a4, a5, a7
+; RV64IA-NEXT:    mv a3, a5
+; RV64IA-NEXT:    sll a4, a4, a6
+; RV64IA-NEXT:    sra a4, a4, a6
+; RV64IA-NEXT:    bge a4, a1, .LBB36_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB36_1 Depth=1
+; RV64IA-NEXT:    xor a3, a5, a1
+; RV64IA-NEXT:    and a3, a3, a7
+; RV64IA-NEXT:    xor a3, a5, a3
+; RV64IA-NEXT:  .LBB36_3: # in Loop: Header=BB36_1 Depth=1
+; RV64IA-NEXT:    sc.w a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB36_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a5, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw max i8* %a, i8 %b acquire
   ret i8 %1
 }
@@ -1337,6 +2450,82 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_max_i8_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    slli a1, a1, 56
+; RV64I-NEXT:    srai s1, a1, 56
+; RV64I-NEXT:    addi s3, sp, 15
+; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:  .LBB37_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    slli a1, a0, 56
+; RV64I-NEXT:    srai a1, a1, 56
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    blt s1, a1, .LBB37_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB37_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB37_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB37_1 Depth=1
+; RV64I-NEXT:    sb a0, 15(sp)
+; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_1
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    beqz a1, .LBB37_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_max_i8_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 56
+; RV64IA-NEXT:    sub a6, a3, a2
+; RV64IA-NEXT:    addi a4, zero, 255
+; RV64IA-NEXT:    sllw a7, a4, a2
+; RV64IA-NEXT:    slli a1, a1, 56
+; RV64IA-NEXT:    srai a1, a1, 56
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB37_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a5, (a0)
+; RV64IA-NEXT:    and a4, a5, a7
+; RV64IA-NEXT:    mv a3, a5
+; RV64IA-NEXT:    sll a4, a4, a6
+; RV64IA-NEXT:    sra a4, a4, a6
+; RV64IA-NEXT:    bge a4, a1, .LBB37_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB37_1 Depth=1
+; RV64IA-NEXT:    xor a3, a5, a1
+; RV64IA-NEXT:    and a3, a3, a7
+; RV64IA-NEXT:    xor a3, a5, a3
+; RV64IA-NEXT:  .LBB37_3: # in Loop: Header=BB37_1 Depth=1
+; RV64IA-NEXT:    sc.w.rl a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB37_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a5, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw max i8* %a, i8 %b release
   ret i8 %1
 }
@@ -1420,6 +2609,85 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_max_i8_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    slli a1, a1, 56
+; RV64I-NEXT:    srai s1, a1, 56
+; RV64I-NEXT:    addi s3, sp, 7
+; RV64I-NEXT:    addi s4, zero, 4
+; RV64I-NEXT:    addi s5, zero, 2
+; RV64I-NEXT:  .LBB38_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    slli a1, a0, 56
+; RV64I-NEXT:    srai a1, a1, 56
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    blt s1, a1, .LBB38_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB38_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB38_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB38_1 Depth=1
+; RV64I-NEXT:    sb a0, 7(sp)
+; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    call __atomic_compare_exchange_1
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lb a0, 7(sp)
+; RV64I-NEXT:    beqz a1, .LBB38_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s6, 8(sp)
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_max_i8_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 56
+; RV64IA-NEXT:    sub a6, a3, a2
+; RV64IA-NEXT:    addi a4, zero, 255
+; RV64IA-NEXT:    sllw a7, a4, a2
+; RV64IA-NEXT:    slli a1, a1, 56
+; RV64IA-NEXT:    srai a1, a1, 56
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB38_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a5, (a0)
+; RV64IA-NEXT:    and a4, a5, a7
+; RV64IA-NEXT:    mv a3, a5
+; RV64IA-NEXT:    sll a4, a4, a6
+; RV64IA-NEXT:    sra a4, a4, a6
+; RV64IA-NEXT:    bge a4, a1, .LBB38_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB38_1 Depth=1
+; RV64IA-NEXT:    xor a3, a5, a1
+; RV64IA-NEXT:    and a3, a3, a7
+; RV64IA-NEXT:    xor a3, a5, a3
+; RV64IA-NEXT:  .LBB38_3: # in Loop: Header=BB38_1 Depth=1
+; RV64IA-NEXT:    sc.w.rl a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB38_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a5, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw max i8* %a, i8 %b acq_rel
   ret i8 %1
 }
@@ -1500,6 +2768,82 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_max_i8_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    slli a1, a1, 56
+; RV64I-NEXT:    srai s5, a1, 56
+; RV64I-NEXT:    addi s3, sp, 15
+; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:  .LBB39_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    slli a1, a0, 56
+; RV64I-NEXT:    srai a1, a1, 56
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    blt s5, a1, .LBB39_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB39_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB39_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB39_1 Depth=1
+; RV64I-NEXT:    sb a0, 15(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_1
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    beqz a1, .LBB39_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_max_i8_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 56
+; RV64IA-NEXT:    sub a6, a3, a2
+; RV64IA-NEXT:    addi a4, zero, 255
+; RV64IA-NEXT:    sllw a7, a4, a2
+; RV64IA-NEXT:    slli a1, a1, 56
+; RV64IA-NEXT:    srai a1, a1, 56
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB39_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aqrl a5, (a0)
+; RV64IA-NEXT:    and a4, a5, a7
+; RV64IA-NEXT:    mv a3, a5
+; RV64IA-NEXT:    sll a4, a4, a6
+; RV64IA-NEXT:    sra a4, a4, a6
+; RV64IA-NEXT:    bge a4, a1, .LBB39_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB39_1 Depth=1
+; RV64IA-NEXT:    xor a3, a5, a1
+; RV64IA-NEXT:    and a3, a3, a7
+; RV64IA-NEXT:    xor a3, a5, a3
+; RV64IA-NEXT:  .LBB39_3: # in Loop: Header=BB39_1 Depth=1
+; RV64IA-NEXT:    sc.w.aqrl a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB39_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a5, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw max i8* %a, i8 %b seq_cst
   ret i8 %1
 }
@@ -1577,6 +2921,79 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_min_i8_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    slli a1, a1, 56
+; RV64I-NEXT:    srai s1, a1, 56
+; RV64I-NEXT:    addi s3, sp, 7
+; RV64I-NEXT:  .LBB40_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    slli a1, a0, 56
+; RV64I-NEXT:    srai a1, a1, 56
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bge s1, a1, .LBB40_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB40_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB40_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB40_1 Depth=1
+; RV64I-NEXT:    sb a0, 7(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, zero
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_1
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lb a0, 7(sp)
+; RV64I-NEXT:    beqz a1, .LBB40_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_min_i8_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 56
+; RV64IA-NEXT:    sub a6, a3, a2
+; RV64IA-NEXT:    addi a4, zero, 255
+; RV64IA-NEXT:    sllw a7, a4, a2
+; RV64IA-NEXT:    slli a1, a1, 56
+; RV64IA-NEXT:    srai a1, a1, 56
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB40_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a5, (a0)
+; RV64IA-NEXT:    and a4, a5, a7
+; RV64IA-NEXT:    mv a3, a5
+; RV64IA-NEXT:    sll a4, a4, a6
+; RV64IA-NEXT:    sra a4, a4, a6
+; RV64IA-NEXT:    bge a1, a4, .LBB40_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB40_1 Depth=1
+; RV64IA-NEXT:    xor a3, a5, a1
+; RV64IA-NEXT:    and a3, a3, a7
+; RV64IA-NEXT:    xor a3, a5, a3
+; RV64IA-NEXT:  .LBB40_3: # in Loop: Header=BB40_1 Depth=1
+; RV64IA-NEXT:    sc.w a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB40_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a5, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw min i8* %a, i8 %b monotonic
   ret i8 %1
 }
@@ -1657,6 +3074,82 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_min_i8_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    slli a1, a1, 56
+; RV64I-NEXT:    srai s5, a1, 56
+; RV64I-NEXT:    addi s3, sp, 15
+; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:  .LBB41_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    slli a1, a0, 56
+; RV64I-NEXT:    srai a1, a1, 56
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bge s5, a1, .LBB41_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB41_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB41_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB41_1 Depth=1
+; RV64I-NEXT:    sb a0, 15(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_1
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    beqz a1, .LBB41_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_min_i8_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 56
+; RV64IA-NEXT:    sub a6, a3, a2
+; RV64IA-NEXT:    addi a4, zero, 255
+; RV64IA-NEXT:    sllw a7, a4, a2
+; RV64IA-NEXT:    slli a1, a1, 56
+; RV64IA-NEXT:    srai a1, a1, 56
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB41_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a5, (a0)
+; RV64IA-NEXT:    and a4, a5, a7
+; RV64IA-NEXT:    mv a3, a5
+; RV64IA-NEXT:    sll a4, a4, a6
+; RV64IA-NEXT:    sra a4, a4, a6
+; RV64IA-NEXT:    bge a1, a4, .LBB41_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB41_1 Depth=1
+; RV64IA-NEXT:    xor a3, a5, a1
+; RV64IA-NEXT:    and a3, a3, a7
+; RV64IA-NEXT:    xor a3, a5, a3
+; RV64IA-NEXT:  .LBB41_3: # in Loop: Header=BB41_1 Depth=1
+; RV64IA-NEXT:    sc.w a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB41_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a5, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw min i8* %a, i8 %b acquire
   ret i8 %1
 }
@@ -1737,6 +3230,82 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_min_i8_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    slli a1, a1, 56
+; RV64I-NEXT:    srai s1, a1, 56
+; RV64I-NEXT:    addi s3, sp, 15
+; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:  .LBB42_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    slli a1, a0, 56
+; RV64I-NEXT:    srai a1, a1, 56
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bge s1, a1, .LBB42_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB42_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB42_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB42_1 Depth=1
+; RV64I-NEXT:    sb a0, 15(sp)
+; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_1
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    beqz a1, .LBB42_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_min_i8_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 56
+; RV64IA-NEXT:    sub a6, a3, a2
+; RV64IA-NEXT:    addi a4, zero, 255
+; RV64IA-NEXT:    sllw a7, a4, a2
+; RV64IA-NEXT:    slli a1, a1, 56
+; RV64IA-NEXT:    srai a1, a1, 56
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB42_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a5, (a0)
+; RV64IA-NEXT:    and a4, a5, a7
+; RV64IA-NEXT:    mv a3, a5
+; RV64IA-NEXT:    sll a4, a4, a6
+; RV64IA-NEXT:    sra a4, a4, a6
+; RV64IA-NEXT:    bge a1, a4, .LBB42_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB42_1 Depth=1
+; RV64IA-NEXT:    xor a3, a5, a1
+; RV64IA-NEXT:    and a3, a3, a7
+; RV64IA-NEXT:    xor a3, a5, a3
+; RV64IA-NEXT:  .LBB42_3: # in Loop: Header=BB42_1 Depth=1
+; RV64IA-NEXT:    sc.w.rl a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB42_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a5, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw min i8* %a, i8 %b release
   ret i8 %1
 }
@@ -1820,6 +3389,85 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_min_i8_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    slli a1, a1, 56
+; RV64I-NEXT:    srai s1, a1, 56
+; RV64I-NEXT:    addi s3, sp, 7
+; RV64I-NEXT:    addi s4, zero, 4
+; RV64I-NEXT:    addi s5, zero, 2
+; RV64I-NEXT:  .LBB43_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    slli a1, a0, 56
+; RV64I-NEXT:    srai a1, a1, 56
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bge s1, a1, .LBB43_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB43_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB43_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB43_1 Depth=1
+; RV64I-NEXT:    sb a0, 7(sp)
+; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    call __atomic_compare_exchange_1
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lb a0, 7(sp)
+; RV64I-NEXT:    beqz a1, .LBB43_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s6, 8(sp)
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_min_i8_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 56
+; RV64IA-NEXT:    sub a6, a3, a2
+; RV64IA-NEXT:    addi a4, zero, 255
+; RV64IA-NEXT:    sllw a7, a4, a2
+; RV64IA-NEXT:    slli a1, a1, 56
+; RV64IA-NEXT:    srai a1, a1, 56
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB43_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a5, (a0)
+; RV64IA-NEXT:    and a4, a5, a7
+; RV64IA-NEXT:    mv a3, a5
+; RV64IA-NEXT:    sll a4, a4, a6
+; RV64IA-NEXT:    sra a4, a4, a6
+; RV64IA-NEXT:    bge a1, a4, .LBB43_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB43_1 Depth=1
+; RV64IA-NEXT:    xor a3, a5, a1
+; RV64IA-NEXT:    and a3, a3, a7
+; RV64IA-NEXT:    xor a3, a5, a3
+; RV64IA-NEXT:  .LBB43_3: # in Loop: Header=BB43_1 Depth=1
+; RV64IA-NEXT:    sc.w.rl a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB43_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a5, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw min i8* %a, i8 %b acq_rel
   ret i8 %1
 }
@@ -1900,6 +3548,82 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_min_i8_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    slli a1, a1, 56
+; RV64I-NEXT:    srai s5, a1, 56
+; RV64I-NEXT:    addi s3, sp, 15
+; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:  .LBB44_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    slli a1, a0, 56
+; RV64I-NEXT:    srai a1, a1, 56
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bge s5, a1, .LBB44_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB44_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB44_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB44_1 Depth=1
+; RV64I-NEXT:    sb a0, 15(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_1
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    beqz a1, .LBB44_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_min_i8_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 56
+; RV64IA-NEXT:    sub a6, a3, a2
+; RV64IA-NEXT:    addi a4, zero, 255
+; RV64IA-NEXT:    sllw a7, a4, a2
+; RV64IA-NEXT:    slli a1, a1, 56
+; RV64IA-NEXT:    srai a1, a1, 56
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB44_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aqrl a5, (a0)
+; RV64IA-NEXT:    and a4, a5, a7
+; RV64IA-NEXT:    mv a3, a5
+; RV64IA-NEXT:    sll a4, a4, a6
+; RV64IA-NEXT:    sra a4, a4, a6
+; RV64IA-NEXT:    bge a1, a4, .LBB44_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB44_1 Depth=1
+; RV64IA-NEXT:    xor a3, a5, a1
+; RV64IA-NEXT:    and a3, a3, a7
+; RV64IA-NEXT:    xor a3, a5, a3
+; RV64IA-NEXT:  .LBB44_3: # in Loop: Header=BB44_1 Depth=1
+; RV64IA-NEXT:    sc.w.aqrl a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB44_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a5, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw min i8* %a, i8 %b seq_cst
   ret i8 %1
 }
@@ -1970,6 +3694,72 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umax_i8_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    andi s1, a1, 255
+; RV64I-NEXT:    addi s3, sp, 7
+; RV64I-NEXT:  .LBB45_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    andi a1, a0, 255
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bltu s1, a1, .LBB45_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB45_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB45_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB45_1 Depth=1
+; RV64I-NEXT:    sb a0, 7(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, zero
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_1
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lb a0, 7(sp)
+; RV64I-NEXT:    beqz a1, .LBB45_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umax_i8_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a6, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB45_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    and a3, a4, a6
+; RV64IA-NEXT:    mv a5, a4
+; RV64IA-NEXT:    bgeu a3, a1, .LBB45_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB45_1 Depth=1
+; RV64IA-NEXT:    xor a5, a4, a1
+; RV64IA-NEXT:    and a5, a5, a6
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:  .LBB45_3: # in Loop: Header=BB45_1 Depth=1
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB45_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i8* %a, i8 %b monotonic
   ret i8 %1
 }
@@ -2043,6 +3833,75 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umax_i8_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    andi s5, a1, 255
+; RV64I-NEXT:    addi s3, sp, 15
+; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:  .LBB46_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    andi a1, a0, 255
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bltu s5, a1, .LBB46_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB46_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB46_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB46_1 Depth=1
+; RV64I-NEXT:    sb a0, 15(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_1
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    beqz a1, .LBB46_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umax_i8_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a6, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB46_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    and a3, a4, a6
+; RV64IA-NEXT:    mv a5, a4
+; RV64IA-NEXT:    bgeu a3, a1, .LBB46_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB46_1 Depth=1
+; RV64IA-NEXT:    xor a5, a4, a1
+; RV64IA-NEXT:    and a5, a5, a6
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:  .LBB46_3: # in Loop: Header=BB46_1 Depth=1
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB46_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i8* %a, i8 %b acquire
   ret i8 %1
 }
@@ -2116,6 +3975,75 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umax_i8_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    andi s1, a1, 255
+; RV64I-NEXT:    addi s3, sp, 15
+; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:  .LBB47_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    andi a1, a0, 255
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bltu s1, a1, .LBB47_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB47_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB47_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB47_1 Depth=1
+; RV64I-NEXT:    sb a0, 15(sp)
+; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_1
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    beqz a1, .LBB47_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umax_i8_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a6, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB47_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    and a3, a4, a6
+; RV64IA-NEXT:    mv a5, a4
+; RV64IA-NEXT:    bgeu a3, a1, .LBB47_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB47_1 Depth=1
+; RV64IA-NEXT:    xor a5, a4, a1
+; RV64IA-NEXT:    and a5, a5, a6
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:  .LBB47_3: # in Loop: Header=BB47_1 Depth=1
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB47_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i8* %a, i8 %b release
   ret i8 %1
 }
@@ -2192,6 +4120,78 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umax_i8_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    andi s1, a1, 255
+; RV64I-NEXT:    addi s3, sp, 7
+; RV64I-NEXT:    addi s4, zero, 4
+; RV64I-NEXT:    addi s5, zero, 2
+; RV64I-NEXT:  .LBB48_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    andi a1, a0, 255
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bltu s1, a1, .LBB48_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB48_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB48_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB48_1 Depth=1
+; RV64I-NEXT:    sb a0, 7(sp)
+; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    call __atomic_compare_exchange_1
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lb a0, 7(sp)
+; RV64I-NEXT:    beqz a1, .LBB48_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s6, 8(sp)
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umax_i8_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a6, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB48_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    and a3, a4, a6
+; RV64IA-NEXT:    mv a5, a4
+; RV64IA-NEXT:    bgeu a3, a1, .LBB48_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB48_1 Depth=1
+; RV64IA-NEXT:    xor a5, a4, a1
+; RV64IA-NEXT:    and a5, a5, a6
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:  .LBB48_3: # in Loop: Header=BB48_1 Depth=1
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB48_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i8* %a, i8 %b acq_rel
   ret i8 %1
 }
@@ -2265,6 +4265,75 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umax_i8_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    andi s5, a1, 255
+; RV64I-NEXT:    addi s3, sp, 15
+; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:  .LBB49_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    andi a1, a0, 255
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bltu s5, a1, .LBB49_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB49_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB49_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB49_1 Depth=1
+; RV64I-NEXT:    sb a0, 15(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_1
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    beqz a1, .LBB49_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umax_i8_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a6, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB49_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aqrl a4, (a0)
+; RV64IA-NEXT:    and a3, a4, a6
+; RV64IA-NEXT:    mv a5, a4
+; RV64IA-NEXT:    bgeu a3, a1, .LBB49_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB49_1 Depth=1
+; RV64IA-NEXT:    xor a5, a4, a1
+; RV64IA-NEXT:    and a5, a5, a6
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:  .LBB49_3: # in Loop: Header=BB49_1 Depth=1
+; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB49_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i8* %a, i8 %b seq_cst
   ret i8 %1
 }
@@ -2335,6 +4404,72 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umin_i8_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    andi s1, a1, 255
+; RV64I-NEXT:    addi s3, sp, 7
+; RV64I-NEXT:  .LBB50_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    andi a1, a0, 255
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bgeu s1, a1, .LBB50_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB50_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB50_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB50_1 Depth=1
+; RV64I-NEXT:    sb a0, 7(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, zero
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_1
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lb a0, 7(sp)
+; RV64I-NEXT:    beqz a1, .LBB50_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umin_i8_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a6, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB50_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    and a3, a4, a6
+; RV64IA-NEXT:    mv a5, a4
+; RV64IA-NEXT:    bgeu a1, a3, .LBB50_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB50_1 Depth=1
+; RV64IA-NEXT:    xor a5, a4, a1
+; RV64IA-NEXT:    and a5, a5, a6
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:  .LBB50_3: # in Loop: Header=BB50_1 Depth=1
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB50_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i8* %a, i8 %b monotonic
   ret i8 %1
 }
@@ -2408,6 +4543,75 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umin_i8_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    andi s5, a1, 255
+; RV64I-NEXT:    addi s3, sp, 15
+; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:  .LBB51_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    andi a1, a0, 255
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bgeu s5, a1, .LBB51_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB51_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB51_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB51_1 Depth=1
+; RV64I-NEXT:    sb a0, 15(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_1
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    beqz a1, .LBB51_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umin_i8_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a6, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB51_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    and a3, a4, a6
+; RV64IA-NEXT:    mv a5, a4
+; RV64IA-NEXT:    bgeu a1, a3, .LBB51_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB51_1 Depth=1
+; RV64IA-NEXT:    xor a5, a4, a1
+; RV64IA-NEXT:    and a5, a5, a6
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:  .LBB51_3: # in Loop: Header=BB51_1 Depth=1
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB51_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i8* %a, i8 %b acquire
   ret i8 %1
 }
@@ -2481,6 +4685,75 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umin_i8_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    andi s1, a1, 255
+; RV64I-NEXT:    addi s3, sp, 15
+; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:  .LBB52_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    andi a1, a0, 255
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bgeu s1, a1, .LBB52_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB52_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB52_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB52_1 Depth=1
+; RV64I-NEXT:    sb a0, 15(sp)
+; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_1
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    beqz a1, .LBB52_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umin_i8_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a6, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB52_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    and a3, a4, a6
+; RV64IA-NEXT:    mv a5, a4
+; RV64IA-NEXT:    bgeu a1, a3, .LBB52_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB52_1 Depth=1
+; RV64IA-NEXT:    xor a5, a4, a1
+; RV64IA-NEXT:    and a5, a5, a6
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:  .LBB52_3: # in Loop: Header=BB52_1 Depth=1
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB52_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i8* %a, i8 %b release
   ret i8 %1
 }
@@ -2557,6 +4830,78 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umin_i8_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    andi s1, a1, 255
+; RV64I-NEXT:    addi s3, sp, 7
+; RV64I-NEXT:    addi s4, zero, 4
+; RV64I-NEXT:    addi s5, zero, 2
+; RV64I-NEXT:  .LBB53_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    andi a1, a0, 255
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bgeu s1, a1, .LBB53_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB53_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB53_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB53_1 Depth=1
+; RV64I-NEXT:    sb a0, 7(sp)
+; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    call __atomic_compare_exchange_1
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lb a0, 7(sp)
+; RV64I-NEXT:    beqz a1, .LBB53_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s6, 8(sp)
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umin_i8_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a6, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB53_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    and a3, a4, a6
+; RV64IA-NEXT:    mv a5, a4
+; RV64IA-NEXT:    bgeu a1, a3, .LBB53_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB53_1 Depth=1
+; RV64IA-NEXT:    xor a5, a4, a1
+; RV64IA-NEXT:    and a5, a5, a6
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:  .LBB53_3: # in Loop: Header=BB53_1 Depth=1
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB53_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i8* %a, i8 %b acq_rel
   ret i8 %1
 }
@@ -2630,6 +4975,75 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a4, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umin_i8_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lbu a0, 0(a0)
+; RV64I-NEXT:    andi s5, a1, 255
+; RV64I-NEXT:    addi s3, sp, 15
+; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:  .LBB54_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    andi a1, a0, 255
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bgeu s5, a1, .LBB54_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB54_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB54_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB54_1 Depth=1
+; RV64I-NEXT:    sb a0, 15(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_1
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lb a0, 15(sp)
+; RV64I-NEXT:    beqz a1, .LBB54_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umin_i8_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 255
+; RV64IA-NEXT:    sllw a6, a3, a2
+; RV64IA-NEXT:    andi a1, a1, 255
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB54_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aqrl a4, (a0)
+; RV64IA-NEXT:    and a3, a4, a6
+; RV64IA-NEXT:    mv a5, a4
+; RV64IA-NEXT:    bgeu a1, a3, .LBB54_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB54_1 Depth=1
+; RV64IA-NEXT:    xor a5, a4, a1
+; RV64IA-NEXT:    and a5, a5, a6
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:  .LBB54_3: # in Loop: Header=BB54_1 Depth=1
+; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB54_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a4, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i8* %a, i8 %b seq_cst
   ret i8 %1
 }
@@ -2666,6 +5080,38 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xchg_i16_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_exchange_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xchg_i16_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a2, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB55_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    add a5, zero, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a2
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB55_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i16* %a, i16 %b monotonic
   ret i16 %1
 }
@@ -2702,6 +5148,38 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xchg_i16_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_exchange_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xchg_i16_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a2, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB56_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    add a5, zero, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a2
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB56_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i16* %a, i16 %b acquire
   ret i16 %1
 }
@@ -2738,6 +5216,38 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xchg_i16_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_exchange_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xchg_i16_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a2, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB57_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    add a5, zero, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a2
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB57_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i16* %a, i16 %b release
   ret i16 %1
 }
@@ -2774,6 +5284,38 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xchg_i16_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_exchange_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xchg_i16_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a2, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB58_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    add a5, zero, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a2
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB58_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i16* %a, i16 %b acq_rel
   ret i16 %1
 }
@@ -2810,6 +5352,38 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xchg_i16_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_exchange_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xchg_i16_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a2, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB59_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aqrl a4, (a0)
+; RV64IA-NEXT:    add a5, zero, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a2
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB59_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i16* %a, i16 %b seq_cst
   ret i16 %1
 }
@@ -2846,6 +5420,38 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_add_i16_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_add_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_add_i16_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a2, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB60_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    add a5, a4, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a2
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB60_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw add i16* %a, i16 %b monotonic
   ret i16 %1
 }
@@ -2882,6 +5488,38 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_add_i16_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_add_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_add_i16_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a2, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB61_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    add a5, a4, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a2
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB61_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw add i16* %a, i16 %b acquire
   ret i16 %1
 }
@@ -2918,6 +5556,38 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_add_i16_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_add_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_add_i16_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a2, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB62_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    add a5, a4, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a2
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB62_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw add i16* %a, i16 %b release
   ret i16 %1
 }
@@ -2954,6 +5624,38 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_add_i16_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_add_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_add_i16_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a2, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB63_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    add a5, a4, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a2
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB63_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw add i16* %a, i16 %b acq_rel
   ret i16 %1
 }
@@ -2990,6 +5692,38 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_add_i16_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_add_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_add_i16_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a2, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB64_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aqrl a4, (a0)
+; RV64IA-NEXT:    add a5, a4, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a2
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB64_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw add i16* %a, i16 %b seq_cst
   ret i16 %1
 }
@@ -3026,6 +5760,38 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_sub_i16_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_sub_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_sub_i16_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a2, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB65_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    sub a5, a4, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a2
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB65_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i16* %a, i16 %b monotonic
   ret i16 %1
 }
@@ -3062,6 +5828,38 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_sub_i16_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_sub_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_sub_i16_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a2, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB66_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    sub a5, a4, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a2
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB66_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i16* %a, i16 %b acquire
   ret i16 %1
 }
@@ -3098,6 +5896,38 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_sub_i16_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_sub_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_sub_i16_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a2, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB67_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    sub a5, a4, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a2
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB67_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i16* %a, i16 %b release
   ret i16 %1
 }
@@ -3134,6 +5964,38 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_sub_i16_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_sub_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_sub_i16_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a2, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB68_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    sub a5, a4, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a2
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB68_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i16* %a, i16 %b acq_rel
   ret i16 %1
 }
@@ -3170,6 +6032,38 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_sub_i16_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_sub_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_sub_i16_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a2, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB69_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aqrl a4, (a0)
+; RV64IA-NEXT:    sub a5, a4, a1
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a2
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB69_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i16* %a, i16 %b seq_cst
   ret i16 %1
 }
@@ -3200,6 +6094,32 @@
 ; RV32IA-NEXT:    amoand.w a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_and_i16_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_and_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_and_i16_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sll a1, a1, a3
+; RV64IA-NEXT:    sll a2, a2, a3
+; RV64IA-NEXT:    not a2, a2
+; RV64IA-NEXT:    or a1, a2, a1
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoand.w a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw and i16* %a, i16 %b monotonic
   ret i16 %1
 }
@@ -3230,6 +6150,32 @@
 ; RV32IA-NEXT:    amoand.w.aq a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_and_i16_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_and_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_and_i16_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sll a1, a1, a3
+; RV64IA-NEXT:    sll a2, a2, a3
+; RV64IA-NEXT:    not a2, a2
+; RV64IA-NEXT:    or a1, a2, a1
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoand.w.aq a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw and i16* %a, i16 %b acquire
   ret i16 %1
 }
@@ -3260,6 +6206,32 @@
 ; RV32IA-NEXT:    amoand.w.rl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_and_i16_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_and_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_and_i16_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sll a1, a1, a3
+; RV64IA-NEXT:    sll a2, a2, a3
+; RV64IA-NEXT:    not a2, a2
+; RV64IA-NEXT:    or a1, a2, a1
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoand.w.rl a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw and i16* %a, i16 %b release
   ret i16 %1
 }
@@ -3290,6 +6262,32 @@
 ; RV32IA-NEXT:    amoand.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_and_i16_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_and_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_and_i16_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sll a1, a1, a3
+; RV64IA-NEXT:    sll a2, a2, a3
+; RV64IA-NEXT:    not a2, a2
+; RV64IA-NEXT:    or a1, a2, a1
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoand.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw and i16* %a, i16 %b acq_rel
   ret i16 %1
 }
@@ -3320,6 +6318,32 @@
 ; RV32IA-NEXT:    amoand.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_and_i16_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_and_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_and_i16_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sll a1, a1, a3
+; RV64IA-NEXT:    sll a2, a2, a3
+; RV64IA-NEXT:    not a2, a2
+; RV64IA-NEXT:    or a1, a2, a1
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoand.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw and i16* %a, i16 %b seq_cst
   ret i16 %1
 }
@@ -3357,6 +6381,39 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_nand_i16_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_nand_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_nand_i16_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a2, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB75_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    and a5, a4, a1
+; RV64IA-NEXT:    not a5, a5
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a2
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB75_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i16* %a, i16 %b monotonic
   ret i16 %1
 }
@@ -3394,6 +6451,39 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_nand_i16_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_nand_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_nand_i16_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a2, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB76_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    and a5, a4, a1
+; RV64IA-NEXT:    not a5, a5
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a2
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB76_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i16* %a, i16 %b acquire
   ret i16 %1
 }
@@ -3431,6 +6521,39 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_nand_i16_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_nand_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_nand_i16_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a2, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB77_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    and a5, a4, a1
+; RV64IA-NEXT:    not a5, a5
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a2
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB77_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i16* %a, i16 %b release
   ret i16 %1
 }
@@ -3468,6 +6591,39 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_nand_i16_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_nand_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_nand_i16_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a2, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB78_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    and a5, a4, a1
+; RV64IA-NEXT:    not a5, a5
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a2
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB78_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i16* %a, i16 %b acq_rel
   ret i16 %1
 }
@@ -3505,6 +6661,39 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_nand_i16_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_nand_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_nand_i16_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a2, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB79_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aqrl a4, (a0)
+; RV64IA-NEXT:    and a5, a4, a1
+; RV64IA-NEXT:    not a5, a5
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    and a5, a5, a2
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB79_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i16* %a, i16 %b seq_cst
   ret i16 %1
 }
@@ -3532,6 +6721,29 @@
 ; RV32IA-NEXT:    amoor.w a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_or_i16_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_or_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_or_i16_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoor.w a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw or i16* %a, i16 %b monotonic
   ret i16 %1
 }
@@ -3559,6 +6771,29 @@
 ; RV32IA-NEXT:    amoor.w.aq a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_or_i16_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_or_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_or_i16_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoor.w.aq a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw or i16* %a, i16 %b acquire
   ret i16 %1
 }
@@ -3586,6 +6821,29 @@
 ; RV32IA-NEXT:    amoor.w.rl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_or_i16_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_or_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_or_i16_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoor.w.rl a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw or i16* %a, i16 %b release
   ret i16 %1
 }
@@ -3613,6 +6871,29 @@
 ; RV32IA-NEXT:    amoor.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_or_i16_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_or_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_or_i16_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoor.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw or i16* %a, i16 %b acq_rel
   ret i16 %1
 }
@@ -3640,6 +6921,29 @@
 ; RV32IA-NEXT:    amoor.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_or_i16_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_or_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_or_i16_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoor.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw or i16* %a, i16 %b seq_cst
   ret i16 %1
 }
@@ -3667,6 +6971,29 @@
 ; RV32IA-NEXT:    amoxor.w a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xor_i16_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_xor_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xor_i16_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoxor.w a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i16* %a, i16 %b monotonic
   ret i16 %1
 }
@@ -3694,6 +7021,29 @@
 ; RV32IA-NEXT:    amoxor.w.aq a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xor_i16_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_xor_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xor_i16_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoxor.w.aq a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i16* %a, i16 %b acquire
   ret i16 %1
 }
@@ -3721,6 +7071,29 @@
 ; RV32IA-NEXT:    amoxor.w.rl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xor_i16_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_xor_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xor_i16_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoxor.w.rl a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i16* %a, i16 %b release
   ret i16 %1
 }
@@ -3748,6 +7121,29 @@
 ; RV32IA-NEXT:    amoxor.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xor_i16_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_xor_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xor_i16_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoxor.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i16* %a, i16 %b acq_rel
   ret i16 %1
 }
@@ -3775,6 +7171,29 @@
 ; RV32IA-NEXT:    amoxor.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    srl a0, a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xor_i16_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_xor_2
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xor_i16_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    sll a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:    amoxor.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    srlw a0, a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i16* %a, i16 %b seq_cst
   ret i16 %1
 }
@@ -3853,6 +7272,80 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_max_i16_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lhu a0, 0(a0)
+; RV64I-NEXT:    slli a1, a1, 48
+; RV64I-NEXT:    srai s1, a1, 48
+; RV64I-NEXT:    addi s3, sp, 6
+; RV64I-NEXT:  .LBB90_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    slli a1, a0, 48
+; RV64I-NEXT:    srai a1, a1, 48
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    blt s1, a1, .LBB90_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB90_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB90_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB90_1 Depth=1
+; RV64I-NEXT:    sh a0, 6(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, zero
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_2
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lh a0, 6(sp)
+; RV64I-NEXT:    beqz a1, .LBB90_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_max_i16_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 48
+; RV64IA-NEXT:    sub a6, a3, a2
+; RV64IA-NEXT:    lui a4, 16
+; RV64IA-NEXT:    addiw a4, a4, -1
+; RV64IA-NEXT:    sllw a7, a4, a2
+; RV64IA-NEXT:    slli a1, a1, 48
+; RV64IA-NEXT:    srai a1, a1, 48
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB90_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a5, (a0)
+; RV64IA-NEXT:    and a4, a5, a7
+; RV64IA-NEXT:    mv a3, a5
+; RV64IA-NEXT:    sll a4, a4, a6
+; RV64IA-NEXT:    sra a4, a4, a6
+; RV64IA-NEXT:    bge a4, a1, .LBB90_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB90_1 Depth=1
+; RV64IA-NEXT:    xor a3, a5, a1
+; RV64IA-NEXT:    and a3, a3, a7
+; RV64IA-NEXT:    xor a3, a5, a3
+; RV64IA-NEXT:  .LBB90_3: # in Loop: Header=BB90_1 Depth=1
+; RV64IA-NEXT:    sc.w a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB90_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a5, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw max i16* %a, i16 %b monotonic
   ret i16 %1
 }
@@ -3934,6 +7427,83 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_max_i16_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lhu a0, 0(a0)
+; RV64I-NEXT:    slli a1, a1, 48
+; RV64I-NEXT:    srai s5, a1, 48
+; RV64I-NEXT:    addi s3, sp, 14
+; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:  .LBB91_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    slli a1, a0, 48
+; RV64I-NEXT:    srai a1, a1, 48
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    blt s5, a1, .LBB91_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB91_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB91_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB91_1 Depth=1
+; RV64I-NEXT:    sh a0, 14(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_2
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lh a0, 14(sp)
+; RV64I-NEXT:    beqz a1, .LBB91_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_max_i16_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 48
+; RV64IA-NEXT:    sub a6, a3, a2
+; RV64IA-NEXT:    lui a4, 16
+; RV64IA-NEXT:    addiw a4, a4, -1
+; RV64IA-NEXT:    sllw a7, a4, a2
+; RV64IA-NEXT:    slli a1, a1, 48
+; RV64IA-NEXT:    srai a1, a1, 48
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB91_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a5, (a0)
+; RV64IA-NEXT:    and a4, a5, a7
+; RV64IA-NEXT:    mv a3, a5
+; RV64IA-NEXT:    sll a4, a4, a6
+; RV64IA-NEXT:    sra a4, a4, a6
+; RV64IA-NEXT:    bge a4, a1, .LBB91_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB91_1 Depth=1
+; RV64IA-NEXT:    xor a3, a5, a1
+; RV64IA-NEXT:    and a3, a3, a7
+; RV64IA-NEXT:    xor a3, a5, a3
+; RV64IA-NEXT:  .LBB91_3: # in Loop: Header=BB91_1 Depth=1
+; RV64IA-NEXT:    sc.w a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB91_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a5, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw max i16* %a, i16 %b acquire
   ret i16 %1
 }
@@ -4015,6 +7585,83 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_max_i16_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    lhu a0, 0(a0)
+; RV64I-NEXT:    slli a1, a1, 48
+; RV64I-NEXT:    srai s1, a1, 48
+; RV64I-NEXT:    addi s3, sp, 14
+; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:  .LBB92_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    slli a1, a0, 48
+; RV64I-NEXT:    srai a1, a1, 48
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    blt s1, a1, .LBB92_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB92_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB92_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB92_1 Depth=1
+; RV64I-NEXT:    sh a0, 14(sp)
+; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_2
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lh a0, 14(sp)
+; RV64I-NEXT:    beqz a1, .LBB92_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_max_i16_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 48
+; RV64IA-NEXT:    sub a6, a3, a2
+; RV64IA-NEXT:    lui a4, 16
+; RV64IA-NEXT:    addiw a4, a4, -1
+; RV64IA-NEXT:    sllw a7, a4, a2
+; RV64IA-NEXT:    slli a1, a1, 48
+; RV64IA-NEXT:    srai a1, a1, 48
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB92_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a5, (a0)
+; RV64IA-NEXT:    and a4, a5, a7
+; RV64IA-NEXT:    mv a3, a5
+; RV64IA-NEXT:    sll a4, a4, a6
+; RV64IA-NEXT:    sra a4, a4, a6
+; RV64IA-NEXT:    bge a4, a1, .LBB92_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB92_1 Depth=1
+; RV64IA-NEXT:    xor a3, a5, a1
+; RV64IA-NEXT:    and a3, a3, a7
+; RV64IA-NEXT:    xor a3, a5, a3
+; RV64IA-NEXT:  .LBB92_3: # in Loop: Header=BB92_1 Depth=1
+; RV64IA-NEXT:    sc.w.rl a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB92_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a5, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw max i16* %a, i16 %b release
   ret i16 %1
 }
@@ -4099,6 +7746,86 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_max_i16_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    lhu a0, 0(a0)
+; RV64I-NEXT:    slli a1, a1, 48
+; RV64I-NEXT:    srai s1, a1, 48
+; RV64I-NEXT:    addi s3, sp, 6
+; RV64I-NEXT:    addi s4, zero, 4
+; RV64I-NEXT:    addi s5, zero, 2
+; RV64I-NEXT:  .LBB93_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    slli a1, a0, 48
+; RV64I-NEXT:    srai a1, a1, 48
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    blt s1, a1, .LBB93_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB93_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB93_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB93_1 Depth=1
+; RV64I-NEXT:    sh a0, 6(sp)
+; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    call __atomic_compare_exchange_2
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lh a0, 6(sp)
+; RV64I-NEXT:    beqz a1, .LBB93_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s6, 8(sp)
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_max_i16_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 48
+; RV64IA-NEXT:    sub a6, a3, a2
+; RV64IA-NEXT:    lui a4, 16
+; RV64IA-NEXT:    addiw a4, a4, -1
+; RV64IA-NEXT:    sllw a7, a4, a2
+; RV64IA-NEXT:    slli a1, a1, 48
+; RV64IA-NEXT:    srai a1, a1, 48
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB93_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a5, (a0)
+; RV64IA-NEXT:    and a4, a5, a7
+; RV64IA-NEXT:    mv a3, a5
+; RV64IA-NEXT:    sll a4, a4, a6
+; RV64IA-NEXT:    sra a4, a4, a6
+; RV64IA-NEXT:    bge a4, a1, .LBB93_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB93_1 Depth=1
+; RV64IA-NEXT:    xor a3, a5, a1
+; RV64IA-NEXT:    and a3, a3, a7
+; RV64IA-NEXT:    xor a3, a5, a3
+; RV64IA-NEXT:  .LBB93_3: # in Loop: Header=BB93_1 Depth=1
+; RV64IA-NEXT:    sc.w.rl a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB93_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a5, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw max i16* %a, i16 %b acq_rel
   ret i16 %1
 }
@@ -4180,6 +7907,83 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_max_i16_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lhu a0, 0(a0)
+; RV64I-NEXT:    slli a1, a1, 48
+; RV64I-NEXT:    srai s5, a1, 48
+; RV64I-NEXT:    addi s3, sp, 14
+; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:  .LBB94_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    slli a1, a0, 48
+; RV64I-NEXT:    srai a1, a1, 48
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    blt s5, a1, .LBB94_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB94_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB94_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB94_1 Depth=1
+; RV64I-NEXT:    sh a0, 14(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_2
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lh a0, 14(sp)
+; RV64I-NEXT:    beqz a1, .LBB94_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_max_i16_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 48
+; RV64IA-NEXT:    sub a6, a3, a2
+; RV64IA-NEXT:    lui a4, 16
+; RV64IA-NEXT:    addiw a4, a4, -1
+; RV64IA-NEXT:    sllw a7, a4, a2
+; RV64IA-NEXT:    slli a1, a1, 48
+; RV64IA-NEXT:    srai a1, a1, 48
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB94_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aqrl a5, (a0)
+; RV64IA-NEXT:    and a4, a5, a7
+; RV64IA-NEXT:    mv a3, a5
+; RV64IA-NEXT:    sll a4, a4, a6
+; RV64IA-NEXT:    sra a4, a4, a6
+; RV64IA-NEXT:    bge a4, a1, .LBB94_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB94_1 Depth=1
+; RV64IA-NEXT:    xor a3, a5, a1
+; RV64IA-NEXT:    and a3, a3, a7
+; RV64IA-NEXT:    xor a3, a5, a3
+; RV64IA-NEXT:  .LBB94_3: # in Loop: Header=BB94_1 Depth=1
+; RV64IA-NEXT:    sc.w.aqrl a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB94_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a5, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw max i16* %a, i16 %b seq_cst
   ret i16 %1
 }
@@ -4258,6 +8062,80 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_min_i16_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lhu a0, 0(a0)
+; RV64I-NEXT:    slli a1, a1, 48
+; RV64I-NEXT:    srai s1, a1, 48
+; RV64I-NEXT:    addi s3, sp, 6
+; RV64I-NEXT:  .LBB95_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    slli a1, a0, 48
+; RV64I-NEXT:    srai a1, a1, 48
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bge s1, a1, .LBB95_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB95_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB95_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB95_1 Depth=1
+; RV64I-NEXT:    sh a0, 6(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, zero
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_2
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lh a0, 6(sp)
+; RV64I-NEXT:    beqz a1, .LBB95_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_min_i16_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 48
+; RV64IA-NEXT:    sub a6, a3, a2
+; RV64IA-NEXT:    lui a4, 16
+; RV64IA-NEXT:    addiw a4, a4, -1
+; RV64IA-NEXT:    sllw a7, a4, a2
+; RV64IA-NEXT:    slli a1, a1, 48
+; RV64IA-NEXT:    srai a1, a1, 48
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB95_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a5, (a0)
+; RV64IA-NEXT:    and a4, a5, a7
+; RV64IA-NEXT:    mv a3, a5
+; RV64IA-NEXT:    sll a4, a4, a6
+; RV64IA-NEXT:    sra a4, a4, a6
+; RV64IA-NEXT:    bge a1, a4, .LBB95_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB95_1 Depth=1
+; RV64IA-NEXT:    xor a3, a5, a1
+; RV64IA-NEXT:    and a3, a3, a7
+; RV64IA-NEXT:    xor a3, a5, a3
+; RV64IA-NEXT:  .LBB95_3: # in Loop: Header=BB95_1 Depth=1
+; RV64IA-NEXT:    sc.w a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB95_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a5, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw min i16* %a, i16 %b monotonic
   ret i16 %1
 }
@@ -4339,6 +8217,83 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_min_i16_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lhu a0, 0(a0)
+; RV64I-NEXT:    slli a1, a1, 48
+; RV64I-NEXT:    srai s5, a1, 48
+; RV64I-NEXT:    addi s3, sp, 14
+; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:  .LBB96_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    slli a1, a0, 48
+; RV64I-NEXT:    srai a1, a1, 48
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bge s5, a1, .LBB96_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB96_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB96_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB96_1 Depth=1
+; RV64I-NEXT:    sh a0, 14(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_2
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lh a0, 14(sp)
+; RV64I-NEXT:    beqz a1, .LBB96_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_min_i16_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 48
+; RV64IA-NEXT:    sub a6, a3, a2
+; RV64IA-NEXT:    lui a4, 16
+; RV64IA-NEXT:    addiw a4, a4, -1
+; RV64IA-NEXT:    sllw a7, a4, a2
+; RV64IA-NEXT:    slli a1, a1, 48
+; RV64IA-NEXT:    srai a1, a1, 48
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB96_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a5, (a0)
+; RV64IA-NEXT:    and a4, a5, a7
+; RV64IA-NEXT:    mv a3, a5
+; RV64IA-NEXT:    sll a4, a4, a6
+; RV64IA-NEXT:    sra a4, a4, a6
+; RV64IA-NEXT:    bge a1, a4, .LBB96_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB96_1 Depth=1
+; RV64IA-NEXT:    xor a3, a5, a1
+; RV64IA-NEXT:    and a3, a3, a7
+; RV64IA-NEXT:    xor a3, a5, a3
+; RV64IA-NEXT:  .LBB96_3: # in Loop: Header=BB96_1 Depth=1
+; RV64IA-NEXT:    sc.w a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB96_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a5, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw min i16* %a, i16 %b acquire
   ret i16 %1
 }
@@ -4420,6 +8375,83 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_min_i16_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    lhu a0, 0(a0)
+; RV64I-NEXT:    slli a1, a1, 48
+; RV64I-NEXT:    srai s1, a1, 48
+; RV64I-NEXT:    addi s3, sp, 14
+; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:  .LBB97_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    slli a1, a0, 48
+; RV64I-NEXT:    srai a1, a1, 48
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bge s1, a1, .LBB97_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB97_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB97_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB97_1 Depth=1
+; RV64I-NEXT:    sh a0, 14(sp)
+; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_2
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lh a0, 14(sp)
+; RV64I-NEXT:    beqz a1, .LBB97_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_min_i16_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 48
+; RV64IA-NEXT:    sub a6, a3, a2
+; RV64IA-NEXT:    lui a4, 16
+; RV64IA-NEXT:    addiw a4, a4, -1
+; RV64IA-NEXT:    sllw a7, a4, a2
+; RV64IA-NEXT:    slli a1, a1, 48
+; RV64IA-NEXT:    srai a1, a1, 48
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB97_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a5, (a0)
+; RV64IA-NEXT:    and a4, a5, a7
+; RV64IA-NEXT:    mv a3, a5
+; RV64IA-NEXT:    sll a4, a4, a6
+; RV64IA-NEXT:    sra a4, a4, a6
+; RV64IA-NEXT:    bge a1, a4, .LBB97_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB97_1 Depth=1
+; RV64IA-NEXT:    xor a3, a5, a1
+; RV64IA-NEXT:    and a3, a3, a7
+; RV64IA-NEXT:    xor a3, a5, a3
+; RV64IA-NEXT:  .LBB97_3: # in Loop: Header=BB97_1 Depth=1
+; RV64IA-NEXT:    sc.w.rl a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB97_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a5, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw min i16* %a, i16 %b release
   ret i16 %1
 }
@@ -4504,6 +8536,86 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_min_i16_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    lhu a0, 0(a0)
+; RV64I-NEXT:    slli a1, a1, 48
+; RV64I-NEXT:    srai s1, a1, 48
+; RV64I-NEXT:    addi s3, sp, 6
+; RV64I-NEXT:    addi s4, zero, 4
+; RV64I-NEXT:    addi s5, zero, 2
+; RV64I-NEXT:  .LBB98_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    slli a1, a0, 48
+; RV64I-NEXT:    srai a1, a1, 48
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bge s1, a1, .LBB98_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB98_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB98_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB98_1 Depth=1
+; RV64I-NEXT:    sh a0, 6(sp)
+; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    call __atomic_compare_exchange_2
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lh a0, 6(sp)
+; RV64I-NEXT:    beqz a1, .LBB98_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s6, 8(sp)
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_min_i16_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 48
+; RV64IA-NEXT:    sub a6, a3, a2
+; RV64IA-NEXT:    lui a4, 16
+; RV64IA-NEXT:    addiw a4, a4, -1
+; RV64IA-NEXT:    sllw a7, a4, a2
+; RV64IA-NEXT:    slli a1, a1, 48
+; RV64IA-NEXT:    srai a1, a1, 48
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB98_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a5, (a0)
+; RV64IA-NEXT:    and a4, a5, a7
+; RV64IA-NEXT:    mv a3, a5
+; RV64IA-NEXT:    sll a4, a4, a6
+; RV64IA-NEXT:    sra a4, a4, a6
+; RV64IA-NEXT:    bge a1, a4, .LBB98_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB98_1 Depth=1
+; RV64IA-NEXT:    xor a3, a5, a1
+; RV64IA-NEXT:    and a3, a3, a7
+; RV64IA-NEXT:    xor a3, a5, a3
+; RV64IA-NEXT:  .LBB98_3: # in Loop: Header=BB98_1 Depth=1
+; RV64IA-NEXT:    sc.w.rl a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB98_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a5, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw min i16* %a, i16 %b acq_rel
   ret i16 %1
 }
@@ -4585,6 +8697,83 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a5, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_min_i16_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lhu a0, 0(a0)
+; RV64I-NEXT:    slli a1, a1, 48
+; RV64I-NEXT:    srai s5, a1, 48
+; RV64I-NEXT:    addi s3, sp, 14
+; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:  .LBB99_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    slli a1, a0, 48
+; RV64I-NEXT:    srai a1, a1, 48
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bge s5, a1, .LBB99_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB99_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB99_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB99_1 Depth=1
+; RV64I-NEXT:    sh a0, 14(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_2
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lh a0, 14(sp)
+; RV64I-NEXT:    beqz a1, .LBB99_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_min_i16_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    slli a2, a0, 3
+; RV64IA-NEXT:    andi a2, a2, 24
+; RV64IA-NEXT:    addi a3, zero, 48
+; RV64IA-NEXT:    sub a6, a3, a2
+; RV64IA-NEXT:    lui a4, 16
+; RV64IA-NEXT:    addiw a4, a4, -1
+; RV64IA-NEXT:    sllw a7, a4, a2
+; RV64IA-NEXT:    slli a1, a1, 48
+; RV64IA-NEXT:    srai a1, a1, 48
+; RV64IA-NEXT:    sllw a1, a1, a2
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB99_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aqrl a5, (a0)
+; RV64IA-NEXT:    and a4, a5, a7
+; RV64IA-NEXT:    mv a3, a5
+; RV64IA-NEXT:    sll a4, a4, a6
+; RV64IA-NEXT:    sra a4, a4, a6
+; RV64IA-NEXT:    bge a1, a4, .LBB99_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB99_1 Depth=1
+; RV64IA-NEXT:    xor a3, a5, a1
+; RV64IA-NEXT:    and a3, a3, a7
+; RV64IA-NEXT:    xor a3, a5, a3
+; RV64IA-NEXT:  .LBB99_3: # in Loop: Header=BB99_1 Depth=1
+; RV64IA-NEXT:    sc.w.aqrl a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB99_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a5, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw min i16* %a, i16 %b seq_cst
   ret i16 %1
 }
@@ -4660,6 +8849,77 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umax_i16_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lhu a0, 0(a0)
+; RV64I-NEXT:    lui a1, 16
+; RV64I-NEXT:    addiw s1, a1, -1
+; RV64I-NEXT:    and s5, s2, s1
+; RV64I-NEXT:    addi s3, sp, 14
+; RV64I-NEXT:  .LBB100_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    and a1, a0, s1
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bltu s5, a1, .LBB100_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB100_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB100_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB100_1 Depth=1
+; RV64I-NEXT:    sh a0, 14(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, zero
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_2
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lh a0, 14(sp)
+; RV64I-NEXT:    beqz a1, .LBB100_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umax_i16_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a6, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB100_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    and a2, a4, a6
+; RV64IA-NEXT:    mv a5, a4
+; RV64IA-NEXT:    bgeu a2, a1, .LBB100_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB100_1 Depth=1
+; RV64IA-NEXT:    xor a5, a4, a1
+; RV64IA-NEXT:    and a5, a5, a6
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:  .LBB100_3: # in Loop: Header=BB100_1 Depth=1
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB100_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i16* %a, i16 %b monotonic
   ret i16 %1
 }
@@ -4738,6 +8998,80 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umax_i16_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lhu a0, 0(a0)
+; RV64I-NEXT:    lui a1, 16
+; RV64I-NEXT:    addiw s5, a1, -1
+; RV64I-NEXT:    and s6, s2, s5
+; RV64I-NEXT:    addi s3, sp, 6
+; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:  .LBB101_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    and a1, a0, s5
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bltu s6, a1, .LBB101_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB101_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB101_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB101_1 Depth=1
+; RV64I-NEXT:    sh a0, 6(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_2
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lh a0, 6(sp)
+; RV64I-NEXT:    beqz a1, .LBB101_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s6, 8(sp)
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umax_i16_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a6, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB101_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    and a2, a4, a6
+; RV64IA-NEXT:    mv a5, a4
+; RV64IA-NEXT:    bgeu a2, a1, .LBB101_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB101_1 Depth=1
+; RV64IA-NEXT:    xor a5, a4, a1
+; RV64IA-NEXT:    and a5, a5, a6
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:  .LBB101_3: # in Loop: Header=BB101_1 Depth=1
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB101_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i16* %a, i16 %b acquire
   ret i16 %1
 }
@@ -4816,6 +9150,80 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umax_i16_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    lhu a0, 0(a0)
+; RV64I-NEXT:    lui a1, 16
+; RV64I-NEXT:    addiw s1, a1, -1
+; RV64I-NEXT:    and s6, s2, s1
+; RV64I-NEXT:    addi s3, sp, 6
+; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:  .LBB102_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    and a1, a0, s1
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bltu s6, a1, .LBB102_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB102_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB102_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB102_1 Depth=1
+; RV64I-NEXT:    sh a0, 6(sp)
+; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_2
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lh a0, 6(sp)
+; RV64I-NEXT:    beqz a1, .LBB102_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s6, 8(sp)
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umax_i16_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a6, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB102_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    and a2, a4, a6
+; RV64IA-NEXT:    mv a5, a4
+; RV64IA-NEXT:    bgeu a2, a1, .LBB102_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB102_1 Depth=1
+; RV64IA-NEXT:    xor a5, a4, a1
+; RV64IA-NEXT:    and a5, a5, a6
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:  .LBB102_3: # in Loop: Header=BB102_1 Depth=1
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB102_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i16* %a, i16 %b release
   ret i16 %1
 }
@@ -4897,6 +9305,83 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umax_i16_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -80
+; RV64I-NEXT:    sd ra, 72(sp)
+; RV64I-NEXT:    sd s1, 64(sp)
+; RV64I-NEXT:    sd s2, 56(sp)
+; RV64I-NEXT:    sd s3, 48(sp)
+; RV64I-NEXT:    sd s4, 40(sp)
+; RV64I-NEXT:    sd s5, 32(sp)
+; RV64I-NEXT:    sd s6, 24(sp)
+; RV64I-NEXT:    sd s7, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    lhu a0, 0(a0)
+; RV64I-NEXT:    lui a1, 16
+; RV64I-NEXT:    addiw s1, a1, -1
+; RV64I-NEXT:    and s7, s2, s1
+; RV64I-NEXT:    addi s3, sp, 14
+; RV64I-NEXT:    addi s4, zero, 4
+; RV64I-NEXT:    addi s5, zero, 2
+; RV64I-NEXT:  .LBB103_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    and a1, a0, s1
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bltu s7, a1, .LBB103_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB103_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB103_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB103_1 Depth=1
+; RV64I-NEXT:    sh a0, 14(sp)
+; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    call __atomic_compare_exchange_2
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lh a0, 14(sp)
+; RV64I-NEXT:    beqz a1, .LBB103_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s7, 16(sp)
+; RV64I-NEXT:    ld s6, 24(sp)
+; RV64I-NEXT:    ld s5, 32(sp)
+; RV64I-NEXT:    ld s4, 40(sp)
+; RV64I-NEXT:    ld s3, 48(sp)
+; RV64I-NEXT:    ld s2, 56(sp)
+; RV64I-NEXT:    ld s1, 64(sp)
+; RV64I-NEXT:    ld ra, 72(sp)
+; RV64I-NEXT:    addi sp, sp, 80
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umax_i16_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a6, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB103_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    and a2, a4, a6
+; RV64IA-NEXT:    mv a5, a4
+; RV64IA-NEXT:    bgeu a2, a1, .LBB103_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB103_1 Depth=1
+; RV64IA-NEXT:    xor a5, a4, a1
+; RV64IA-NEXT:    and a5, a5, a6
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:  .LBB103_3: # in Loop: Header=BB103_1 Depth=1
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB103_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i16* %a, i16 %b acq_rel
   ret i16 %1
 }
@@ -4975,6 +9460,80 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umax_i16_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lhu a0, 0(a0)
+; RV64I-NEXT:    lui a1, 16
+; RV64I-NEXT:    addiw s5, a1, -1
+; RV64I-NEXT:    and s6, s2, s5
+; RV64I-NEXT:    addi s3, sp, 6
+; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:  .LBB104_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    and a1, a0, s5
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bltu s6, a1, .LBB104_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB104_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB104_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB104_1 Depth=1
+; RV64I-NEXT:    sh a0, 6(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_2
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lh a0, 6(sp)
+; RV64I-NEXT:    beqz a1, .LBB104_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s6, 8(sp)
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umax_i16_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a6, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB104_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aqrl a4, (a0)
+; RV64IA-NEXT:    and a2, a4, a6
+; RV64IA-NEXT:    mv a5, a4
+; RV64IA-NEXT:    bgeu a2, a1, .LBB104_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB104_1 Depth=1
+; RV64IA-NEXT:    xor a5, a4, a1
+; RV64IA-NEXT:    and a5, a5, a6
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:  .LBB104_3: # in Loop: Header=BB104_1 Depth=1
+; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB104_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i16* %a, i16 %b seq_cst
   ret i16 %1
 }
@@ -5050,6 +9609,77 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umin_i16_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lhu a0, 0(a0)
+; RV64I-NEXT:    lui a1, 16
+; RV64I-NEXT:    addiw s1, a1, -1
+; RV64I-NEXT:    and s5, s2, s1
+; RV64I-NEXT:    addi s3, sp, 14
+; RV64I-NEXT:  .LBB105_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    and a1, a0, s1
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bgeu s5, a1, .LBB105_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB105_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB105_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB105_1 Depth=1
+; RV64I-NEXT:    sh a0, 14(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, zero
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_2
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lh a0, 14(sp)
+; RV64I-NEXT:    beqz a1, .LBB105_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umin_i16_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a6, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB105_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    and a2, a4, a6
+; RV64IA-NEXT:    mv a5, a4
+; RV64IA-NEXT:    bgeu a1, a2, .LBB105_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB105_1 Depth=1
+; RV64IA-NEXT:    xor a5, a4, a1
+; RV64IA-NEXT:    and a5, a5, a6
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:  .LBB105_3: # in Loop: Header=BB105_1 Depth=1
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB105_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i16* %a, i16 %b monotonic
   ret i16 %1
 }
@@ -5128,6 +9758,80 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umin_i16_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lhu a0, 0(a0)
+; RV64I-NEXT:    lui a1, 16
+; RV64I-NEXT:    addiw s5, a1, -1
+; RV64I-NEXT:    and s6, s2, s5
+; RV64I-NEXT:    addi s3, sp, 6
+; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:  .LBB106_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    and a1, a0, s5
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bgeu s6, a1, .LBB106_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB106_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB106_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB106_1 Depth=1
+; RV64I-NEXT:    sh a0, 6(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_2
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lh a0, 6(sp)
+; RV64I-NEXT:    beqz a1, .LBB106_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s6, 8(sp)
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umin_i16_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a6, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB106_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    and a2, a4, a6
+; RV64IA-NEXT:    mv a5, a4
+; RV64IA-NEXT:    bgeu a1, a2, .LBB106_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB106_1 Depth=1
+; RV64IA-NEXT:    xor a5, a4, a1
+; RV64IA-NEXT:    and a5, a5, a6
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:  .LBB106_3: # in Loop: Header=BB106_1 Depth=1
+; RV64IA-NEXT:    sc.w a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB106_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i16* %a, i16 %b acquire
   ret i16 %1
 }
@@ -5206,6 +9910,80 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umin_i16_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    lhu a0, 0(a0)
+; RV64I-NEXT:    lui a1, 16
+; RV64I-NEXT:    addiw s1, a1, -1
+; RV64I-NEXT:    and s6, s2, s1
+; RV64I-NEXT:    addi s3, sp, 6
+; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:  .LBB107_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    and a1, a0, s1
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bgeu s6, a1, .LBB107_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB107_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB107_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB107_1 Depth=1
+; RV64I-NEXT:    sh a0, 6(sp)
+; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_2
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lh a0, 6(sp)
+; RV64I-NEXT:    beqz a1, .LBB107_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s6, 8(sp)
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umin_i16_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a6, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB107_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a4, (a0)
+; RV64IA-NEXT:    and a2, a4, a6
+; RV64IA-NEXT:    mv a5, a4
+; RV64IA-NEXT:    bgeu a1, a2, .LBB107_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB107_1 Depth=1
+; RV64IA-NEXT:    xor a5, a4, a1
+; RV64IA-NEXT:    and a5, a5, a6
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:  .LBB107_3: # in Loop: Header=BB107_1 Depth=1
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB107_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i16* %a, i16 %b release
   ret i16 %1
 }
@@ -5287,6 +10065,83 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umin_i16_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -80
+; RV64I-NEXT:    sd ra, 72(sp)
+; RV64I-NEXT:    sd s1, 64(sp)
+; RV64I-NEXT:    sd s2, 56(sp)
+; RV64I-NEXT:    sd s3, 48(sp)
+; RV64I-NEXT:    sd s4, 40(sp)
+; RV64I-NEXT:    sd s5, 32(sp)
+; RV64I-NEXT:    sd s6, 24(sp)
+; RV64I-NEXT:    sd s7, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    lhu a0, 0(a0)
+; RV64I-NEXT:    lui a1, 16
+; RV64I-NEXT:    addiw s1, a1, -1
+; RV64I-NEXT:    and s7, s2, s1
+; RV64I-NEXT:    addi s3, sp, 14
+; RV64I-NEXT:    addi s4, zero, 4
+; RV64I-NEXT:    addi s5, zero, 2
+; RV64I-NEXT:  .LBB108_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    and a1, a0, s1
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bgeu s7, a1, .LBB108_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB108_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB108_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB108_1 Depth=1
+; RV64I-NEXT:    sh a0, 14(sp)
+; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    call __atomic_compare_exchange_2
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lh a0, 14(sp)
+; RV64I-NEXT:    beqz a1, .LBB108_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s7, 16(sp)
+; RV64I-NEXT:    ld s6, 24(sp)
+; RV64I-NEXT:    ld s5, 32(sp)
+; RV64I-NEXT:    ld s4, 40(sp)
+; RV64I-NEXT:    ld s3, 48(sp)
+; RV64I-NEXT:    ld s2, 56(sp)
+; RV64I-NEXT:    ld s1, 64(sp)
+; RV64I-NEXT:    ld ra, 72(sp)
+; RV64I-NEXT:    addi sp, sp, 80
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umin_i16_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a6, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB108_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a4, (a0)
+; RV64IA-NEXT:    and a2, a4, a6
+; RV64IA-NEXT:    mv a5, a4
+; RV64IA-NEXT:    bgeu a1, a2, .LBB108_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB108_1 Depth=1
+; RV64IA-NEXT:    xor a5, a4, a1
+; RV64IA-NEXT:    and a5, a5, a6
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:  .LBB108_3: # in Loop: Header=BB108_1 Depth=1
+; RV64IA-NEXT:    sc.w.rl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB108_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i16* %a, i16 %b acq_rel
   ret i16 %1
 }
@@ -5365,6 +10220,80 @@
 ; RV32IA-NEXT:  # %bb.4:
 ; RV32IA-NEXT:    srl a0, a4, a3
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umin_i16_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lhu a0, 0(a0)
+; RV64I-NEXT:    lui a1, 16
+; RV64I-NEXT:    addiw s5, a1, -1
+; RV64I-NEXT:    and s6, s2, s5
+; RV64I-NEXT:    addi s3, sp, 6
+; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:  .LBB109_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    and a1, a0, s5
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bgeu s6, a1, .LBB109_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB109_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB109_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB109_1 Depth=1
+; RV64I-NEXT:    sh a0, 6(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_2
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lh a0, 6(sp)
+; RV64I-NEXT:    beqz a1, .LBB109_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s6, 8(sp)
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umin_i16_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    lui a2, 16
+; RV64IA-NEXT:    addiw a2, a2, -1
+; RV64IA-NEXT:    and a1, a1, a2
+; RV64IA-NEXT:    slli a3, a0, 3
+; RV64IA-NEXT:    andi a3, a3, 24
+; RV64IA-NEXT:    sllw a6, a2, a3
+; RV64IA-NEXT:    sllw a1, a1, a3
+; RV64IA-NEXT:    andi a0, a0, -4
+; RV64IA-NEXT:  .LBB109_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aqrl a4, (a0)
+; RV64IA-NEXT:    and a2, a4, a6
+; RV64IA-NEXT:    mv a5, a4
+; RV64IA-NEXT:    bgeu a1, a2, .LBB109_3
+; RV64IA-NEXT:  # %bb.2: # in Loop: Header=BB109_1 Depth=1
+; RV64IA-NEXT:    xor a5, a4, a1
+; RV64IA-NEXT:    and a5, a5, a6
+; RV64IA-NEXT:    xor a5, a4, a5
+; RV64IA-NEXT:  .LBB109_3: # in Loop: Header=BB109_1 Depth=1
+; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a0)
+; RV64IA-NEXT:    bnez a5, .LBB109_1
+; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:    srlw a0, a4, a3
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i16* %a, i16 %b seq_cst
   ret i16 %1
 }
@@ -5384,6 +10313,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoswap.w a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xchg_i32_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_exchange_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xchg_i32_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoswap.w a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i32* %a, i32 %b monotonic
   ret i32 %1
 }
@@ -5403,6 +10347,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoswap.w.aq a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xchg_i32_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_exchange_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xchg_i32_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoswap.w.aq a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i32* %a, i32 %b acquire
   ret i32 %1
 }
@@ -5422,6 +10381,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoswap.w.rl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xchg_i32_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_exchange_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xchg_i32_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoswap.w.rl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i32* %a, i32 %b release
   ret i32 %1
 }
@@ -5441,6 +10415,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoswap.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xchg_i32_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_exchange_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xchg_i32_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoswap.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i32* %a, i32 %b acq_rel
   ret i32 %1
 }
@@ -5460,6 +10449,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoswap.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xchg_i32_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_exchange_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xchg_i32_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoswap.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i32* %a, i32 %b seq_cst
   ret i32 %1
 }
@@ -5479,6 +10483,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoadd.w a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_add_i32_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_add_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_add_i32_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoadd.w a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw add i32* %a, i32 %b monotonic
   ret i32 %1
 }
@@ -5498,6 +10517,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoadd.w.aq a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_add_i32_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_add_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_add_i32_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoadd.w.aq a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw add i32* %a, i32 %b acquire
   ret i32 %1
 }
@@ -5517,6 +10551,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoadd.w.rl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_add_i32_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_add_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_add_i32_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoadd.w.rl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw add i32* %a, i32 %b release
   ret i32 %1
 }
@@ -5536,6 +10585,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoadd.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_add_i32_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_add_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_add_i32_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoadd.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw add i32* %a, i32 %b acq_rel
   ret i32 %1
 }
@@ -5555,6 +10619,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoadd.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_add_i32_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_add_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_add_i32_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoadd.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw add i32* %a, i32 %b seq_cst
   ret i32 %1
 }
@@ -5575,6 +10654,22 @@
 ; RV32IA-NEXT:    neg a1, a1
 ; RV32IA-NEXT:    amoadd.w a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_sub_i32_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_sub_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_sub_i32_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    neg a1, a1
+; RV64IA-NEXT:    amoadd.w a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i32* %a, i32 %b monotonic
   ret i32 %1
 }
@@ -5595,6 +10690,22 @@
 ; RV32IA-NEXT:    neg a1, a1
 ; RV32IA-NEXT:    amoadd.w.aq a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_sub_i32_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_sub_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_sub_i32_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    neg a1, a1
+; RV64IA-NEXT:    amoadd.w.aq a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i32* %a, i32 %b acquire
   ret i32 %1
 }
@@ -5615,6 +10726,22 @@
 ; RV32IA-NEXT:    neg a1, a1
 ; RV32IA-NEXT:    amoadd.w.rl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_sub_i32_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_sub_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_sub_i32_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    neg a1, a1
+; RV64IA-NEXT:    amoadd.w.rl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i32* %a, i32 %b release
   ret i32 %1
 }
@@ -5635,6 +10762,22 @@
 ; RV32IA-NEXT:    neg a1, a1
 ; RV32IA-NEXT:    amoadd.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_sub_i32_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_sub_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_sub_i32_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    neg a1, a1
+; RV64IA-NEXT:    amoadd.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i32* %a, i32 %b acq_rel
   ret i32 %1
 }
@@ -5655,6 +10798,22 @@
 ; RV32IA-NEXT:    neg a1, a1
 ; RV32IA-NEXT:    amoadd.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_sub_i32_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_sub_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_sub_i32_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    neg a1, a1
+; RV64IA-NEXT:    amoadd.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i32* %a, i32 %b seq_cst
   ret i32 %1
 }
@@ -5674,6 +10833,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoand.w a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_and_i32_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_and_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_and_i32_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoand.w a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw and i32* %a, i32 %b monotonic
   ret i32 %1
 }
@@ -5693,6 +10867,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoand.w.aq a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_and_i32_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_and_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_and_i32_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoand.w.aq a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw and i32* %a, i32 %b acquire
   ret i32 %1
 }
@@ -5712,6 +10901,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoand.w.rl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_and_i32_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_and_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_and_i32_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoand.w.rl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw and i32* %a, i32 %b release
   ret i32 %1
 }
@@ -5731,6 +10935,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoand.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_and_i32_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_and_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_and_i32_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoand.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw and i32* %a, i32 %b acq_rel
   ret i32 %1
 }
@@ -5750,6 +10969,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoand.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_and_i32_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_and_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_and_i32_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoand.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw and i32* %a, i32 %b seq_cst
   ret i32 %1
 }
@@ -5776,6 +11010,28 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    mv a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_nand_i32_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_nand_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_nand_i32_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:  .LBB130_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a2, (a0)
+; RV64IA-NEXT:    and a3, a2, a1
+; RV64IA-NEXT:    not a3, a3
+; RV64IA-NEXT:    sc.w a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB130_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    mv a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i32* %a, i32 %b monotonic
   ret i32 %1
 }
@@ -5802,6 +11058,28 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    mv a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_nand_i32_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_nand_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_nand_i32_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:  .LBB131_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a2, (a0)
+; RV64IA-NEXT:    and a3, a2, a1
+; RV64IA-NEXT:    not a3, a3
+; RV64IA-NEXT:    sc.w a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB131_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    mv a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i32* %a, i32 %b acquire
   ret i32 %1
 }
@@ -5828,6 +11106,28 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    mv a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_nand_i32_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_nand_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_nand_i32_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:  .LBB132_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w a2, (a0)
+; RV64IA-NEXT:    and a3, a2, a1
+; RV64IA-NEXT:    not a3, a3
+; RV64IA-NEXT:    sc.w.rl a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB132_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    mv a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i32* %a, i32 %b release
   ret i32 %1
 }
@@ -5854,6 +11154,28 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    mv a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_nand_i32_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_nand_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_nand_i32_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:  .LBB133_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aq a2, (a0)
+; RV64IA-NEXT:    and a3, a2, a1
+; RV64IA-NEXT:    not a3, a3
+; RV64IA-NEXT:    sc.w.rl a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB133_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    mv a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i32* %a, i32 %b acq_rel
   ret i32 %1
 }
@@ -5880,6 +11202,28 @@
 ; RV32IA-NEXT:  # %bb.2:
 ; RV32IA-NEXT:    mv a0, a2
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_nand_i32_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_nand_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_nand_i32_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:  .LBB134_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.w.aqrl a2, (a0)
+; RV64IA-NEXT:    and a3, a2, a1
+; RV64IA-NEXT:    not a3, a3
+; RV64IA-NEXT:    sc.w.aqrl a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB134_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    mv a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i32* %a, i32 %b seq_cst
   ret i32 %1
 }
@@ -5899,6 +11243,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoor.w a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_or_i32_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_or_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_or_i32_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoor.w a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw or i32* %a, i32 %b monotonic
   ret i32 %1
 }
@@ -5918,6 +11277,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoor.w.aq a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_or_i32_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_or_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_or_i32_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoor.w.aq a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw or i32* %a, i32 %b acquire
   ret i32 %1
 }
@@ -5937,6 +11311,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoor.w.rl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_or_i32_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_or_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_or_i32_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoor.w.rl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw or i32* %a, i32 %b release
   ret i32 %1
 }
@@ -5956,6 +11345,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoor.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_or_i32_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_or_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_or_i32_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoor.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw or i32* %a, i32 %b acq_rel
   ret i32 %1
 }
@@ -5975,6 +11379,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoor.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_or_i32_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_or_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_or_i32_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoor.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw or i32* %a, i32 %b seq_cst
   ret i32 %1
 }
@@ -5994,6 +11413,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoxor.w a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xor_i32_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_xor_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xor_i32_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoxor.w a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i32* %a, i32 %b monotonic
   ret i32 %1
 }
@@ -6013,6 +11447,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoxor.w.aq a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xor_i32_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_xor_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xor_i32_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoxor.w.aq a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i32* %a, i32 %b acquire
   ret i32 %1
 }
@@ -6032,6 +11481,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoxor.w.rl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xor_i32_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_xor_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xor_i32_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoxor.w.rl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i32* %a, i32 %b release
   ret i32 %1
 }
@@ -6051,6 +11515,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoxor.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xor_i32_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_xor_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xor_i32_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoxor.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i32* %a, i32 %b acq_rel
   ret i32 %1
 }
@@ -6070,6 +11549,21 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amoxor.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xor_i32_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_xor_4
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xor_i32_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoxor.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i32* %a, i32 %b seq_cst
   ret i32 %1
 }
@@ -6115,6 +11609,52 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amomax.w a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_max_i32_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lwu a0, 0(a0)
+; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    addi s3, sp, 4
+; RV64I-NEXT:  .LBB145_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    blt s1, a1, .LBB145_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB145_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB145_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB145_1 Depth=1
+; RV64I-NEXT:    sw a0, 4(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, zero
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_4
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lw a0, 4(sp)
+; RV64I-NEXT:    beqz a1, .LBB145_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_max_i32_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomax.w a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw max i32* %a, i32 %b monotonic
   ret i32 %1
 }
@@ -6163,6 +11703,55 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amomax.w.aq a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_max_i32_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lwu a0, 0(a0)
+; RV64I-NEXT:    sext.w s5, a1
+; RV64I-NEXT:    addi s3, sp, 12
+; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:  .LBB146_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    blt s5, a1, .LBB146_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB146_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB146_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB146_1 Depth=1
+; RV64I-NEXT:    sw a0, 12(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_4
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    beqz a1, .LBB146_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_max_i32_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomax.w.aq a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw max i32* %a, i32 %b acquire
   ret i32 %1
 }
@@ -6211,6 +11800,55 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amomax.w.rl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_max_i32_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    lwu a0, 0(a0)
+; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    addi s3, sp, 12
+; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:  .LBB147_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    blt s1, a1, .LBB147_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB147_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB147_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB147_1 Depth=1
+; RV64I-NEXT:    sw a0, 12(sp)
+; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_4
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    beqz a1, .LBB147_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_max_i32_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomax.w.rl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw max i32* %a, i32 %b release
   ret i32 %1
 }
@@ -6262,6 +11900,58 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amomax.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_max_i32_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    lwu a0, 0(a0)
+; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    addi s3, sp, 4
+; RV64I-NEXT:    addi s4, zero, 4
+; RV64I-NEXT:    addi s5, zero, 2
+; RV64I-NEXT:  .LBB148_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    blt s1, a1, .LBB148_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB148_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB148_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB148_1 Depth=1
+; RV64I-NEXT:    sw a0, 4(sp)
+; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    call __atomic_compare_exchange_4
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lw a0, 4(sp)
+; RV64I-NEXT:    beqz a1, .LBB148_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s6, 8(sp)
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_max_i32_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomax.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw max i32* %a, i32 %b acq_rel
   ret i32 %1
 }
@@ -6310,6 +12000,55 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amomax.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_max_i32_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lwu a0, 0(a0)
+; RV64I-NEXT:    sext.w s5, a1
+; RV64I-NEXT:    addi s3, sp, 12
+; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:  .LBB149_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    blt s5, a1, .LBB149_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB149_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB149_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB149_1 Depth=1
+; RV64I-NEXT:    sw a0, 12(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_4
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    beqz a1, .LBB149_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_max_i32_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomax.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw max i32* %a, i32 %b seq_cst
   ret i32 %1
 }
@@ -6355,6 +12094,52 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amomin.w a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_min_i32_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lwu a0, 0(a0)
+; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    addi s3, sp, 4
+; RV64I-NEXT:  .LBB150_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bge s1, a1, .LBB150_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB150_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB150_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB150_1 Depth=1
+; RV64I-NEXT:    sw a0, 4(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, zero
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_4
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lw a0, 4(sp)
+; RV64I-NEXT:    beqz a1, .LBB150_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_min_i32_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomin.w a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw min i32* %a, i32 %b monotonic
   ret i32 %1
 }
@@ -6403,6 +12188,55 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amomin.w.aq a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_min_i32_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lwu a0, 0(a0)
+; RV64I-NEXT:    sext.w s5, a1
+; RV64I-NEXT:    addi s3, sp, 12
+; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:  .LBB151_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bge s5, a1, .LBB151_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB151_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB151_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB151_1 Depth=1
+; RV64I-NEXT:    sw a0, 12(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_4
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    beqz a1, .LBB151_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_min_i32_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomin.w.aq a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw min i32* %a, i32 %b acquire
   ret i32 %1
 }
@@ -6451,6 +12285,55 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amomin.w.rl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_min_i32_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    lwu a0, 0(a0)
+; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    addi s3, sp, 12
+; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:  .LBB152_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bge s1, a1, .LBB152_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB152_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB152_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB152_1 Depth=1
+; RV64I-NEXT:    sw a0, 12(sp)
+; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_4
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    beqz a1, .LBB152_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_min_i32_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomin.w.rl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw min i32* %a, i32 %b release
   ret i32 %1
 }
@@ -6502,6 +12385,58 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amomin.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_min_i32_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    lwu a0, 0(a0)
+; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    addi s3, sp, 4
+; RV64I-NEXT:    addi s4, zero, 4
+; RV64I-NEXT:    addi s5, zero, 2
+; RV64I-NEXT:  .LBB153_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bge s1, a1, .LBB153_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB153_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB153_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB153_1 Depth=1
+; RV64I-NEXT:    sw a0, 4(sp)
+; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    call __atomic_compare_exchange_4
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lw a0, 4(sp)
+; RV64I-NEXT:    beqz a1, .LBB153_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s6, 8(sp)
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_min_i32_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomin.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw min i32* %a, i32 %b acq_rel
   ret i32 %1
 }
@@ -6550,6 +12485,55 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amomin.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_min_i32_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lwu a0, 0(a0)
+; RV64I-NEXT:    sext.w s5, a1
+; RV64I-NEXT:    addi s3, sp, 12
+; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:  .LBB154_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bge s5, a1, .LBB154_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB154_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB154_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB154_1 Depth=1
+; RV64I-NEXT:    sw a0, 12(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_4
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    beqz a1, .LBB154_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_min_i32_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomin.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw min i32* %a, i32 %b seq_cst
   ret i32 %1
 }
@@ -6595,6 +12579,52 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amomaxu.w a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umax_i32_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lwu a0, 0(a0)
+; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    addi s3, sp, 4
+; RV64I-NEXT:  .LBB155_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bltu s1, a1, .LBB155_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB155_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB155_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB155_1 Depth=1
+; RV64I-NEXT:    sw a0, 4(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, zero
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_4
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lw a0, 4(sp)
+; RV64I-NEXT:    beqz a1, .LBB155_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umax_i32_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomaxu.w a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i32* %a, i32 %b monotonic
   ret i32 %1
 }
@@ -6643,6 +12673,55 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amomaxu.w.aq a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umax_i32_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lwu a0, 0(a0)
+; RV64I-NEXT:    sext.w s5, a1
+; RV64I-NEXT:    addi s3, sp, 12
+; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:  .LBB156_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bltu s5, a1, .LBB156_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB156_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB156_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB156_1 Depth=1
+; RV64I-NEXT:    sw a0, 12(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_4
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    beqz a1, .LBB156_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umax_i32_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomaxu.w.aq a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i32* %a, i32 %b acquire
   ret i32 %1
 }
@@ -6691,6 +12770,55 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amomaxu.w.rl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umax_i32_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    lwu a0, 0(a0)
+; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    addi s3, sp, 12
+; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:  .LBB157_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bltu s1, a1, .LBB157_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB157_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB157_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB157_1 Depth=1
+; RV64I-NEXT:    sw a0, 12(sp)
+; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_4
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    beqz a1, .LBB157_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umax_i32_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomaxu.w.rl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i32* %a, i32 %b release
   ret i32 %1
 }
@@ -6742,6 +12870,58 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amomaxu.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umax_i32_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    lwu a0, 0(a0)
+; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    addi s3, sp, 4
+; RV64I-NEXT:    addi s4, zero, 4
+; RV64I-NEXT:    addi s5, zero, 2
+; RV64I-NEXT:  .LBB158_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bltu s1, a1, .LBB158_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB158_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB158_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB158_1 Depth=1
+; RV64I-NEXT:    sw a0, 4(sp)
+; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    call __atomic_compare_exchange_4
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lw a0, 4(sp)
+; RV64I-NEXT:    beqz a1, .LBB158_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s6, 8(sp)
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umax_i32_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomaxu.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i32* %a, i32 %b acq_rel
   ret i32 %1
 }
@@ -6790,6 +12970,55 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amomaxu.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umax_i32_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lwu a0, 0(a0)
+; RV64I-NEXT:    sext.w s5, a1
+; RV64I-NEXT:    addi s3, sp, 12
+; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:  .LBB159_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bltu s5, a1, .LBB159_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB159_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB159_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB159_1 Depth=1
+; RV64I-NEXT:    sw a0, 12(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_4
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    beqz a1, .LBB159_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umax_i32_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomaxu.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i32* %a, i32 %b seq_cst
   ret i32 %1
 }
@@ -6835,6 +13064,52 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amominu.w a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umin_i32_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lwu a0, 0(a0)
+; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    addi s3, sp, 4
+; RV64I-NEXT:  .LBB160_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bgeu s1, a1, .LBB160_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB160_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB160_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB160_1 Depth=1
+; RV64I-NEXT:    sw a0, 4(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, zero
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_4
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lw a0, 4(sp)
+; RV64I-NEXT:    beqz a1, .LBB160_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umin_i32_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amominu.w a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i32* %a, i32 %b monotonic
   ret i32 %1
 }
@@ -6883,6 +13158,55 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amominu.w.aq a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umin_i32_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lwu a0, 0(a0)
+; RV64I-NEXT:    sext.w s5, a1
+; RV64I-NEXT:    addi s3, sp, 12
+; RV64I-NEXT:    addi s1, zero, 2
+; RV64I-NEXT:  .LBB161_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bgeu s5, a1, .LBB161_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB161_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB161_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB161_1 Depth=1
+; RV64I-NEXT:    sw a0, 12(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_4
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    beqz a1, .LBB161_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umin_i32_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amominu.w.aq a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i32* %a, i32 %b acquire
   ret i32 %1
 }
@@ -6931,6 +13255,55 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amominu.w.rl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umin_i32_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s5, a0
+; RV64I-NEXT:    lwu a0, 0(a0)
+; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    addi s3, sp, 12
+; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:  .LBB162_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bgeu s1, a1, .LBB162_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB162_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB162_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB162_1 Depth=1
+; RV64I-NEXT:    sw a0, 12(sp)
+; RV64I-NEXT:    mv a0, s5
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_4
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    beqz a1, .LBB162_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umin_i32_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amominu.w.rl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i32* %a, i32 %b release
   ret i32 %1
 }
@@ -6982,6 +13355,58 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amominu.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umin_i32_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    sd s6, 8(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s6, a0
+; RV64I-NEXT:    lwu a0, 0(a0)
+; RV64I-NEXT:    sext.w s1, a1
+; RV64I-NEXT:    addi s3, sp, 4
+; RV64I-NEXT:    addi s4, zero, 4
+; RV64I-NEXT:    addi s5, zero, 2
+; RV64I-NEXT:  .LBB163_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bgeu s1, a1, .LBB163_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB163_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB163_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB163_1 Depth=1
+; RV64I-NEXT:    sw a0, 4(sp)
+; RV64I-NEXT:    mv a0, s6
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    call __atomic_compare_exchange_4
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lw a0, 4(sp)
+; RV64I-NEXT:    beqz a1, .LBB163_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s6, 8(sp)
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umin_i32_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amominu.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i32* %a, i32 %b acq_rel
   ret i32 %1
 }
@@ -7030,6 +13455,55 @@
 ; RV32IA:       # %bb.0:
 ; RV32IA-NEXT:    amominu.w.aqrl a0, a1, (a0)
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umin_i32_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s2, a1
+; RV64I-NEXT:    mv s4, a0
+; RV64I-NEXT:    lwu a0, 0(a0)
+; RV64I-NEXT:    sext.w s5, a1
+; RV64I-NEXT:    addi s3, sp, 12
+; RV64I-NEXT:    addi s1, zero, 5
+; RV64I-NEXT:  .LBB164_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sext.w a1, a0
+; RV64I-NEXT:    mv a2, a0
+; RV64I-NEXT:    bgeu s5, a1, .LBB164_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB164_1 Depth=1
+; RV64I-NEXT:    mv a2, s2
+; RV64I-NEXT:  .LBB164_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB164_1 Depth=1
+; RV64I-NEXT:    sw a0, 12(sp)
+; RV64I-NEXT:    mv a0, s4
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s1
+; RV64I-NEXT:    mv a4, s1
+; RV64I-NEXT:    call __atomic_compare_exchange_4
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    lw a0, 12(sp)
+; RV64I-NEXT:    beqz a1, .LBB164_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umin_i32_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amominu.w.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i32* %a, i32 %b seq_cst
   ret i32 %1
 }
@@ -7054,6 +13528,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xchg_i64_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_exchange_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xchg_i64_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoswap.d a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i64* %a, i64 %b monotonic
   ret i64 %1
 }
@@ -7078,6 +13567,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xchg_i64_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_exchange_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xchg_i64_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoswap.d.aq a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i64* %a, i64 %b acquire
   ret i64 %1
 }
@@ -7102,6 +13606,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xchg_i64_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_exchange_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xchg_i64_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoswap.d.rl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i64* %a, i64 %b release
   ret i64 %1
 }
@@ -7126,6 +13645,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xchg_i64_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_exchange_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xchg_i64_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoswap.d.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i64* %a, i64 %b acq_rel
   ret i64 %1
 }
@@ -7150,6 +13684,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xchg_i64_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_exchange_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xchg_i64_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoswap.d.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xchg i64* %a, i64 %b seq_cst
   ret i64 %1
 }
@@ -7174,6 +13723,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_add_i64_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_add_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_add_i64_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoadd.d a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw add i64* %a, i64 %b monotonic
   ret i64 %1
 }
@@ -7198,6 +13762,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_add_i64_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_add_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_add_i64_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoadd.d.aq a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw add i64* %a, i64 %b acquire
   ret i64 %1
 }
@@ -7222,6 +13801,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_add_i64_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_add_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_add_i64_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoadd.d.rl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw add i64* %a, i64 %b release
   ret i64 %1
 }
@@ -7246,6 +13840,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_add_i64_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_add_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_add_i64_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoadd.d.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw add i64* %a, i64 %b acq_rel
   ret i64 %1
 }
@@ -7270,6 +13879,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_add_i64_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_add_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_add_i64_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoadd.d.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw add i64* %a, i64 %b seq_cst
   ret i64 %1
 }
@@ -7294,6 +13918,22 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_sub_i64_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_sub_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_sub_i64_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    neg a1, a1
+; RV64IA-NEXT:    amoadd.d a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i64* %a, i64 %b monotonic
   ret i64 %1
 }
@@ -7318,6 +13958,22 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_sub_i64_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_sub_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_sub_i64_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    neg a1, a1
+; RV64IA-NEXT:    amoadd.d.aq a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i64* %a, i64 %b acquire
   ret i64 %1
 }
@@ -7342,6 +13998,22 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_sub_i64_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_sub_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_sub_i64_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    neg a1, a1
+; RV64IA-NEXT:    amoadd.d.rl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i64* %a, i64 %b release
   ret i64 %1
 }
@@ -7366,6 +14038,22 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_sub_i64_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_sub_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_sub_i64_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    neg a1, a1
+; RV64IA-NEXT:    amoadd.d.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i64* %a, i64 %b acq_rel
   ret i64 %1
 }
@@ -7390,6 +14078,22 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_sub_i64_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_sub_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_sub_i64_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    neg a1, a1
+; RV64IA-NEXT:    amoadd.d.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw sub i64* %a, i64 %b seq_cst
   ret i64 %1
 }
@@ -7414,6 +14118,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_and_i64_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_and_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_and_i64_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoand.d a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw and i64* %a, i64 %b monotonic
   ret i64 %1
 }
@@ -7438,6 +14157,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_and_i64_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_and_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_and_i64_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoand.d.aq a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw and i64* %a, i64 %b acquire
   ret i64 %1
 }
@@ -7462,6 +14196,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_and_i64_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_and_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_and_i64_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoand.d.rl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw and i64* %a, i64 %b release
   ret i64 %1
 }
@@ -7486,6 +14235,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_and_i64_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_and_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_and_i64_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoand.d.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw and i64* %a, i64 %b acq_rel
   ret i64 %1
 }
@@ -7510,6 +14274,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_and_i64_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_and_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_and_i64_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoand.d.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw and i64* %a, i64 %b seq_cst
   ret i64 %1
 }
@@ -7534,6 +14313,28 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_nand_i64_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_nand_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_nand_i64_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:  .LBB185_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.d a2, (a0)
+; RV64IA-NEXT:    and a3, a2, a1
+; RV64IA-NEXT:    not a3, a3
+; RV64IA-NEXT:    sc.d a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB185_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    mv a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i64* %a, i64 %b monotonic
   ret i64 %1
 }
@@ -7558,6 +14359,28 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_nand_i64_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_nand_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_nand_i64_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:  .LBB186_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.d.aq a2, (a0)
+; RV64IA-NEXT:    and a3, a2, a1
+; RV64IA-NEXT:    not a3, a3
+; RV64IA-NEXT:    sc.d a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB186_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    mv a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i64* %a, i64 %b acquire
   ret i64 %1
 }
@@ -7582,6 +14405,28 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_nand_i64_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_nand_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_nand_i64_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:  .LBB187_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.d a2, (a0)
+; RV64IA-NEXT:    and a3, a2, a1
+; RV64IA-NEXT:    not a3, a3
+; RV64IA-NEXT:    sc.d.rl a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB187_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    mv a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i64* %a, i64 %b release
   ret i64 %1
 }
@@ -7606,6 +14451,28 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_nand_i64_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_nand_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_nand_i64_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:  .LBB188_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.d.aq a2, (a0)
+; RV64IA-NEXT:    and a3, a2, a1
+; RV64IA-NEXT:    not a3, a3
+; RV64IA-NEXT:    sc.d.rl a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB188_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    mv a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i64* %a, i64 %b acq_rel
   ret i64 %1
 }
@@ -7630,6 +14497,28 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_nand_i64_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_nand_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_nand_i64_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:  .LBB189_1: # =>This Inner Loop Header: Depth=1
+; RV64IA-NEXT:    lr.d.aqrl a2, (a0)
+; RV64IA-NEXT:    and a3, a2, a1
+; RV64IA-NEXT:    not a3, a3
+; RV64IA-NEXT:    sc.d.aqrl a3, a3, (a0)
+; RV64IA-NEXT:    bnez a3, .LBB189_1
+; RV64IA-NEXT:  # %bb.2:
+; RV64IA-NEXT:    mv a0, a2
+; RV64IA-NEXT:    ret
   %1 = atomicrmw nand i64* %a, i64 %b seq_cst
   ret i64 %1
 }
@@ -7654,6 +14543,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_or_i64_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_or_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_or_i64_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoor.d a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw or i64* %a, i64 %b monotonic
   ret i64 %1
 }
@@ -7678,6 +14582,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_or_i64_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_or_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_or_i64_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoor.d.aq a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw or i64* %a, i64 %b acquire
   ret i64 %1
 }
@@ -7702,6 +14621,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_or_i64_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_or_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_or_i64_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoor.d.rl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw or i64* %a, i64 %b release
   ret i64 %1
 }
@@ -7726,6 +14660,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_or_i64_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_or_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_or_i64_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoor.d.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw or i64* %a, i64 %b acq_rel
   ret i64 %1
 }
@@ -7750,6 +14699,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_or_i64_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_or_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_or_i64_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoor.d.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw or i64* %a, i64 %b seq_cst
   ret i64 %1
 }
@@ -7774,6 +14738,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xor_i64_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    mv a2, zero
+; RV64I-NEXT:    call __atomic_fetch_xor_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xor_i64_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoxor.d a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i64* %a, i64 %b monotonic
   ret i64 %1
 }
@@ -7798,6 +14777,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xor_i64_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 2
+; RV64I-NEXT:    call __atomic_fetch_xor_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xor_i64_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoxor.d.aq a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i64* %a, i64 %b acquire
   ret i64 %1
 }
@@ -7822,6 +14816,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xor_i64_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 3
+; RV64I-NEXT:    call __atomic_fetch_xor_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xor_i64_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoxor.d.rl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i64* %a, i64 %b release
   ret i64 %1
 }
@@ -7846,6 +14855,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xor_i64_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 4
+; RV64I-NEXT:    call __atomic_fetch_xor_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xor_i64_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoxor.d.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i64* %a, i64 %b acq_rel
   ret i64 %1
 }
@@ -7870,6 +14894,21 @@
 ; RV32IA-NEXT:    lw ra, 12(sp)
 ; RV32IA-NEXT:    addi sp, sp, 16
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_xor_i64_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -16
+; RV64I-NEXT:    sd ra, 8(sp)
+; RV64I-NEXT:    addi a2, zero, 5
+; RV64I-NEXT:    call __atomic_fetch_xor_8
+; RV64I-NEXT:    ld ra, 8(sp)
+; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_xor_i64_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amoxor.d.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw xor i64* %a, i64 %b seq_cst
   ret i64 %1
 }
@@ -7990,6 +15029,47 @@
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_max_i64_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    mv s1, a1
+; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    ld a2, 0(a0)
+; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:  .LBB200_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sd a2, 8(sp)
+; RV64I-NEXT:    blt s1, a2, .LBB200_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB200_1 Depth=1
+; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:  .LBB200_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB200_1 Depth=1
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, zero
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_8
+; RV64I-NEXT:    ld a2, 8(sp)
+; RV64I-NEXT:    beqz a0, .LBB200_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_max_i64_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomax.d a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw max i64* %a, i64 %b monotonic
   ret i64 %1
 }
@@ -8116,6 +15196,50 @@
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_max_i64_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    mv s1, a1
+; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    ld a2, 0(a0)
+; RV64I-NEXT:    mv s3, sp
+; RV64I-NEXT:    addi s4, zero, 2
+; RV64I-NEXT:  .LBB201_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    blt s1, a2, .LBB201_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB201_1 Depth=1
+; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:  .LBB201_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB201_1 Depth=1
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s4
+; RV64I-NEXT:    call __atomic_compare_exchange_8
+; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    beqz a0, .LBB201_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_max_i64_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomax.d.aq a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw max i64* %a, i64 %b acquire
   ret i64 %1
 }
@@ -8242,6 +15366,50 @@
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_max_i64_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    mv s1, a1
+; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    ld a2, 0(a0)
+; RV64I-NEXT:    mv s3, sp
+; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:  .LBB202_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    blt s1, a2, .LBB202_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB202_1 Depth=1
+; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:  .LBB202_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB202_1 Depth=1
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_8
+; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    beqz a0, .LBB202_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_max_i64_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomax.d.rl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw max i64* %a, i64 %b release
   ret i64 %1
 }
@@ -8374,6 +15542,53 @@
 ; RV32IA-NEXT:    lw ra, 44(sp)
 ; RV32IA-NEXT:    addi sp, sp, 48
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_max_i64_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s1, a1
+; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    ld a2, 0(a0)
+; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s4, zero, 4
+; RV64I-NEXT:    addi s5, zero, 2
+; RV64I-NEXT:  .LBB203_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sd a2, 8(sp)
+; RV64I-NEXT:    blt s1, a2, .LBB203_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB203_1 Depth=1
+; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:  .LBB203_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB203_1 Depth=1
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    call __atomic_compare_exchange_8
+; RV64I-NEXT:    ld a2, 8(sp)
+; RV64I-NEXT:    beqz a0, .LBB203_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_max_i64_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomax.d.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw max i64* %a, i64 %b acq_rel
   ret i64 %1
 }
@@ -8500,6 +15715,50 @@
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_max_i64_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    mv s1, a1
+; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    ld a2, 0(a0)
+; RV64I-NEXT:    mv s3, sp
+; RV64I-NEXT:    addi s4, zero, 5
+; RV64I-NEXT:  .LBB204_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    blt s1, a2, .LBB204_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB204_1 Depth=1
+; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:  .LBB204_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB204_1 Depth=1
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s4
+; RV64I-NEXT:    call __atomic_compare_exchange_8
+; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    beqz a0, .LBB204_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_max_i64_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomax.d.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw max i64* %a, i64 %b seq_cst
   ret i64 %1
 }
@@ -8622,6 +15881,47 @@
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_min_i64_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    mv s1, a1
+; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    ld a2, 0(a0)
+; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:  .LBB205_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sd a2, 8(sp)
+; RV64I-NEXT:    bge s1, a2, .LBB205_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB205_1 Depth=1
+; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:  .LBB205_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB205_1 Depth=1
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, zero
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_8
+; RV64I-NEXT:    ld a2, 8(sp)
+; RV64I-NEXT:    beqz a0, .LBB205_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_min_i64_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomin.d a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw min i64* %a, i64 %b monotonic
   ret i64 %1
 }
@@ -8750,6 +16050,50 @@
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_min_i64_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    mv s1, a1
+; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    ld a2, 0(a0)
+; RV64I-NEXT:    mv s3, sp
+; RV64I-NEXT:    addi s4, zero, 2
+; RV64I-NEXT:  .LBB206_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    bge s1, a2, .LBB206_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB206_1 Depth=1
+; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:  .LBB206_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB206_1 Depth=1
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s4
+; RV64I-NEXT:    call __atomic_compare_exchange_8
+; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    beqz a0, .LBB206_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_min_i64_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomin.d.aq a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw min i64* %a, i64 %b acquire
   ret i64 %1
 }
@@ -8878,6 +16222,50 @@
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_min_i64_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    mv s1, a1
+; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    ld a2, 0(a0)
+; RV64I-NEXT:    mv s3, sp
+; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:  .LBB207_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    bge s1, a2, .LBB207_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB207_1 Depth=1
+; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:  .LBB207_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB207_1 Depth=1
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_8
+; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    beqz a0, .LBB207_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_min_i64_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomin.d.rl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw min i64* %a, i64 %b release
   ret i64 %1
 }
@@ -9012,6 +16400,53 @@
 ; RV32IA-NEXT:    lw ra, 44(sp)
 ; RV32IA-NEXT:    addi sp, sp, 48
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_min_i64_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s1, a1
+; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    ld a2, 0(a0)
+; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s4, zero, 4
+; RV64I-NEXT:    addi s5, zero, 2
+; RV64I-NEXT:  .LBB208_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sd a2, 8(sp)
+; RV64I-NEXT:    bge s1, a2, .LBB208_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB208_1 Depth=1
+; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:  .LBB208_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB208_1 Depth=1
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    call __atomic_compare_exchange_8
+; RV64I-NEXT:    ld a2, 8(sp)
+; RV64I-NEXT:    beqz a0, .LBB208_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_min_i64_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomin.d.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw min i64* %a, i64 %b acq_rel
   ret i64 %1
 }
@@ -9140,6 +16575,50 @@
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_min_i64_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    mv s1, a1
+; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    ld a2, 0(a0)
+; RV64I-NEXT:    mv s3, sp
+; RV64I-NEXT:    addi s4, zero, 5
+; RV64I-NEXT:  .LBB209_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    bge s1, a2, .LBB209_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB209_1 Depth=1
+; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:  .LBB209_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB209_1 Depth=1
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s4
+; RV64I-NEXT:    call __atomic_compare_exchange_8
+; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    beqz a0, .LBB209_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_min_i64_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomin.d.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw min i64* %a, i64 %b seq_cst
   ret i64 %1
 }
@@ -9260,6 +16739,47 @@
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umax_i64_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    mv s1, a1
+; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    ld a2, 0(a0)
+; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:  .LBB210_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sd a2, 8(sp)
+; RV64I-NEXT:    bltu s1, a2, .LBB210_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB210_1 Depth=1
+; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:  .LBB210_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB210_1 Depth=1
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, zero
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_8
+; RV64I-NEXT:    ld a2, 8(sp)
+; RV64I-NEXT:    beqz a0, .LBB210_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umax_i64_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomaxu.d a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i64* %a, i64 %b monotonic
   ret i64 %1
 }
@@ -9386,6 +16906,50 @@
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umax_i64_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    mv s1, a1
+; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    ld a2, 0(a0)
+; RV64I-NEXT:    mv s3, sp
+; RV64I-NEXT:    addi s4, zero, 2
+; RV64I-NEXT:  .LBB211_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    bltu s1, a2, .LBB211_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB211_1 Depth=1
+; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:  .LBB211_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB211_1 Depth=1
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s4
+; RV64I-NEXT:    call __atomic_compare_exchange_8
+; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    beqz a0, .LBB211_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umax_i64_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomaxu.d.aq a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i64* %a, i64 %b acquire
   ret i64 %1
 }
@@ -9512,6 +17076,50 @@
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umax_i64_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    mv s1, a1
+; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    ld a2, 0(a0)
+; RV64I-NEXT:    mv s3, sp
+; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:  .LBB212_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    bltu s1, a2, .LBB212_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB212_1 Depth=1
+; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:  .LBB212_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB212_1 Depth=1
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_8
+; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    beqz a0, .LBB212_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umax_i64_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomaxu.d.rl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i64* %a, i64 %b release
   ret i64 %1
 }
@@ -9644,6 +17252,53 @@
 ; RV32IA-NEXT:    lw ra, 44(sp)
 ; RV32IA-NEXT:    addi sp, sp, 48
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umax_i64_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s1, a1
+; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    ld a2, 0(a0)
+; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s4, zero, 4
+; RV64I-NEXT:    addi s5, zero, 2
+; RV64I-NEXT:  .LBB213_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sd a2, 8(sp)
+; RV64I-NEXT:    bltu s1, a2, .LBB213_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB213_1 Depth=1
+; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:  .LBB213_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB213_1 Depth=1
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    call __atomic_compare_exchange_8
+; RV64I-NEXT:    ld a2, 8(sp)
+; RV64I-NEXT:    beqz a0, .LBB213_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umax_i64_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomaxu.d.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i64* %a, i64 %b acq_rel
   ret i64 %1
 }
@@ -9770,6 +17425,50 @@
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umax_i64_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    mv s1, a1
+; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    ld a2, 0(a0)
+; RV64I-NEXT:    mv s3, sp
+; RV64I-NEXT:    addi s4, zero, 5
+; RV64I-NEXT:  .LBB214_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    bltu s1, a2, .LBB214_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB214_1 Depth=1
+; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:  .LBB214_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB214_1 Depth=1
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s4
+; RV64I-NEXT:    call __atomic_compare_exchange_8
+; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    beqz a0, .LBB214_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umax_i64_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amomaxu.d.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i64* %a, i64 %b seq_cst
   ret i64 %1
 }
@@ -9892,6 +17591,47 @@
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umin_i64_monotonic:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    mv s1, a1
+; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    ld a2, 0(a0)
+; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:  .LBB215_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sd a2, 8(sp)
+; RV64I-NEXT:    bgeu s1, a2, .LBB215_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB215_1 Depth=1
+; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:  .LBB215_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB215_1 Depth=1
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, zero
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_8
+; RV64I-NEXT:    ld a2, 8(sp)
+; RV64I-NEXT:    beqz a0, .LBB215_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umin_i64_monotonic:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amominu.d a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i64* %a, i64 %b monotonic
   ret i64 %1
 }
@@ -10020,6 +17760,50 @@
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umin_i64_acquire:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    mv s1, a1
+; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    ld a2, 0(a0)
+; RV64I-NEXT:    mv s3, sp
+; RV64I-NEXT:    addi s4, zero, 2
+; RV64I-NEXT:  .LBB216_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    bgeu s1, a2, .LBB216_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB216_1 Depth=1
+; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:  .LBB216_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB216_1 Depth=1
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s4
+; RV64I-NEXT:    call __atomic_compare_exchange_8
+; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    beqz a0, .LBB216_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umin_i64_acquire:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amominu.d.aq a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i64* %a, i64 %b acquire
   ret i64 %1
 }
@@ -10148,6 +17932,50 @@
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umin_i64_release:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    mv s1, a1
+; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    ld a2, 0(a0)
+; RV64I-NEXT:    mv s3, sp
+; RV64I-NEXT:    addi s4, zero, 3
+; RV64I-NEXT:  .LBB217_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    bgeu s1, a2, .LBB217_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB217_1 Depth=1
+; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:  .LBB217_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB217_1 Depth=1
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, zero
+; RV64I-NEXT:    call __atomic_compare_exchange_8
+; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    beqz a0, .LBB217_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umin_i64_release:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amominu.d.rl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i64* %a, i64 %b release
   ret i64 %1
 }
@@ -10282,6 +18110,53 @@
 ; RV32IA-NEXT:    lw ra, 44(sp)
 ; RV32IA-NEXT:    addi sp, sp, 48
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umin_i64_acq_rel:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -64
+; RV64I-NEXT:    sd ra, 56(sp)
+; RV64I-NEXT:    sd s1, 48(sp)
+; RV64I-NEXT:    sd s2, 40(sp)
+; RV64I-NEXT:    sd s3, 32(sp)
+; RV64I-NEXT:    sd s4, 24(sp)
+; RV64I-NEXT:    sd s5, 16(sp)
+; RV64I-NEXT:    mv s1, a1
+; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    ld a2, 0(a0)
+; RV64I-NEXT:    addi s3, sp, 8
+; RV64I-NEXT:    addi s4, zero, 4
+; RV64I-NEXT:    addi s5, zero, 2
+; RV64I-NEXT:  .LBB218_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sd a2, 8(sp)
+; RV64I-NEXT:    bgeu s1, a2, .LBB218_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB218_1 Depth=1
+; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:  .LBB218_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB218_1 Depth=1
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s5
+; RV64I-NEXT:    call __atomic_compare_exchange_8
+; RV64I-NEXT:    ld a2, 8(sp)
+; RV64I-NEXT:    beqz a0, .LBB218_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    ld s5, 16(sp)
+; RV64I-NEXT:    ld s4, 24(sp)
+; RV64I-NEXT:    ld s3, 32(sp)
+; RV64I-NEXT:    ld s2, 40(sp)
+; RV64I-NEXT:    ld s1, 48(sp)
+; RV64I-NEXT:    ld ra, 56(sp)
+; RV64I-NEXT:    addi sp, sp, 64
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umin_i64_acq_rel:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amominu.d.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i64* %a, i64 %b acq_rel
   ret i64 %1
 }
@@ -10410,6 +18285,50 @@
 ; RV32IA-NEXT:    lw ra, 28(sp)
 ; RV32IA-NEXT:    addi sp, sp, 32
 ; RV32IA-NEXT:    ret
+;
+; RV64I-LABEL: atomicrmw_umin_i64_seq_cst:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -48
+; RV64I-NEXT:    sd ra, 40(sp)
+; RV64I-NEXT:    sd s1, 32(sp)
+; RV64I-NEXT:    sd s2, 24(sp)
+; RV64I-NEXT:    sd s3, 16(sp)
+; RV64I-NEXT:    sd s4, 8(sp)
+; RV64I-NEXT:    mv s1, a1
+; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    ld a2, 0(a0)
+; RV64I-NEXT:    mv s3, sp
+; RV64I-NEXT:    addi s4, zero, 5
+; RV64I-NEXT:  .LBB219_1: # %atomicrmw.start
+; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT:    sd a2, 0(sp)
+; RV64I-NEXT:    bgeu s1, a2, .LBB219_3
+; RV64I-NEXT:  # %bb.2: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB219_1 Depth=1
+; RV64I-NEXT:    mv a2, s1
+; RV64I-NEXT:  .LBB219_3: # %atomicrmw.start
+; RV64I-NEXT:    # in Loop: Header=BB219_1 Depth=1
+; RV64I-NEXT:    mv a0, s2
+; RV64I-NEXT:    mv a1, s3
+; RV64I-NEXT:    mv a3, s4
+; RV64I-NEXT:    mv a4, s4
+; RV64I-NEXT:    call __atomic_compare_exchange_8
+; RV64I-NEXT:    ld a2, 0(sp)
+; RV64I-NEXT:    beqz a0, .LBB219_1
+; RV64I-NEXT:  # %bb.4: # %atomicrmw.end
+; RV64I-NEXT:    mv a0, a2
+; RV64I-NEXT:    ld s4, 8(sp)
+; RV64I-NEXT:    ld s3, 16(sp)
+; RV64I-NEXT:    ld s2, 24(sp)
+; RV64I-NEXT:    ld s1, 32(sp)
+; RV64I-NEXT:    ld ra, 40(sp)
+; RV64I-NEXT:    addi sp, sp, 48
+; RV64I-NEXT:    ret
+;
+; RV64IA-LABEL: atomicrmw_umin_i64_seq_cst:
+; RV64IA:       # %bb.0:
+; RV64IA-NEXT:    amominu.d.aqrl a0, a1, (a0)
+; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i64* %a, i64 %b seq_cst
   ret i64 %1
 }