Index: include/llvm/CodeGen/BasicTTIImpl.h =================================================================== --- include/llvm/CodeGen/BasicTTIImpl.h +++ include/llvm/CodeGen/BasicTTIImpl.h @@ -1072,12 +1072,12 @@ case Intrinsic::minnum: ISDs.push_back(ISD::FMINNUM); if (FMF.noNaNs()) - ISDs.push_back(ISD::FMINNAN); + ISDs.push_back(ISD::FMINIMUM); break; case Intrinsic::maxnum: ISDs.push_back(ISD::FMAXNUM); if (FMF.noNaNs()) - ISDs.push_back(ISD::FMAXNAN); + ISDs.push_back(ISD::FMAXIMUM); break; case Intrinsic::copysign: ISDs.push_back(ISD::FCOPYSIGN); Index: include/llvm/CodeGen/ISDOpcodes.h =================================================================== --- include/llvm/CodeGen/ISDOpcodes.h +++ include/llvm/CodeGen/ISDOpcodes.h @@ -568,10 +568,10 @@ /// /// The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0. FMINNUM, FMAXNUM, - /// FMINNAN/FMAXNAN - NaN-propagating minimum/maximum that also treat -0.0 + /// FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 /// as less than 0.0. While FMINNUM/FMAXNUM follow IEEE 754-2008 semantics, - /// FMINNAN/FMAXNAN follow IEEE 754-2018 draft semantics. - FMINNAN, FMAXNAN, + /// FMINIMUM/FMAXIMUM follow IEEE 754-2018 draft semantics. + FMINIMUM, FMAXIMUM, /// FSINCOS - Compute both fsin and fcos as a single operation. FSINCOS, Index: include/llvm/CodeGen/TargetLowering.h =================================================================== --- include/llvm/CodeGen/TargetLowering.h +++ include/llvm/CodeGen/TargetLowering.h @@ -2091,8 +2091,8 @@ case ISD::ADDE: case ISD::FMINNUM: case ISD::FMAXNUM: - case ISD::FMINNAN: - case ISD::FMAXNAN: + case ISD::FMINIMUM: + case ISD::FMAXIMUM: return true; default: return false; } Index: include/llvm/Target/TargetSelectionDAG.td =================================================================== --- include/llvm/Target/TargetSelectionDAG.td +++ include/llvm/Target/TargetSelectionDAG.td @@ -408,8 +408,8 @@ [SDNPCommutative, SDNPAssociative]>; def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp, [SDNPCommutative, SDNPAssociative]>; -def fminnan : SDNode<"ISD::FMINNAN" , SDTFPBinOp>; -def fmaxnan : SDNode<"ISD::FMAXNAN" , SDTFPBinOp>; +def fminimum : SDNode<"ISD::FMINIMUM" , SDTFPBinOp>; +def fmaximum : SDNode<"ISD::FMAXIMUM" , SDTFPBinOp>; def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>; def fcanonicalize : SDNode<"ISD::FCANONICALIZE", SDTFPUnaryOp>; def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp =================================================================== --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -371,8 +371,8 @@ SDValue visitFFLOOR(SDNode *N); SDValue visitFMINNUM(SDNode *N); SDValue visitFMAXNUM(SDNode *N); - SDValue visitFMINNAN(SDNode *N); - SDValue visitFMAXNAN(SDNode *N); + SDValue visitFMINIMUM(SDNode *N); + SDValue visitFMAXIMUM(SDNode *N); SDValue visitBRCOND(SDNode *N); SDValue visitBR_CC(SDNode *N); SDValue visitLOAD(SDNode *N); @@ -1584,8 +1584,8 @@ case ISD::FFLOOR: return visitFFLOOR(N); case ISD::FMINNUM: return visitFMINNUM(N); case ISD::FMAXNUM: return visitFMAXNUM(N); - case ISD::FMINNAN: return visitFMINNAN(N); - case ISD::FMAXNAN: return visitFMAXNAN(N); + case ISD::FMINIMUM: return visitFMINIMUM(N); + case ISD::FMAXIMUM: return visitFMAXIMUM(N); case ISD::FCEIL: return visitFCEIL(N); case ISD::FTRUNC: return visitFTRUNC(N); case ISD::BRCOND: return visitBRCOND(N); @@ -12147,11 +12147,11 @@ return visitFMinMax(DAG, N, maxnum); } -SDValue DAGCombiner::visitFMINNAN(SDNode *N) { +SDValue DAGCombiner::visitFMINIMUM(SDNode *N) { return visitFMinMax(DAG, N, minimum); } -SDValue DAGCombiner::visitFMAXNAN(SDNode *N) { +SDValue DAGCombiner::visitFMAXIMUM(SDNode *N) { return visitFMinMax(DAG, N, maximum); } Index: lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp =================================================================== --- lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -1910,8 +1910,8 @@ // Binary FP Operations case ISD::FADD: case ISD::FDIV: - case ISD::FMAXNAN: - case ISD::FMINNAN: + case ISD::FMAXIMUM: + case ISD::FMINIMUM: case ISD::FMAXNUM: case ISD::FMINNUM: case ISD::FMUL: Index: lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp =================================================================== --- lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -353,8 +353,8 @@ case ISD::FABS: case ISD::FMINNUM: case ISD::FMAXNUM: - case ISD::FMINNAN: - case ISD::FMAXNAN: + case ISD::FMINIMUM: + case ISD::FMAXIMUM: case ISD::FCOPYSIGN: case ISD::FSQRT: case ISD::FSIN: Index: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp =================================================================== --- lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -113,8 +113,8 @@ case ISD::FMUL: case ISD::FMINNUM: case ISD::FMAXNUM: - case ISD::FMINNAN: - case ISD::FMAXNAN: + case ISD::FMINIMUM: + case ISD::FMAXIMUM: case ISD::SMIN: case ISD::SMAX: case ISD::UMIN: @@ -783,8 +783,8 @@ case ISD::FMUL: case ISD::FMINNUM: case ISD::FMAXNUM: - case ISD::FMINNAN: - case ISD::FMAXNAN: + case ISD::FMINIMUM: + case ISD::FMAXIMUM: case ISD::SDIV: case ISD::UDIV: case ISD::FDIV: @@ -1800,10 +1800,10 @@ case ISD::VECREDUCE_UMAX: CombineOpc = ISD::UMAX; break; case ISD::VECREDUCE_UMIN: CombineOpc = ISD::UMIN; break; case ISD::VECREDUCE_FMAX: - CombineOpc = NoNaN ? ISD::FMAXNUM : ISD::FMAXNAN; + CombineOpc = NoNaN ? ISD::FMAXNUM : ISD::FMAXIMUM; break; case ISD::VECREDUCE_FMIN: - CombineOpc = NoNaN ? ISD::FMINNUM : ISD::FMINNAN; + CombineOpc = NoNaN ? ISD::FMINNUM : ISD::FMINIMUM; break; default: llvm_unreachable("Unexpected reduce ISD node"); @@ -2352,8 +2352,8 @@ case ISD::XOR: case ISD::FMINNUM: case ISD::FMAXNUM: - case ISD::FMINNAN: - case ISD::FMAXNAN: + case ISD::FMINIMUM: + case ISD::FMAXIMUM: case ISD::SMIN: case ISD::SMAX: case ISD::UMIN: Index: lib/CodeGen/SelectionDAG/SelectionDAG.cpp =================================================================== --- lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -3713,8 +3713,8 @@ return false; } - // TODO: Handle FMINNUM/FMAXNUM/FMINNAN/FMAXNAN when there is an agreement on - // what they should do. + // TODO: Handle FMINNUM/FMAXNUM/FMINIMUM/FMAXIMUM when there is an agreement + // on what they should do. case ISD::EXTRACT_VECTOR_ELT: { return isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1); } Index: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp =================================================================== --- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -2972,16 +2972,16 @@ case SPF_FMINNUM: switch (SPR.NaNBehavior) { case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?"); - case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break; + case SPNB_RETURNS_NAN: Opc = ISD::FMINIMUM; break; case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break; case SPNB_RETURNS_ANY: { if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT)) Opc = ISD::FMINNUM; - else if (TLI.isOperationLegalOrCustom(ISD::FMINNAN, VT)) - Opc = ISD::FMINNAN; + else if (TLI.isOperationLegalOrCustom(ISD::FMINIMUM, VT)) + Opc = ISD::FMINIMUM; else if (UseScalarMinMax) Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ? - ISD::FMINNUM : ISD::FMINNAN; + ISD::FMINNUM : ISD::FMINIMUM; break; } } @@ -2989,17 +2989,17 @@ case SPF_FMAXNUM: switch (SPR.NaNBehavior) { case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?"); - case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break; + case SPNB_RETURNS_NAN: Opc = ISD::FMAXIMUM; break; case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break; case SPNB_RETURNS_ANY: if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT)) Opc = ISD::FMAXNUM; - else if (TLI.isOperationLegalOrCustom(ISD::FMAXNAN, VT)) - Opc = ISD::FMAXNAN; + else if (TLI.isOperationLegalOrCustom(ISD::FMAXIMUM, VT)) + Opc = ISD::FMAXIMUM; else if (UseScalarMinMax) Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()) ? - ISD::FMAXNUM : ISD::FMAXNAN; + ISD::FMAXNUM : ISD::FMAXIMUM; break; } break; @@ -5565,8 +5565,8 @@ case Intrinsic::minnum: { auto VT = getValue(I.getArgOperand(0)).getValueType(); unsigned Opc = - I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMINNAN, VT) - ? ISD::FMINNAN + I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMINIMUM, VT) + ? ISD::FMINIMUM : ISD::FMINNUM; setValue(&I, DAG.getNode(Opc, sdl, VT, getValue(I.getArgOperand(0)), @@ -5576,8 +5576,8 @@ case Intrinsic::maxnum: { auto VT = getValue(I.getArgOperand(0)).getValueType(); unsigned Opc = - I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMAXNAN, VT) - ? ISD::FMAXNAN + I.hasNoNaNs() && TLI.isOperationLegalOrCustom(ISD::FMAXIMUM, VT) + ? ISD::FMAXIMUM : ISD::FMAXNUM; setValue(&I, DAG.getNode(Opc, sdl, VT, getValue(I.getArgOperand(0)), @@ -5585,13 +5585,13 @@ return nullptr; } case Intrinsic::minimum: - setValue(&I, DAG.getNode(ISD::FMINNAN, sdl, + setValue(&I, DAG.getNode(ISD::FMINIMUM, sdl, getValue(I.getArgOperand(0)).getValueType(), getValue(I.getArgOperand(0)), getValue(I.getArgOperand(1)))); return nullptr; case Intrinsic::maximum: - setValue(&I, DAG.getNode(ISD::FMAXNAN, sdl, + setValue(&I, DAG.getNode(ISD::FMAXIMUM, sdl, getValue(I.getArgOperand(0)).getValueType(), getValue(I.getArgOperand(0)), getValue(I.getArgOperand(1)))); Index: lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp =================================================================== --- lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp +++ lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp @@ -176,8 +176,8 @@ case ISD::FABS: return "fabs"; case ISD::FMINNUM: return "fminnum"; case ISD::FMAXNUM: return "fmaxnum"; - case ISD::FMINNAN: return "fminnan"; - case ISD::FMAXNAN: return "fmaxnan"; + case ISD::FMINIMUM: return "fminimum"; + case ISD::FMAXIMUM: return "fmaximum"; case ISD::FNEG: return "fneg"; case ISD::FSQRT: return "fsqrt"; case ISD::STRICT_FSQRT: return "strict_fsqrt"; Index: lib/CodeGen/TargetLoweringBase.cpp =================================================================== --- lib/CodeGen/TargetLoweringBase.cpp +++ lib/CodeGen/TargetLoweringBase.cpp @@ -600,8 +600,8 @@ setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); setOperationAction(ISD::FMINNUM, VT, Expand); setOperationAction(ISD::FMAXNUM, VT, Expand); - setOperationAction(ISD::FMINNAN, VT, Expand); - setOperationAction(ISD::FMAXNAN, VT, Expand); + setOperationAction(ISD::FMINIMUM, VT, Expand); + setOperationAction(ISD::FMAXIMUM, VT, Expand); setOperationAction(ISD::FMAD, VT, Expand); setOperationAction(ISD::SMIN, VT, Expand); setOperationAction(ISD::SMAX, VT, Expand); Index: lib/Target/AArch64/AArch64ISelLowering.cpp =================================================================== --- lib/Target/AArch64/AArch64ISelLowering.cpp +++ lib/Target/AArch64/AArch64ISelLowering.cpp @@ -385,8 +385,8 @@ setOperationAction(ISD::FTRUNC, MVT::f16, Promote); setOperationAction(ISD::FMINNUM, MVT::f16, Promote); setOperationAction(ISD::FMAXNUM, MVT::f16, Promote); - setOperationAction(ISD::FMINNAN, MVT::f16, Promote); - setOperationAction(ISD::FMAXNAN, MVT::f16, Promote); + setOperationAction(ISD::FMINIMUM, MVT::f16, Promote); + setOperationAction(ISD::FMAXIMUM, MVT::f16, Promote); // promote v4f16 to v4f32 when that is known to be safe. setOperationAction(ISD::FADD, MVT::v4f16, Promote); @@ -450,8 +450,8 @@ setOperationAction(ISD::FROUND, Ty, Legal); setOperationAction(ISD::FMINNUM, Ty, Legal); setOperationAction(ISD::FMAXNUM, Ty, Legal); - setOperationAction(ISD::FMINNAN, Ty, Legal); - setOperationAction(ISD::FMAXNAN, Ty, Legal); + setOperationAction(ISD::FMINIMUM, Ty, Legal); + setOperationAction(ISD::FMAXIMUM, Ty, Legal); } if (Subtarget->hasFullFP16()) { @@ -463,8 +463,8 @@ setOperationAction(ISD::FROUND, MVT::f16, Legal); setOperationAction(ISD::FMINNUM, MVT::f16, Legal); setOperationAction(ISD::FMAXNUM, MVT::f16, Legal); - setOperationAction(ISD::FMINNAN, MVT::f16, Legal); - setOperationAction(ISD::FMAXNAN, MVT::f16, Legal); + setOperationAction(ISD::FMINIMUM, MVT::f16, Legal); + setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal); } setOperationAction(ISD::PREFETCH, MVT::Other, Custom); @@ -816,8 +816,8 @@ // F[MIN|MAX][NUM|NAN] are available for all FP NEON types. if (VT.isFloatingPoint() && (VT.getVectorElementType() != MVT::f16 || Subtarget->hasFullFP16())) - for (unsigned Opcode : {ISD::FMINNAN, ISD::FMAXNAN, - ISD::FMINNUM, ISD::FMAXNUM}) + for (unsigned Opcode : + {ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FMINNUM, ISD::FMAXNUM}) setOperationAction(Opcode, VT, Legal); if (Subtarget->isLittleEndian()) { @@ -9849,10 +9849,10 @@ case Intrinsic::aarch64_neon_umaxv: return combineAcrossLanesIntrinsic(AArch64ISD::UMAXV, N, DAG); case Intrinsic::aarch64_neon_fmax: - return DAG.getNode(ISD::FMAXNAN, SDLoc(N), N->getValueType(0), + return DAG.getNode(ISD::FMAXIMUM, SDLoc(N), N->getValueType(0), N->getOperand(1), N->getOperand(2)); case Intrinsic::aarch64_neon_fmin: - return DAG.getNode(ISD::FMINNAN, SDLoc(N), N->getValueType(0), + return DAG.getNode(ISD::FMINIMUM, SDLoc(N), N->getValueType(0), N->getOperand(1), N->getOperand(2)); case Intrinsic::aarch64_neon_fmaxnm: return DAG.getNode(ISD::FMAXNUM, SDLoc(N), N->getValueType(0), Index: lib/Target/AArch64/AArch64InstrInfo.td =================================================================== --- lib/Target/AArch64/AArch64InstrInfo.td +++ lib/Target/AArch64/AArch64InstrInfo.td @@ -3026,18 +3026,18 @@ defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>; } defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", fmaxnum>; -defm FMAX : TwoOperandFPData<0b0100, "fmax", fmaxnan>; +defm FMAX : TwoOperandFPData<0b0100, "fmax", fmaximum>; defm FMINNM : TwoOperandFPData<0b0111, "fminnm", fminnum>; -defm FMIN : TwoOperandFPData<0b0101, "fmin", fminnan>; +defm FMIN : TwoOperandFPData<0b0101, "fmin", fminimum>; let SchedRW = [WriteFMul] in { defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>; defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>; } defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>; -def : Pat<(v1f64 (fmaxnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), +def : Pat<(v1f64 (fmaximum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), (FMAXDrr FPR64:$Rn, FPR64:$Rm)>; -def : Pat<(v1f64 (fminnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), +def : Pat<(v1f64 (fminimum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), (FMINDrr FPR64:$Rn, FPR64:$Rm)>; def : Pat<(v1f64 (fmaxnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))), (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>; @@ -3363,11 +3363,11 @@ defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b000,"fmaxnmp", int_aarch64_neon_fmaxnmp>; defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b000,"fmaxnm", fmaxnum>; defm FMAXP : SIMDThreeSameVectorFP<1,0,0b110,"fmaxp", int_aarch64_neon_fmaxp>; -defm FMAX : SIMDThreeSameVectorFP<0,0,0b110,"fmax", fmaxnan>; +defm FMAX : SIMDThreeSameVectorFP<0,0,0b110,"fmax", fmaximum>; defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b000,"fminnmp", int_aarch64_neon_fminnmp>; defm FMINNM : SIMDThreeSameVectorFP<0,1,0b000,"fminnm", fminnum>; defm FMINP : SIMDThreeSameVectorFP<1,1,0b110,"fminp", int_aarch64_neon_fminp>; -defm FMIN : SIMDThreeSameVectorFP<0,1,0b110,"fmin", fminnan>; +defm FMIN : SIMDThreeSameVectorFP<0,1,0b110,"fmin", fminimum>; // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the // instruction expects the addend first, while the fma intrinsic puts it last. Index: lib/Target/ARM/ARMISelLowering.cpp =================================================================== --- lib/Target/ARM/ARMISelLowering.cpp +++ lib/Target/ARM/ARMISelLowering.cpp @@ -1142,14 +1142,14 @@ if (Subtarget->hasNEON()) { // vmin and vmax aren't available in a scalar form, so we use // a NEON instruction with an undef lane instead. - setOperationAction(ISD::FMINNAN, MVT::f16, Legal); - setOperationAction(ISD::FMAXNAN, MVT::f16, Legal); - setOperationAction(ISD::FMINNAN, MVT::f32, Legal); - setOperationAction(ISD::FMAXNAN, MVT::f32, Legal); - setOperationAction(ISD::FMINNAN, MVT::v2f32, Legal); - setOperationAction(ISD::FMAXNAN, MVT::v2f32, Legal); - setOperationAction(ISD::FMINNAN, MVT::v4f32, Legal); - setOperationAction(ISD::FMAXNAN, MVT::v4f32, Legal); + setOperationAction(ISD::FMINIMUM, MVT::f16, Legal); + setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal); + setOperationAction(ISD::FMINIMUM, MVT::f32, Legal); + setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal); + setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal); + setOperationAction(ISD::FMAXIMUM, MVT::v2f32, Legal); + setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal); + setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal); if (Subtarget->hasFullFP16()) { setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal); @@ -1157,10 +1157,10 @@ setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal); setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal); - setOperationAction(ISD::FMINNAN, MVT::v4f16, Legal); - setOperationAction(ISD::FMAXNAN, MVT::v4f16, Legal); - setOperationAction(ISD::FMINNAN, MVT::v8f16, Legal); - setOperationAction(ISD::FMAXNAN, MVT::v8f16, Legal); + setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal); + setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal); + setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal); + setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal); } } @@ -3405,7 +3405,7 @@ Op.getOperand(1), Op.getOperand(2)); } unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins) - ? ISD::FMINNAN : ISD::FMAXNAN; + ? ISD::FMINIMUM : ISD::FMAXIMUM; return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(), Op.getOperand(1), Op.getOperand(2)); } Index: lib/Target/ARM/ARMInstrNEON.td =================================================================== --- lib/Target/ARM/ARMInstrNEON.td +++ lib/Target/ARM/ARMInstrNEON.td @@ -4523,9 +4523,9 @@ (SubReg_i16_lane imm:$lane)))>; def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1), - (v4i32 (int_arm_neon_vqrdmulh + (v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src2), - (v4i32 (NEONvduplane (v4i32 QPR:$src3), + (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane)))))), (v4i32 (VQRDMLAHslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2), @@ -4576,17 +4576,17 @@ (v2i32 DPR:$Vn), (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm), imm:$lane)))))), - (v2i32 (VQRDMLSHslv2i32 DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, + (v2i32 (VQRDMLSHslv2i32 DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane))>; def : Pat<(v8i16 (int_arm_neon_vqsubs (v8i16 QPR:$src1), (v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src2), - (v8i16 (NEONvduplane (v8i16 QPR:$src3), + (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane)))))), (v8i16 (VQRDMLSHslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2), - (v4i16 (EXTRACT_SUBREG + (v4i16 (EXTRACT_SUBREG QPR:$src3, (DSubReg_i16_reg imm:$lane))), (SubReg_i16_lane imm:$lane)))>; @@ -4598,7 +4598,7 @@ imm:$lane)))))), (v4i32 (VQRDMLSHslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2), - (v2i32 (EXTRACT_SUBREG + (v2i32 (EXTRACT_SUBREG QPR:$src3, (DSubReg_i32_reg imm:$lane))), (SubReg_i32_lane imm:$lane)))>; @@ -5521,17 +5521,17 @@ "vmax", "u", umax, 1>; def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND, "vmax", "f32", - v2f32, v2f32, fmaxnan, 1>; + v2f32, v2f32, fmaximum, 1>; def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ, "vmax", "f32", - v4f32, v4f32, fmaxnan, 1>; + v4f32, v4f32, fmaximum, 1>; def VMAXhd : N3VDInt<0, 0, 0b01, 0b1111, 0, N3RegFrm, IIC_VBIND, "vmax", "f16", - v4f16, v4f16, fmaxnan, 1>, + v4f16, v4f16, fmaximum, 1>, Requires<[HasNEON, HasFullFP16]>; def VMAXhq : N3VQInt<0, 0, 0b01, 0b1111, 0, N3RegFrm, IIC_VBINQ, "vmax", "f16", - v8f16, v8f16, fmaxnan, 1>, + v8f16, v8f16, fmaximum, 1>, Requires<[HasNEON, HasFullFP16]>; // VMAXNM @@ -5563,17 +5563,17 @@ "vmin", "u", umin, 1>; def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND, "vmin", "f32", - v2f32, v2f32, fminnan, 1>; + v2f32, v2f32, fminimum, 1>; def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ, "vmin", "f32", - v4f32, v4f32, fminnan, 1>; + v4f32, v4f32, fminimum, 1>; def VMINhd : N3VDInt<0, 0, 0b11, 0b1111, 0, N3RegFrm, IIC_VBIND, "vmin", "f16", - v4f16, v4f16, fminnan, 1>, + v4f16, v4f16, fminimum, 1>, Requires<[HasNEON, HasFullFP16]>; def VMINhq : N3VQInt<0, 0, 0b11, 0b1111, 0, N3RegFrm, IIC_VBINQ, "vmin", "f16", - v8f16, v8f16, fminnan, 1>, + v8f16, v8f16, fminimum, 1>, Requires<[HasNEON, HasFullFP16]>; // VMINNM @@ -7093,10 +7093,10 @@ Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>; def : N2VSPat; def : N2VSPat; -def : N3VSPatFP16, Requires<[HasFullFP16]>; -def : N3VSPatFP16, Requires<[HasFullFP16]>; -def : N3VSPat, Requires<[HasNEON]>; -def : N3VSPat, Requires<[HasNEON]>; +def : N3VSPatFP16, Requires<[HasFullFP16]>; +def : N3VSPatFP16, Requires<[HasFullFP16]>; +def : N3VSPat, Requires<[HasNEON]>; +def : N3VSPat, Requires<[HasNEON]>; def : NVCVTFIPat; def : NVCVTFIPat; def : NVCVTIFPat; @@ -7544,7 +7544,7 @@ (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>; } -// The following patterns are basically a copy of the patterns above, +// The following patterns are basically a copy of the patterns above, // however with an additional VREV16d instruction to convert data // loaded by VLD1LN into proper vector format in big endian mode. let Predicates = [IsBE] in { Index: lib/Target/Mips/MipsSEISelLowering.cpp =================================================================== --- lib/Target/Mips/MipsSEISelLowering.cpp +++ lib/Target/Mips/MipsSEISelLowering.cpp @@ -158,8 +158,8 @@ setOperationAction(ISD::FTRUNC, MVT::f16, Promote); setOperationAction(ISD::FMINNUM, MVT::f16, Promote); setOperationAction(ISD::FMAXNUM, MVT::f16, Promote); - setOperationAction(ISD::FMINNAN, MVT::f16, Promote); - setOperationAction(ISD::FMAXNAN, MVT::f16, Promote); + setOperationAction(ISD::FMINIMUM, MVT::f16, Promote); + setOperationAction(ISD::FMAXIMUM, MVT::f16, Promote); setTargetDAGCombine(ISD::AND); setTargetDAGCombine(ISD::OR); Index: lib/Target/NVPTX/NVPTXISelLowering.cpp =================================================================== --- lib/Target/NVPTX/NVPTXISelLowering.cpp +++ lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -560,8 +560,8 @@ } setOperationAction(ISD::FMINNUM, MVT::f16, Promote); setOperationAction(ISD::FMAXNUM, MVT::f16, Promote); - setOperationAction(ISD::FMINNAN, MVT::f16, Promote); - setOperationAction(ISD::FMAXNAN, MVT::f16, Promote); + setOperationAction(ISD::FMINIMUM, MVT::f16, Promote); + setOperationAction(ISD::FMAXIMUM, MVT::f16, Promote); // No FEXP2, FLOG2. The PTX ex2 and log2 functions are always approximate. // No FPOW or FREM in PTX. Index: lib/Target/SystemZ/SystemZISelLowering.cpp =================================================================== --- lib/Target/SystemZ/SystemZISelLowering.cpp +++ lib/Target/SystemZ/SystemZISelLowering.cpp @@ -452,29 +452,29 @@ setOperationAction(ISD::FROUND, MVT::v4f32, Legal); setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); - setOperationAction(ISD::FMAXNAN, MVT::f64, Legal); + setOperationAction(ISD::FMAXIMUM, MVT::f64, Legal); setOperationAction(ISD::FMINNUM, MVT::f64, Legal); - setOperationAction(ISD::FMINNAN, MVT::f64, Legal); + setOperationAction(ISD::FMINIMUM, MVT::f64, Legal); setOperationAction(ISD::FMAXNUM, MVT::v2f64, Legal); - setOperationAction(ISD::FMAXNAN, MVT::v2f64, Legal); + setOperationAction(ISD::FMAXIMUM, MVT::v2f64, Legal); setOperationAction(ISD::FMINNUM, MVT::v2f64, Legal); - setOperationAction(ISD::FMINNAN, MVT::v2f64, Legal); + setOperationAction(ISD::FMINIMUM, MVT::v2f64, Legal); setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); - setOperationAction(ISD::FMAXNAN, MVT::f32, Legal); + setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal); setOperationAction(ISD::FMINNUM, MVT::f32, Legal); - setOperationAction(ISD::FMINNAN, MVT::f32, Legal); + setOperationAction(ISD::FMINIMUM, MVT::f32, Legal); setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal); - setOperationAction(ISD::FMAXNAN, MVT::v4f32, Legal); + setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal); setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal); - setOperationAction(ISD::FMINNAN, MVT::v4f32, Legal); + setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal); setOperationAction(ISD::FMAXNUM, MVT::f128, Legal); - setOperationAction(ISD::FMAXNAN, MVT::f128, Legal); + setOperationAction(ISD::FMAXIMUM, MVT::f128, Legal); setOperationAction(ISD::FMINNUM, MVT::f128, Legal); - setOperationAction(ISD::FMINNAN, MVT::f128, Legal); + setOperationAction(ISD::FMINIMUM, MVT::f128, Legal); } // We have fused multiply-addition for f32 and f64 but not f128. Index: lib/Target/SystemZ/SystemZInstrVector.td =================================================================== --- lib/Target/SystemZ/SystemZInstrVector.td +++ lib/Target/SystemZ/SystemZInstrVector.td @@ -1031,7 +1031,7 @@ // Maximum. multiclass VectorMax { def : FPMinMax; - def : FPMinMax; + def : FPMinMax; } let Predicates = [FeatureVectorEnhancements1] in { def VFMAX : TernaryVRRcFloatGeneric<"vfmax", 0xE7EF>; @@ -1055,7 +1055,7 @@ // Minimum. multiclass VectorMin { def : FPMinMax; - def : FPMinMax; + def : FPMinMax; } let Predicates = [FeatureVectorEnhancements1] in { def VFMIN : TernaryVRRcFloatGeneric<"vfmin", 0xE7EE>; Index: lib/Target/WebAssembly/WebAssemblyISelLowering.cpp =================================================================== --- lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -103,9 +103,9 @@ for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) setOperationAction(Op, T, Legal); - // Support minnan and maxnan, which otherwise default to expand. - setOperationAction(ISD::FMINNAN, T, Legal); - setOperationAction(ISD::FMAXNAN, T, Legal); + // Support minimum and maximum, which otherwise default to expand. + setOperationAction(ISD::FMINIMUM, T, Legal); + setOperationAction(ISD::FMAXIMUM, T, Legal); // WebAssembly currently has no builtin f16 support. setOperationAction(ISD::FP16_TO_FP, T, Expand); setOperationAction(ISD::FP_TO_FP16, T, Expand); Index: lib/Target/WebAssembly/WebAssemblyInstrFloat.td =================================================================== --- lib/Target/WebAssembly/WebAssemblyInstrFloat.td +++ lib/Target/WebAssembly/WebAssemblyInstrFloat.td @@ -58,8 +58,8 @@ defm COPYSIGN : BinaryFP; let isCommutable = 1 in { -defm MIN : BinaryFP; -defm MAX : BinaryFP; +defm MIN : BinaryFP; +defm MAX : BinaryFP; } // isCommutable = 1 defm CEIL : UnaryFP; Index: lib/Target/WebAssembly/WebAssemblyInstrSIMD.td =================================================================== --- lib/Target/WebAssembly/WebAssemblyInstrSIMD.td +++ lib/Target/WebAssembly/WebAssemblyInstrSIMD.td @@ -743,10 +743,10 @@ } // NaN-propagating minimum: min -defm MIN : SIMDBinaryFP; +defm MIN : SIMDBinaryFP; // NaN-propagating maximum: max -defm MAX : SIMDBinaryFP; +defm MAX : SIMDBinaryFP; //===----------------------------------------------------------------------===// // Floating-point arithmetic Index: test/CodeGen/ARM/fp16-promote.ll =================================================================== --- test/CodeGen/ARM/fp16-promote.ll +++ test/CodeGen/ARM/fp16-promote.ll @@ -644,7 +644,7 @@ ret void } -; CHECK-ALL-LABEL: test_minnan: +; CHECK-ALL-LABEL: test_minimum: ; CHECK-FP16: vmov.f32 s0, #1.000000e+00 ; CHECK-FP16: vcvtb.f32.f16 ; CHECK-LIBCALL: bl __aeabi_h2f @@ -654,7 +654,7 @@ ; CHECK-NOVFP: bl __aeabi_fcmpge ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL: bl __aeabi_f2h -define void @test_minnan(half* %p) #0 { +define void @test_minimum(half* %p) #0 { %a = load half, half* %p, align 2 %c = fcmp ult half %a, 1.0 %r = select i1 %c, half %a, half 1.0 @@ -662,7 +662,7 @@ ret void } -; CHECK-ALL-LABEL: test_maxnan: +; CHECK-ALL-LABEL: test_maximum: ; CHECK-FP16: vmov.f32 s0, #1.000000e+00 ; CHECK-FP16: vcvtb.f32.f16 ; CHECK-LIBCALL: bl __aeabi_h2f @@ -672,7 +672,7 @@ ; CHECK-NOVFP: bl __aeabi_fcmple ; CHECK-FP16: vcvtb.f16.f32 ; CHECK-LIBCALL: bl __aeabi_f2h -define void @test_maxnan(half* %p) #0 { +define void @test_maximum(half* %p) #0 { %a = load half, half* %p, align 2 %c = fcmp ugt half %a, 1.0 %r = select i1 %c, half %a, half 1.0 Index: test/CodeGen/SystemZ/vec-max-05.ll =================================================================== --- test/CodeGen/SystemZ/vec-max-05.ll +++ test/CodeGen/SystemZ/vec-max-05.ll @@ -42,7 +42,7 @@ ret double %ret } -; Test a f64 constant compare/select resulting in maxnan. +; Test a f64 constant compare/select resulting in maximum. define double @f4(double %dummy, double %val) { ; CHECK-LABEL: f4: ; CHECK: lzdr [[REG:%f[0-9]+]] @@ -92,7 +92,7 @@ ret float %ret } -; Test a f32 constant compare/select resulting in maxnan. +; Test a f32 constant compare/select resulting in maximum. define float @f14(float %dummy, float %val) { ; CHECK-LABEL: f14: ; CHECK: lzer [[REG:%f[0-9]+]] @@ -158,7 +158,7 @@ ret void } -; Test a f128 constant compare/select resulting in maxnan. +; Test a f128 constant compare/select resulting in maximum. define void @f24(fp128 *%ptr, fp128 *%dst) { ; CHECK-LABEL: f24: ; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2) Index: test/CodeGen/SystemZ/vec-min-05.ll =================================================================== --- test/CodeGen/SystemZ/vec-min-05.ll +++ test/CodeGen/SystemZ/vec-min-05.ll @@ -42,7 +42,7 @@ ret double %ret } -; Test a f64 constant compare/select resulting in minnan. +; Test a f64 constant compare/select resulting in minimum. define double @f4(double %dummy, double %val) { ; CHECK-LABEL: f4: ; CHECK: lzdr [[REG:%f[0-9]+]] @@ -92,7 +92,7 @@ ret float %ret } -; Test a f32 constant compare/select resulting in minnan. +; Test a f32 constant compare/select resulting in minimum. define float @f14(float %dummy, float %val) { ; CHECK-LABEL: f14: ; CHECK: lzer [[REG:%f[0-9]+]] @@ -158,7 +158,7 @@ ret void } -; Test a f128 constant compare/select resulting in minnan. +; Test a f128 constant compare/select resulting in minimum. define void @f24(fp128 *%ptr, fp128 *%dst) { ; CHECK-LABEL: f24: ; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2) Index: test/CodeGen/WebAssembly/simd-arith.ll =================================================================== --- test/CodeGen/WebAssembly/simd-arith.ll +++ test/CodeGen/WebAssembly/simd-arith.ll @@ -801,7 +801,7 @@ ; SIMD128-NEXT: .result v128{{$}} ; SIMD128-NEXT: f32.const $push[[L0:[0-9]+]]=, 0x1.4p2 ; SIMD128-NEXT: f32x4.splat $push[[L1:[0-9]+]]=, $pop[[L0]] -; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $pop[[L1]], $0{{$}} +; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} ; SIMD128-NEXT: return $pop[[R]]{{$}} define <4 x float> @min_ordered_v4f32(<4 x float> %x) { %cmps = fcmp ole <4 x float> , %x @@ -816,7 +816,7 @@ ; SIMD128-NEXT: .result v128{{$}} ; SIMD128-NEXT: f32.const $push[[L0:[0-9]+]]=, 0x1.4p2 ; SIMD128-NEXT: f32x4.splat $push[[L1:[0-9]+]]=, $pop[[L0]] -; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $pop[[L1]], $0{{$}} +; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} ; SIMD128-NEXT: return $pop[[R]]{{$}} define <4 x float> @max_ordered_v4f32(<4 x float> %x) { %cmps = fcmp oge <4 x float> , %x @@ -968,7 +968,7 @@ ; SIMD128-NEXT: .result v128{{$}} ; SIMD128-NEXT: f64.const $push[[L0:[0-9]+]]=, 0x1.4p2 ; SIMD128-NEXT: f64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]] -; SIMD128-NEXT: f64x2.min $push[[R:[0-9]+]]=, $pop[[L1]], $0{{$}} +; SIMD128-NEXT: f64x2.min $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} ; SIMD128-NEXT: return $pop[[R]]{{$}} define <2 x double> @min_ordered_v2f64(<2 x double> %x) { %cmps = fcmp ole <2 x double> , %x @@ -983,7 +983,7 @@ ; SIMD128-NEXT: .result v128{{$}} ; SIMD128-NEXT: f64.const $push[[L0:[0-9]+]]=, 0x1.4p2 ; SIMD128-NEXT: f64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]] -; SIMD128-NEXT: f64x2.max $push[[R:[0-9]+]]=, $pop[[L1]], $0{{$}} +; SIMD128-NEXT: f64x2.max $push[[R:[0-9]+]]=, $0, $pop[[L1]]{{$}} ; SIMD128-NEXT: return $pop[[R]]{{$}} define <2 x double> @max_ordered_v2f64(<2 x double> %x) { %cmps = fcmp oge <2 x double> , %x Index: unittests/Analysis/ValueTrackingTest.cpp =================================================================== --- unittests/Analysis/ValueTrackingTest.cpp +++ unittests/Analysis/ValueTrackingTest.cpp @@ -149,7 +149,7 @@ expectPattern({SPF_FMINNUM, SPNB_RETURNS_OTHER, true}); } -TEST_F(MatchSelectPatternTest, VectorFMinNaN) { +TEST_F(MatchSelectPatternTest, VectorFMinimum) { parseAssembly( "define <4 x float> @test(<4 x float> %a) {\n" " %1 = fcmp ule <4 x float> %a, \n" @@ -177,7 +177,7 @@ expectPattern({SPF_FMINNUM, SPNB_RETURNS_OTHER, true}); } -TEST_F(MatchSelectPatternTest, VectorNotFMinNaN) { +TEST_F(MatchSelectPatternTest, VectorNotFMinimum) { parseAssembly( "define <4 x float> @test(<4 x float> %a) {\n" " %1 = fcmp ule <4 x float> %a, \n"