Index: llvm/trunk/tools/llvm-exegesis/lib/Latency.cpp =================================================================== --- llvm/trunk/tools/llvm-exegesis/lib/Latency.cpp +++ llvm/trunk/tools/llvm-exegesis/lib/Latency.cpp @@ -32,8 +32,7 @@ for (const unsigned OtherOpcode : Opcodes) { if (OtherOpcode == Instr.Description->Opcode) continue; - const auto &OtherInstrDesc = State.getInstrInfo().get(OtherOpcode); - const Instruction OtherInstr(OtherInstrDesc, RATC); + const Instruction OtherInstr(State, OtherOpcode); if (OtherInstr.hasMemoryOperands()) continue; const AliasingConfigurations Forward(Instr, OtherInstr); @@ -59,7 +58,7 @@ llvm::Expected LatencySnippetGenerator::generateCodeTemplate(unsigned Opcode) const { - const Instruction Instr(State.getInstrInfo().get(Opcode), RATC); + const Instruction Instr(State, Opcode); if (Instr.hasMemoryOperands()) return llvm::make_error( "Infeasible : has memory operands"); Index: llvm/trunk/tools/llvm-exegesis/lib/LlvmState.h =================================================================== --- llvm/trunk/tools/llvm-exegesis/lib/LlvmState.h +++ llvm/trunk/tools/llvm-exegesis/lib/LlvmState.h @@ -15,6 +15,7 @@ #ifndef LLVM_TOOLS_LLVM_EXEGESIS_LLVMSTATE_H #define LLVM_TOOLS_LLVM_EXEGESIS_LLVMSTATE_H +#include "RegisterAliasing.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrInfo.h" @@ -54,10 +55,12 @@ const llvm::MCSubtargetInfo &getSubtargetInfo() const { return *TargetMachine->getMCSubtargetInfo(); } + const RegisterAliasingTrackerCache &getRATC() const { return *RATC; } private: const ExegesisTarget *TheExegesisTarget; std::unique_ptr TargetMachine; + std::unique_ptr RATC; }; } // namespace exegesis Index: llvm/trunk/tools/llvm-exegesis/lib/LlvmState.cpp =================================================================== --- llvm/trunk/tools/llvm-exegesis/lib/LlvmState.cpp +++ llvm/trunk/tools/llvm-exegesis/lib/LlvmState.cpp @@ -35,6 +35,8 @@ llvm::errs() << "no exegesis target for " << Triple << ", using default\n"; TheExegesisTarget = &ExegesisTarget::getDefault(); } + RATC.reset(new RegisterAliasingTrackerCache( + getRegInfo(), getFunctionReservedRegs(getTargetMachine()))); } LLVMState::LLVMState() Index: llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.h =================================================================== --- llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.h +++ llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.h @@ -21,6 +21,7 @@ #include +#include "LlvmState.h" #include "RegisterAliasing.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/Optional.h" @@ -92,8 +93,7 @@ // A view over an MCInstrDesc offering a convenient interface to compute // Register aliasing. struct Instruction { - Instruction(const llvm::MCInstrDesc &MCInstrDesc, - const RegisterAliasingTrackerCache &ATC); + Instruction(const LLVMState &State, unsigned Opcode); // Returns the Operand linked to this Variable. // In case the Variable is tied, the primary (i.e. Def) Operand is returned. Index: llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.cpp =================================================================== --- llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.cpp +++ llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.cpp @@ -87,24 +87,24 @@ return *Info; } -Instruction::Instruction(const llvm::MCInstrDesc &MCInstrDesc, - const RegisterAliasingTrackerCache &RATC) - : Description(&MCInstrDesc) { +Instruction::Instruction(const LLVMState &State, unsigned Opcode) + : Description(&State.getInstrInfo().get(Opcode)) { + const auto &RATC = State.getRATC(); unsigned OpIndex = 0; - for (; OpIndex < MCInstrDesc.getNumOperands(); ++OpIndex) { - const auto &OpInfo = MCInstrDesc.opInfo_begin()[OpIndex]; + for (; OpIndex < Description->getNumOperands(); ++OpIndex) { + const auto &OpInfo = Description->opInfo_begin()[OpIndex]; Operand Operand; Operand.Index = OpIndex; - Operand.IsDef = (OpIndex < MCInstrDesc.getNumDefs()); + Operand.IsDef = (OpIndex < Description->getNumDefs()); // TODO(gchatelet): Handle isLookupPtrRegClass. if (OpInfo.RegClass >= 0) Operand.Tracker = &RATC.getRegisterClass(OpInfo.RegClass); Operand.TiedToIndex = - MCInstrDesc.getOperandConstraint(OpIndex, llvm::MCOI::TIED_TO); + Description->getOperandConstraint(OpIndex, llvm::MCOI::TIED_TO); Operand.Info = &OpInfo; Operands.push_back(Operand); } - for (const llvm::MCPhysReg *MCPhysReg = MCInstrDesc.getImplicitDefs(); + for (const llvm::MCPhysReg *MCPhysReg = Description->getImplicitDefs(); MCPhysReg && *MCPhysReg; ++MCPhysReg, ++OpIndex) { Operand Operand; Operand.Index = OpIndex; @@ -113,7 +113,7 @@ Operand.ImplicitReg = MCPhysReg; Operands.push_back(Operand); } - for (const llvm::MCPhysReg *MCPhysReg = MCInstrDesc.getImplicitUses(); + for (const llvm::MCPhysReg *MCPhysReg = Description->getImplicitUses(); MCPhysReg && *MCPhysReg; ++MCPhysReg, ++OpIndex) { Operand Operand; Operand.Index = OpIndex; Index: llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.h =================================================================== --- llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.h +++ llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.h @@ -54,7 +54,6 @@ protected: const LLVMState &State; - const RegisterAliasingTrackerCache RATC; // Generates a single code template that has a self-dependency. llvm::Expected Index: llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.cpp =================================================================== --- llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.cpp +++ llvm/trunk/tools/llvm-exegesis/lib/SnippetGenerator.cpp @@ -25,9 +25,7 @@ SnippetGeneratorFailure::SnippetGeneratorFailure(const llvm::Twine &S) : llvm::StringError(S, llvm::inconvertibleErrorCode()) {} -SnippetGenerator::SnippetGenerator(const LLVMState &State) - : State(State), RATC(State.getRegInfo(), - getFunctionReservedRegs(State.getTargetMachine())) {} +SnippetGenerator::SnippetGenerator(const LLVMState &State) : State(State) {} SnippetGenerator::~SnippetGenerator() = default; @@ -35,6 +33,7 @@ SnippetGenerator::generateConfigurations(unsigned Opcode) const { if (auto E = generateCodeTemplate(Opcode)) { CodeTemplate &CT = E.get(); + const auto &RATC = State.getRATC(); const llvm::BitVector &ForbiddenRegs = CT.ScratchSpacePointerInReg ? RATC.getRegister(CT.ScratchSpacePointerInReg).aliasedBits() @@ -64,7 +63,7 @@ // Ignore memory operands which are handled separately. // Loop invariant: DefinedRegs[i] is true iif it has been set at least once // before the current instruction. - llvm::BitVector DefinedRegs = RATC.emptyRegisters(); + llvm::BitVector DefinedRegs = State.getRATC().emptyRegisters(); std::vector RIV; for (const InstructionTemplate &IT : Instructions) { // Returns the register that this Operand sets or uses, or 0 if this is not Index: llvm/trunk/tools/llvm-exegesis/lib/Uops.cpp =================================================================== --- llvm/trunk/tools/llvm-exegesis/lib/Uops.cpp +++ llvm/trunk/tools/llvm-exegesis/lib/Uops.cpp @@ -130,7 +130,7 @@ CodeTemplate CT; const llvm::BitVector *ScratchSpaceAliasedRegs = nullptr; - const Instruction Instr(State.getInstrInfo().get(Opcode), RATC); + const Instruction Instr(State, Opcode); if (Instr.hasMemoryOperands()) { CT.ScratchSpacePointerInReg = ET.getScratchMemoryRegister(State.getTargetMachine().getTargetTriple()); @@ -138,7 +138,7 @@ return llvm::make_error( "Infeasible : target does not support memory instructions"); ScratchSpaceAliasedRegs = - &RATC.getRegister(CT.ScratchSpacePointerInReg).aliasedBits(); + &State.getRATC().getRegister(CT.ScratchSpacePointerInReg).aliasedBits(); // If the instruction implicitly writes to ScratchSpacePointerInReg , abort. // FIXME: We could make a copy of the scratch register. for (const auto &Op : Instr.Operands) { @@ -185,12 +185,13 @@ instantiateMemoryOperands(CT.ScratchSpacePointerInReg, CT.Instructions); return std::move(CT); } + const auto &ReservedRegisters = State.getRATC().reservedRegisters(); // No tied variables, we pick random values for defs. llvm::BitVector Defs(State.getRegInfo().getNumRegs()); for (const auto &Op : Instr.Operands) { if (Op.isReg() && Op.isExplicit() && Op.isDef() && !Op.isMemory()) { auto PossibleRegisters = Op.getRegisterAliasing().sourceBits(); - remove(PossibleRegisters, RATC.reservedRegisters()); + remove(PossibleRegisters, ReservedRegisters); // Do not use the scratch memory address register. if (ScratchSpaceAliasedRegs) remove(PossibleRegisters, *ScratchSpaceAliasedRegs); @@ -205,7 +206,7 @@ for (const auto &Op : Instr.Operands) { if (Op.isReg() && Op.isExplicit() && Op.isUse() && !Op.isMemory()) { auto PossibleRegisters = Op.getRegisterAliasing().sourceBits(); - remove(PossibleRegisters, RATC.reservedRegisters()); + remove(PossibleRegisters, ReservedRegisters); // Do not use the scratch memory address register. if (ScratchSpaceAliasedRegs) remove(PossibleRegisters, *ScratchSpaceAliasedRegs); Index: llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp =================================================================== --- llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp +++ llvm/trunk/tools/llvm-exegesis/lib/X86/Target.cpp @@ -37,9 +37,9 @@ } // Handle X87. - const auto &InstrDesc = InstrInfo.get(Opcode); - const unsigned FPInstClass = InstrDesc.TSFlags & llvm::X86II::FPTypeMask; - const Instruction Instr(InstrDesc, this->RATC); + const unsigned FPInstClass = + InstrInfo.get(Opcode).TSFlags & llvm::X86II::FPTypeMask; + const Instruction Instr(this->State, Opcode); switch (FPInstClass) { case llvm::X86II::NotFP: break; Index: llvm/trunk/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp =================================================================== --- llvm/trunk/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp +++ llvm/trunk/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp @@ -248,7 +248,7 @@ FakeSnippetGenerator(const LLVMState &State) : SnippetGenerator(State) {} Instruction createInstruction(unsigned Opcode) { - return Instruction(State.getInstrInfo().get(Opcode), RATC); + return Instruction(State, Opcode); } private: