This is an archive of the discontinued LLVM Phabricator instance.

Differential D53077

[MIPS GlobalISel] Legalize constants
ClosedPublic

Authored by Petar.Avramovic on Oct 10 2018, 6:43 AM.

Details

Reviewers
atanasyan
petarj
dsanders
Commits
rG8a0841253353: [MIPS GlobalISel] Legalize constants
rL344684: [MIPS GlobalISel] Legalize constants
Summary

Legalize s1, s8, s16 and s64 G_CONSTANT for MIPS 32.

Diff Detail

Repository
rL LLVM

Event Timeline

Petar.Avramovic created this revision.Oct 10 2018, 6:43 AM
Herald added subscribers: arichardson, kristof.beyls, rovka, sdardis. · View Herald TranscriptOct 10 2018, 6:43 AM
atanasyan accepted this revision.Oct 15 2018, 6:28 AM

LGTM

This revision is now accepted and ready to land.Oct 15 2018, 6:28 AM
Closed by commit rL344684: [MIPS GlobalISel] Legalize constants (authored by petarj). · Explain WhyOct 17 2018, 3:32 AM
This revision was automatically updated to reflect the committed changes.
Herald added subscribers: llvm-commits, jrtc27. · View Herald TranscriptOct 17 2018, 3:32 AM

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
25 lines
test/
CodeGen/
Mips/
GlobalISel/
legalizer/
164 lines
llvm-ir/
108 lines

Diff 169979

llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp

Show All 34 LinesMipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
getActionDefinitionsBuilder({G_AND, G_OR, G_XOR, G_SHL, G_ASHR, G_LSHR}) getActionDefinitionsBuilder({G_AND, G_OR, G_XOR, G_SHL, G_ASHR, G_LSHR})
.legalFor({s32}); .legalFor({s32});
getActionDefinitionsBuilder(G_ICMP) getActionDefinitionsBuilder(G_ICMP)
.legalFor({{s32, s32}}) .legalFor({{s32, s32}})
.minScalar(0, s32); .minScalar(0, s32);
getActionDefinitionsBuilder(G_CONSTANT) getActionDefinitionsBuilder(G_CONSTANT)
.legalFor({s32}); .legalFor({s32})
.minScalar(0, s32)
.customFor({s64});
getActionDefinitionsBuilder(G_GEP) getActionDefinitionsBuilder(G_GEP)
.legalFor({{p0, s32}}); .legalFor({{p0, s32}});
getActionDefinitionsBuilder(G_FRAME_INDEX) getActionDefinitionsBuilder(G_FRAME_INDEX)
.legalFor({p0}); .legalFor({p0});
getActionDefinitionsBuilder(G_GLOBAL_VALUE) getActionDefinitionsBuilder(G_GLOBAL_VALUE)
Show All 34 Lines case G_ADD: {
MIRBuilder.buildICmp(CmpInst::ICMP_ULT, Carry, ResLow, LHSLow); MIRBuilder.buildICmp(CmpInst::ICMP_ULT, Carry, ResLow, LHSLow);
MIRBuilder.buildAdd(ResHigh, TmpResHigh, Carry); MIRBuilder.buildAdd(ResHigh, TmpResHigh, Carry);
MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {ResHigh, ResLow}); MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {ResHigh, ResLow});
MI.eraseFromParent(); MI.eraseFromParent();
break; break;
} }
case G_CONSTANT: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
const LLT sHalf = LLT::scalar(Size / 2);
const APInt &CImmValue = MI.getOperand(1).getCImm()->getValue();
unsigned ResLow = MRI.createGenericVirtualRegister(sHalf);
unsigned ResHigh = MRI.createGenericVirtualRegister(sHalf);
MIRBuilder.buildConstant(
ResLow, *ConstantInt::get(MI.getMF()->getFunction().getContext(),
CImmValue.trunc(Size / 2)));
MIRBuilder.buildConstant(
ResHigh, *ConstantInt::get(MI.getMF()->getFunction().getContext(),
CImmValue.lshr(Size / 2).trunc(Size / 2)));
MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {ResHigh, ResLow});
MI.eraseFromParent();
break;
}
default: default:
return false; return false;
} }
return true; return true;
} }

llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
--- |
define void @any_i64() {entry: ret void}
define void @any_i32() {entry: ret void}
define void @signed_i16() {entry: ret void}
define void @signed_i8() {entry: ret void}
define void @unsigned_i16() {entry: ret void}
define void @unsigned_i8() {entry: ret void}
define void @i1_true() {entry: ret void}
define void @i1_false() {entry: ret void}
...
---
name: any_i64
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: any_i64
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; MIPS32: $v0 = COPY [[C]](s32)
; MIPS32: $v1 = COPY [[C1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
%0:_(s64) = G_CONSTANT i64 -9223372036854775808
%1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0(s64)
$v0 = COPY %2(s32)
$v1 = COPY %1(s32)
RetRA implicit $v0, implicit $v1
...
---
name: any_i32
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: any_i32
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; MIPS32: $v0 = COPY [[C]](s32)
; MIPS32: RetRA implicit $v0
%0:_(s32) = G_CONSTANT i32 -2147483648
$v0 = COPY %0(s32)
RetRA implicit $v0
...
---
name: signed_i16
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: signed_i16
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]]
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]]
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
%0:_(s16) = G_CONSTANT i16 -32768
%1:_(s32) = G_SEXT %0(s16)
$v0 = COPY %1(s32)
RetRA implicit $v0
...
---
name: signed_i8
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: signed_i8
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -128
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]]
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]]
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
%0:_(s8) = G_CONSTANT i8 -128
%1:_(s32) = G_SEXT %0(s8)
$v0 = COPY %1(s32)
RetRA implicit $v0
...
---
name: unsigned_i16
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: unsigned_i16
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0
%0:_(s16) = G_CONSTANT i16 -32768
%1:_(s32) = G_ZEXT %0(s16)
$v0 = COPY %1(s32)
RetRA implicit $v0
...
---
name: unsigned_i8
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: unsigned_i8
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -128
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0
%0:_(s8) = G_CONSTANT i8 -128
%1:_(s32) = G_ZEXT %0(s8)
$v0 = COPY %1(s32)
RetRA implicit $v0
...
---
name: i1_true
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: i1_true
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0
%0:_(s1) = G_CONSTANT i1 true
%1:_(s32) = G_ZEXT %0(s1)
$v0 = COPY %1(s32)
RetRA implicit $v0
...
---
name: i1_false
alignment: 2
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: i1_false
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0
%0:_(s1) = G_CONSTANT i1 false
%1:_(s32) = G_ZEXT %0(s1)
$v0 = COPY %1(s32)
RetRA implicit $v0
...

llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
define i64 @any_i64() {
; MIPS32-LABEL: any_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, 0
; MIPS32-NEXT: ori $2, $1, 0
; MIPS32-NEXT: lui $1, 32768
; MIPS32-NEXT: ori $3, $1, 0
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
ret i64 -9223372036854775808
}
define i32 @any_i32() {
; MIPS32-LABEL: any_i32:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, 32768
; MIPS32-NEXT: ori $2, $1, 0
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
ret i32 -2147483648
}
define signext i16 @signed_i16() {
; MIPS32-LABEL: signed_i16:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, 65535
; MIPS32-NEXT: ori $1, $1, 32768
; MIPS32-NEXT: sll $1, $1, 16
; MIPS32-NEXT: sra $2, $1, 16
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
ret i16 -32768
}
define signext i8 @signed_i8() {
; MIPS32-LABEL: signed_i8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, 65535
; MIPS32-NEXT: ori $1, $1, 65408
; MIPS32-NEXT: sll $1, $1, 24
; MIPS32-NEXT: sra $2, $1, 24
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
ret i8 -128
}
define zeroext i16 @unsigned_i16() {
; MIPS32-LABEL: unsigned_i16:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, 65535
; MIPS32-NEXT: ori $1, $1, 32768
; MIPS32-NEXT: lui $2, 0
; MIPS32-NEXT: ori $2, $2, 65535
; MIPS32-NEXT: and $2, $1, $2
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
ret i16 -32768
}
define zeroext i8 @unsigned_i8() {
; MIPS32-LABEL: unsigned_i8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, 65535
; MIPS32-NEXT: ori $1, $1, 65408
; MIPS32-NEXT: lui $2, 0
; MIPS32-NEXT: ori $2, $2, 255
; MIPS32-NEXT: and $2, $1, $2
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
ret i8 -128
}
define zeroext i1 @i1_true() {
; MIPS32-LABEL: i1_true:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, 65535
; MIPS32-NEXT: ori $1, $1, 65535
; MIPS32-NEXT: lui $2, 0
; MIPS32-NEXT: ori $2, $2, 1
; MIPS32-NEXT: and $2, $1, $2
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
ret i1 true
}
define zeroext i1 @i1_false() {
; MIPS32-LABEL: i1_false:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, 0
; MIPS32-NEXT: ori $1, $1, 0
; MIPS32-NEXT: lui $2, 0
; MIPS32-NEXT: ori $2, $2, 1
; MIPS32-NEXT: and $2, $1, $2
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
ret i1 false
}