Index: include/llvm/CodeGen/ISDOpcodes.h =================================================================== --- include/llvm/CodeGen/ISDOpcodes.h +++ include/llvm/CodeGen/ISDOpcodes.h @@ -256,6 +256,14 @@ /// Same for multiplication. SMULO, UMULO, + /// RESULT = SADDSAT(LHS, RHS) - Perform signed saturation addition on 2 + /// integers with the same bit width (W). If the true value of LHS + RHS + /// exceeds the largest signed value that can be represented by W bits, the + /// resulting value is this maximum value. Otherwise, if this value is less + /// than the smallest signed value that can be represented by W bits, the + /// resulting value is this minimum value. + SADDSAT, + /// Simple binary floating point operators. FADD, FSUB, FMUL, FDIV, FREM, Index: include/llvm/CodeGen/TargetLowering.h =================================================================== --- include/llvm/CodeGen/TargetLowering.h +++ include/llvm/CodeGen/TargetLowering.h @@ -797,6 +797,10 @@ return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op]; } + /// Method for building the DAG expansion of ISD::SADDSAT. + SDValue getExpandedSignedSaturationAddition(SDNode *Node, + SelectionDAG &DAG) const; + LegalizeAction getStrictFPOperationAction(unsigned Op, EVT VT) const { unsigned EqOpc; switch (Op) { Index: include/llvm/IR/Intrinsics.td =================================================================== --- include/llvm/IR/Intrinsics.td +++ include/llvm/IR/Intrinsics.td @@ -700,6 +700,12 @@ [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]>; +//===------------------------- Fixed Point Intrinsics ---------------------===// +// +def int_sadd_sat : Intrinsic<[llvm_anyint_ty], + [LLVMMatchType<0>, LLVMMatchType<0>], + [IntrNoMem, IntrSpeculatable]>; + //===------------------------- Memory Use Markers -------------------------===// // def int_lifetime_start : Intrinsic<[], Index: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp =================================================================== --- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -1115,6 +1115,10 @@ Action = TLI.getStrictFPOperationAction(Node->getOpcode(), Node->getValueType(0)); break; + case ISD::SADDSAT: { + Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); + break; + } case ISD::MSCATTER: Action = TLI.getOperationAction(Node->getOpcode(), cast(Node)->getValue().getValueType()); @@ -3460,6 +3464,10 @@ } break; } + case ISD::SADDSAT: { + Results.push_back(TLI.getExpandedSignedSaturationAddition(Node, DAG)); + break; + } case ISD::SADDO: case ISD::SSUBO: { SDValue LHS = Node->getOperand(0); Index: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp =================================================================== --- lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -141,6 +141,8 @@ case ISD::ADDCARRY: case ISD::SUBCARRY: Res = PromoteIntRes_ADDSUBCARRY(N, ResNo); break; + case ISD::SADDSAT: Res = PromoteIntRes_SADDSAT(N); break; + case ISD::ATOMIC_LOAD: Res = PromoteIntRes_Atomic0(cast(N)); break; @@ -534,6 +536,39 @@ return SDValue(Res.getNode(), 1); } +SDValue DAGTypeLegalizer::PromoteIntRes_SADDSAT(SDNode *N) { + // For promoting iN -> iM, this can be expanded by + // 1. ANY_EXTEND iN to iM + // 2. SHL by M-N + // 3. SADDSAT + // 4. ASHR by M-N + SDLoc dl(N); + SDValue Op1 = N->getOperand(0); + SDValue Op2 = N->getOperand(1); + unsigned OldBits = Op1.getValueSizeInBits(); + + SDValue Op1Promoted = GetPromotedInteger(Op1); + Op1Promoted = + DAG.getNode(ISD::ANY_EXTEND, dl, Op1Promoted.getValueType(), Op1Promoted); + SDValue Op2Promoted = GetPromotedInteger(Op2); + Op2Promoted = + DAG.getNode(ISD::ANY_EXTEND, dl, Op2Promoted.getValueType(), Op2Promoted); + + EVT PromotedType = Op1Promoted.getValueType(); + unsigned NewBits = Op1Promoted.getValueSizeInBits(); + unsigned SHLAmount = NewBits - OldBits; + EVT SHVT = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout()); + SDValue ShiftAmount = DAG.getConstant(SHLAmount, dl, SHVT); + Op1Promoted = + DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount); + Op2Promoted = + DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount); + + SDValue Result = + DAG.getNode(ISD::SADDSAT, dl, PromotedType, Op1Promoted, Op2Promoted); + return DAG.getNode(ISD::SRA, dl, PromotedType, Result, ShiftAmount); +} + SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) { if (ResNo == 1) return PromoteIntRes_Overflow(N); @@ -1454,6 +1489,8 @@ case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break; case ISD::UMULO: case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break; + + case ISD::SADDSAT: ExpandIntRes_SATSADD(N, Lo, Hi); break; } // If Lo/Hi is null, the sub-method took care of registering results etc. @@ -2416,6 +2453,12 @@ ReplaceValueWith(SDValue(N, 1), R.getValue(2)); } +void DAGTypeLegalizer::ExpandIntRes_SATSADD(SDNode *N, SDValue &Lo, + SDValue &Hi) { + SDValue Result = TLI.getExpandedSignedSaturationAddition(N, DAG); + SplitInteger(Result, Lo, Hi); +} + void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node, SDValue &Lo, SDValue &Hi) { SDValue LHS = Node->getOperand(0); @@ -2962,6 +3005,7 @@ ISD::CondCode &CCCode, const SDLoc &dl) { SDValue LHSLo, LHSHi, RHSLo, RHSHi; + NewLHS.dump(); GetExpandedInteger(NewLHS, LHSLo, LHSHi); GetExpandedInteger(NewRHS, RHSLo, RHSHi); Index: lib/CodeGen/SelectionDAG/LegalizeTypes.h =================================================================== --- lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -330,6 +330,7 @@ SDValue PromoteIntRes_UNDEF(SDNode *N); SDValue PromoteIntRes_VAARG(SDNode *N); SDValue PromoteIntRes_XMULO(SDNode *N, unsigned ResNo); + SDValue PromoteIntRes_SADDSAT(SDNode *N); // Integer Operand Promotion. bool PromoteIntegerOperand(SDNode *N, unsigned OpNo); @@ -414,6 +415,7 @@ void ExpandIntRes_SADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandIntRes_UADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandIntRes_XMULO (SDNode *N, SDValue &Lo, SDValue &Hi); + void ExpandIntRes_SATSADD (SDNode *N, SDValue &Lo, SDValue &Hi); void ExpandIntRes_ATOMIC_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi); Index: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp =================================================================== --- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -5759,6 +5759,12 @@ setValue(&I, DAG.getSelect(sdl, VT, IsZeroShift, IsFSHL ? X : Y, Or)); return nullptr; } + case Intrinsic::sadd_sat: { + SDValue Op1 = getValue(I.getArgOperand(0)); + SDValue Op2 = getValue(I.getArgOperand(1)); + setValue(&I, DAG.getNode(ISD::SADDSAT, sdl, Op1.getValueType(), Op1, Op2)); + return nullptr; + } case Intrinsic::stacksave: { SDValue Op = getRoot(); Res = DAG.getNode( Index: lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp =================================================================== --- lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp +++ lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp @@ -282,6 +282,8 @@ case ISD::SRA_PARTS: return "sra_parts"; case ISD::SRL_PARTS: return "srl_parts"; + case ISD::SADDSAT: return "saddsat"; + // Conversion operators. case ISD::SIGN_EXTEND: return "sign_extend"; case ISD::ZERO_EXTEND: return "zero_extend"; Index: lib/CodeGen/TargetLoweringBase.cpp =================================================================== --- lib/CodeGen/TargetLoweringBase.cpp +++ lib/CodeGen/TargetLoweringBase.cpp @@ -608,6 +608,7 @@ setOperationAction(ISD::UMIN, VT, Expand); setOperationAction(ISD::UMAX, VT, Expand); setOperationAction(ISD::ABS, VT, Expand); + setOperationAction(ISD::SADDSAT, VT, Expand); // Overflow operations default to expand setOperationAction(ISD::SADDO, VT, Expand); @@ -1857,3 +1858,53 @@ void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const { MF.getRegInfo().freezeReservedRegs(MF); } + +SDValue TargetLoweringBase::getExpandedSignedSaturationAddition( + SDNode *Node, SelectionDAG &DAG) const { + assert(Node->getOpcode() == ISD::SADDSAT && + "Expected method to receive SADDSAT node."); + assert(Node->getNumOperands() == 2 && + "Expected SADDSAT node to have 2 operands."); + + SDLoc dl(Node); + SDValue LHS = Node->getOperand(0); + SDValue RHS = Node->getOperand(1); + assert(LHS.getValueType().isScalarInteger() && + "Expected operands to be scalar integers in SADDSAT"); + assert(RHS.getValueType().isScalarInteger() && + "Expected operands to be scalar integers in SADDSAT"); + unsigned BitWidth = LHS.getValueSizeInBits(); + + EVT ResultType = LHS.getValueType(); + SDValue Sum = DAG.getNode(ISD::ADD, dl, ResultType, LHS, RHS); + + // Compute the overflow. + // + // SatMax -> (LHS > 0) && (RHS > 0) && (Sum < 0) + // SatMin -> (LHS < 0) && (RHS < 0) && (Sum > 0) + // + SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType()); + EVT BoolVT = + getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i1); + + SDValue LHSPos = DAG.getSetCC(dl, BoolVT, LHS, Zero, ISD::SETGT); + SDValue RHSPos = DAG.getSetCC(dl, BoolVT, RHS, Zero, ISD::SETGT); + SDValue SumPos = DAG.getSetCC(dl, BoolVT, Sum, Zero, ISD::SETGT); + SDValue LHSNeg = DAG.getSetCC(dl, BoolVT, LHS, Zero, ISD::SETLT); + SDValue RHSNeg = DAG.getSetCC(dl, BoolVT, RHS, Zero, ISD::SETLT); + SDValue SumNeg = DAG.getSetCC(dl, BoolVT, Sum, Zero, ISD::SETLT); + + SDValue OperandsPos = DAG.getNode(ISD::AND, dl, BoolVT, LHSPos, RHSPos); + SDValue OperandsNeg = DAG.getNode(ISD::AND, dl, BoolVT, LHSNeg, RHSNeg); + + SDValue UseSatMax = DAG.getNode(ISD::AND, dl, BoolVT, OperandsPos, SumNeg); + SDValue UseSatMin = DAG.getNode(ISD::AND, dl, BoolVT, OperandsNeg, SumPos); + + APInt MinVal = APInt::getSignedMinValue(BitWidth); + APInt MaxVal = APInt::getSignedMaxValue(BitWidth); + SDValue SatMin = DAG.getConstant(MinVal, dl, ResultType); + SDValue SatMax = DAG.getConstant(MaxVal, dl, ResultType); + + SDValue Result = DAG.getSelect(dl, ResultType, UseSatMax, SatMax, Sum); + return DAG.getSelect(dl, ResultType, UseSatMin, SatMin, Result); +} Index: lib/IR/Verifier.cpp =================================================================== --- lib/IR/Verifier.cpp +++ lib/IR/Verifier.cpp @@ -4473,6 +4473,15 @@ break; } + case Intrinsic::sadd_sat: { + Value *Op1 = CS.getArgOperand(0); + Value *Op2 = CS.getArgOperand(1); + Assert(Op1->getType()->isIntegerTy(), + "first operand of sadd_sat must be an int type"); + Assert(Op2->getType()->isIntegerTy(), + "second operand of sadd_sat must be an int type"); + break; + } }; } Index: test/CodeGen/X86/sadd_sat.ll =================================================================== --- /dev/null +++ test/CodeGen/X86/sadd_sat.ll @@ -0,0 +1,142 @@ +; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mcpu=generic -march=x86 | FileCheck %s --check-prefix=CHECK32 + +declare i4 @llvm.sadd.sat.i4 (i4, i4) +declare i32 @llvm.sadd.sat.i32 (i32, i32) +declare i64 @llvm.sadd.sat.i64 (i64, i64) + +define i32 @func(i32 %x, i32 %y) { +; CHECK: func +; CHECK: # %bb.0: +; CHECK-NEXT: testl %edi, %edi +; CHECK-NEXT: sets %r8b +; CHECK-NEXT: setg %cl +; CHECK-NEXT: testl %esi, %esi +; CHECK-NEXT: sets %dl +; CHECK-NEXT: setg %al +; CHECK-NEXT: andb %cl, %al +; CHECK-NEXT: addl %esi, %edi +; CHECK-NEXT: testl %edi, %edi +; CHECK-NEXT: setg %sil +; CHECK-NEXT: sets %cl +; CHECK-NEXT: testb %cl, %al +; CHECK-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF +; CHECK-NEXT: cmovel %edi, %ecx +; CHECK-NEXT: andb %r8b, %dl +; CHECK-NEXT: testb %sil, %dl +; CHECK-NEXT: movl $-2147483648, %eax # imm = 0x80000000 +; CHECK-NEXT: cmovel %ecx, %eax +; CHECK-NEXT: retq + %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y); + ret i32 %tmp; +} + +define i64 @func2(i64 %x, i64 %y) { +; CHECK32: func2 +; CHECK32: # %bb.0: +; CHECK32: pushl %ebp +; CHECK32: .cfi_def_cfa_offset 8 +; CHECK32: pushl %ebx +; CHECK32: .cfi_def_cfa_offset 12 +; CHECK32: pushl %edi +; CHECK32: .cfi_def_cfa_offset 16 +; CHECK32: pushl %esi +; CHECK32: .cfi_def_cfa_offset 20 +; CHECK32: .cfi_offset %esi, -20 +; CHECK32: .cfi_offset %edi, -16 +; CHECK32: .cfi_offset %ebx, -12 +; CHECK32: .cfi_offset %ebp, -8 +; CHECK32: movl 20(%esp), %esi +; CHECK32: movl 24(%esp), %edx +; CHECK32: movl 28(%esp), %edi +; CHECK32: movl 32(%esp), %eax +; CHECK32: movl %edi, %ebx +; CHECK32: negl %ebx +; CHECK32: movl $0, %ebx +; CHECK32: sbbl %eax, %ebx +; CHECK32: setl %bl +; CHECK32: movl %esi, %ebp +; CHECK32: negl %ebp +; CHECK32: movl $0, %ebp +; CHECK32: sbbl %edx, %ebp +; CHECK32: setl %cl +; CHECK32: andb %bl, %cl +; CHECK32: addl %edi, %esi +; CHECK32: movl %edx, %ebx +; CHECK32: adcl %eax, %ebx +; CHECK32: sets %ch +; CHECK32: testb %ch, %cl +; CHECK32: movl $2147483647, %edi # imm = 0x7FFFFFFF +; CHECK32: jne .LBB1_2 +; CHECK32: # %bb.1: +; CHECK32: movl %ebx, %edi +; CHECK32: .LBB1_2: +; CHECK32: movl $-1, %ebp +; CHECK32: jne .LBB1_4 +; CHECK32: # %bb.3: +; CHECK32: movl %esi, %ebp +; CHECK32: .LBB1_4: +; CHECK32: negl %esi +; CHECK32: movl $0, %ecx +; CHECK32: sbbl %ebx, %ecx +; CHECK32: setl %cl +; CHECK32: testl %eax, 24(%esp) +; CHECK32: sets %dl +; CHECK32: testb %cl, %dl +; CHECK32: movl $0, %eax +; CHECK32: jne .LBB1_6 +; CHECK32: # %bb.5: +; CHECK32: movl %ebp, %eax +; CHECK32: .LBB1_6: +; CHECK32: movl $-2147483648, %edx # imm = 0x80000000 +; CHECK32: jne .LBB1_8 +; CHECK32: # %bb.7: +; CHECK32: movl %edi, %edx +; CHECK32: .LBB1_8: +; CHECK32: popl %esi +; CHECK32: .cfi_def_cfa_offset 16 +; CHECK32: popl %edi +; CHECK32: .cfi_def_cfa_offset 12 +; CHECK32: popl %ebx +; CHECK32: .cfi_def_cfa_offset 8 +; CHECK32: popl %ebp +; CHECK32: .cfi_def_cfa_offset 4 +; CHECK32: retl + %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y); + ret i64 %tmp; +} + +define i4 @func3(i4 %x, i4 %y) { +; CHECK: func3 +; CHECK: # %bb.0: +; CHECK-NEXT: shlb $4, %dil +; CHECK-NEXT: testb %dil, %dil +; CHECK-NEXT: sets %al +; CHECK-NEXT: setg %cl +; CHECK-NEXT: shlb $4, %sil +; CHECK-NEXT: testb %sil, %sil +; CHECK-NEXT: sets %r8b +; CHECK-NEXT: setg %dl +; CHECK-NEXT: andb %cl, %dl +; CHECK-NEXT: addb %dil, %sil +; CHECK-NEXT: testb %sil, %sil +; CHECK-NEXT: setg %dil +; CHECK-NEXT: sets %cl +; CHECK-NEXT: testb %cl, %dl +; CHECK-NEXT: movb $127, %dl +; CHECK-NEXT: jne .LBB2_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: movl %esi, %edx +; CHECK-NEXT: .LBB2_2: +; CHECK-NEXT: andb %r8b, %al +; CHECK-NEXT: testb %dil, %al +; CHECK-NEXT: movb $-128, %al +; CHECK-NEXT: jne .LBB2_4 +; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: movl %edx, %eax +; CHECK-NEXT: .LBB2_4: +; CHECK-NEXT: sarb $4, %al +; CHECK-NEXT: retq + %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y); + ret i4 %tmp; +}