Index: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -708,8 +708,12 @@ return MCID.getSize(); // If this machine instr is an inline asm, measure it. - if (MI.getOpcode() == ARM::INLINEASM) - return getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI); + if (MI.getOpcode() == ARM::INLINEASM) { + unsigned Size = getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI); + if (!MF->getInfo()->isThumbFunction()) + Size = alignTo(Size, 4); + return Size; + } unsigned Opc = MI.getOpcode(); switch (Opc) { default: Index: llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp =================================================================== --- llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp +++ llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp @@ -31,6 +31,9 @@ SupportsDebugInformation = true; + // Conditional Thumb 4-byte instructions can have an implicit IT. + MaxInstLength = 6; + // Exceptions handling ExceptionsType = (TheTriple.isOSDarwin() && !TheTriple.isWatchABI()) ? ExceptionHandling::SjLj @@ -56,6 +59,9 @@ SupportsDebugInformation = true; + // Conditional Thumb 4-byte instructions can have an implicit IT. + MaxInstLength = 6; + // Exceptions handling switch (TheTriple.getOS()) { case Triple::NetBSD: @@ -90,6 +96,9 @@ PrivateGlobalPrefix = "$M"; PrivateLabelPrefix = "$M"; CommentString = ";"; + + // Conditional Thumb 4-byte instructions can have an implicit IT. + MaxInstLength = 6; } void ARMCOFFMCAsmInfoGNU::anchor() { } @@ -110,5 +119,7 @@ UseIntegratedAssembler = true; DwarfRegNumForCFI = false; -} + // Conditional Thumb 4-byte instructions can have an implicit IT. + MaxInstLength = 6; +} Index: llvm/trunk/test/CodeGen/ARM/cbz-implicit-it-range.ll =================================================================== --- llvm/trunk/test/CodeGen/ARM/cbz-implicit-it-range.ll +++ llvm/trunk/test/CodeGen/ARM/cbz-implicit-it-range.ll @@ -0,0 +1,47 @@ +;RUN: llc -O2 -mtriple=thumbv7a-linux-gnueabihf -arm-implicit-it=always %s -o - | FileCheck %s +;RUN: llc -O2 -mtriple=thumbv7a-linux-gnueabihf -no-integrated-as %s -o - | FileCheck %s + +; Check that we do not produce a CBZ instruction to jump over the inline +; assembly as the distance is too far if the implicit IT instructions are +; added. + +define void @f0(i32 %p1, i32 %p2, i32 %p3) nounwind { +entry: + %cmp = icmp eq i32 %p1, 0 + br i1 %cmp, label %if.else, label %if.then + +if.then: + tail call void asm sideeffect "movseq r0, #0\0A", ""() + tail call void asm sideeffect "movseq r0, #0\0A", ""() + tail call void asm sideeffect "movseq r0, #0\0A", ""() + tail call void asm sideeffect "movseq r0, #0\0A", ""() + tail call void asm sideeffect "movseq r0, #0\0A", ""() + tail call void asm sideeffect "movseq r0, #0\0A", ""() + tail call void asm sideeffect "movseq r0, #0\0A", ""() + tail call void asm sideeffect "movseq r0, #0\0A", ""() + tail call void asm sideeffect "movseq r0, #0\0A", ""() + tail call void asm sideeffect "movseq r0, #0\0A", ""() + tail call void asm sideeffect "movseq r0, #0\0A", ""() + tail call void asm sideeffect "movseq r0, #0\0A", ""() + tail call void asm sideeffect "movseq r0, #0\0A", ""() + tail call void asm sideeffect "movseq r0, #0\0A", ""() + tail call void asm sideeffect "movseq r0, #0\0A", ""() + tail call void asm sideeffect "movseq r0, #0\0A", ""() + tail call void asm sideeffect "movseq r0, #0\0A", ""() + tail call void asm sideeffect "movseq r0, #0\0A", ""() + tail call void asm sideeffect "movseq r0, #0\0A", ""() + tail call void asm sideeffect "movseq r0, #0\0A", ""() + tail call void asm sideeffect "movseq r0, #0\0A", ""() + tail call void asm sideeffect "movseq r0, #0\0A", ""() + br label %if.end + +if.else: + tail call void asm sideeffect "nop\0A", ""() + br label %if.end + +if.end: + ret void +} +; CHECK-LABEL: f0: +; CHECK: beq .LBB0_{{[0-9]+}} +