[AArch64] Enable post-RA MI scheduler

[ssijaric]

Summary

We saw improvements in spec2000/mesa (5%) and spec2000/crafty (3%) on cortex-a53 when compiled with -Ofast -mcpu=cortex-a53. The patch enables the post-RA MI scheduler for both cortex-a53 and cortex-a57, but I haven't done runs on cortex-a57. If compile time is an issue, perhaps we can enable this only for the in-order architectures (e.g. cortex-a53).

Thanks,
Sanjin

[Jiangning]

Hi Sanji,

I measured Spec2000 for cortex-a57, and got the following results,

(negative is good)

spec.cpu2000.ref.175_vpr 1.63%
spec.cpu2000.ref.253_perlbmk 1.17%
spec.cpu2000.ref.300_twolf 1.48%

spec.cpu2000.ref.177_mesa -2.88%
spec.cpu2000.ref.183_equake -3.78%
spec.cpu2000.ref.188_ammp -1.49%
spec.cpu2000.ref.255_vortex -1.78%
spec.cpu2000.ref.256_bzip2 -1.17%

I think the result on A57 is OK, and at least no significant regression.

Thanks,
-Jiangning

2014-09-10 5:34 GMT+08:00 Sanjin Sijaric <[e-mail]>:

Hi mcrosier, Jiangning, jmolloy, t.p.northover,

We saw improvements in spec2000/mesa (5%) and spec2000/crafty (3%) on
cortex-a53 when compiled with -Ofast -mcpu=cortex-a53. The patch enables
the post-RA MI scheduler for both cortex-a53 and cortex-a57, but I haven't
done runs on cortex-a57. If compile time is an issue, perhaps we can
enable this only for the in-order architectures (e.g. cortex-a53).

Thanks,
Sanjin

http://reviews.llvm.org/D5278

Files:

lib/Target/AArch64/AArch64Subtarget.h
lib/Target/AArch64/AArch64TargetMachine.cpp
test/CodeGen/AArch64/arm64-postra-mi-sched.ll

[mcrosier]

In D5278#7, @Jiangning wrote:

Hi Sanji,

I measured Spec2000 for cortex-a57, and got the following results,
I think the result on A57 is OK, and at least no significant regression.

Thanks,
-Jiangning

Jiangning,
Did the compile-times look okay?

[ssijaric]

Hi Jiangning,

Thanks for the A57 runs.

I ran compile time measurements when compiling spec2000 and spec2006. There was no overall degradation, but the compiles weren't done in a "stable" environment. There are similar variations when running two back-to-back compiles with the same configuration.

[mcrosier]

Is anyone opposed to this being pushed. Jiangning confirmed the performance findings on A57. Internally, we saw good numbers on an A53 devices. No serious compile time regressions were reported. I'd like to get this in before our weekend performance run, so please let me know.

Chad

test/CodeGen/AArch64/arm64-postra-mi-sched.ll

1

I'll update the -march to use aarch64 before pushing.

[atrick]

Awesome. Thanks for doing this.

[rengolin]

Hi Chad,

I also saw no regressions on A57 and some improvements. LGTM.

cheers,
--renato

[mcrosier]

Committed in r217693. Thanks, everyone.

lib/Target/AArch64/AArch64Subtarget.h

     return &getInstrInfo()->getRegisterInfo();
   }
   bool enableMachineScheduler() const override { return true; }
+  bool enablePostMachineScheduler() const override {
+    return isCortexA53() || isCortexA57();
+  }
 
   bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
 

lib/Target/AArch64/AArch64TargetMachine.cpp

 class AArch64PassConfig : public TargetPassConfig {
 public:
   AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
-      : TargetPassConfig(TM, PM) {}
+      : TargetPassConfig(TM, PM) {
+    substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
+  }
 
   AArch64TargetMachine &getAArch64TargetMachine() const {
     return getTM<AArch64TargetMachine>();

test/CodeGen/AArch64/arm64-postra-mi-sched.ll

+; RUN: llc < %s -O3 -march=arm64 -mcpu=cortex-a53 | FileCheck %s
+; With cortex-a53, each of fmul and fcvt have latency of 6 cycles.  After the
+; pre-RA MI scheduler, fmul, fcvt and fdiv will be consecutive.  The top-down
+; post-RA MI scheduler will clean this up.
+@d1 = common global double 0.000000e+00, align 8
+
+; Function Attrs: nounwind
+define i32 @f(float %s2, float %s3, double %d, i32 %i2, i32 %i3) #0 {
+entry:
+; CHECK: fmul
+; CHECK-NEXT: add
+; CHECK: fcvt
+; CHECK-NEXT: mul
+  %mul = fmul float %s2, %s3
+  %conv = fpext float %mul to double
+  %div = fdiv double %d, %conv
+  store double %div, double* @d1, align 8, !tbaa !1
+  %factor = shl i32 %i3, 1
+  %add1 = add i32 %i2, 4
+  %add2 = add i32 %add1, %factor
+  %add3 = add nsw i32 %add2, %i2
+  %add4 = add nsw i32 %add3, %add2
+  %mul5 = mul i32 %add3, %add3
+  %mul6 = mul i32 %mul5, %add4
+  %mul7 = shl i32 %add4, 1
+  %factor18 = mul i32 %mul7, %mul6
+  %add9 = add i32 %factor18, %mul6
+  ret i32 %add9
+}
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.ident = !{!0}
+
+!0 = metadata !{metadata !"clang version 3.6.0 "}
+!1 = metadata !{metadata !2, metadata !2, i64 0}
+!2 = metadata !{metadata !"double", metadata !3, i64 0}
+!3 = metadata !{metadata !"omnipotent char", metadata !4, i64 0}
+!4 = metadata !{metadata !"Simple C/C++ TBAA"}