Index: lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp =================================================================== --- lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp +++ lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp @@ -39,7 +39,7 @@ static MCRegisterInfo *createMSP430MCRegisterInfo(StringRef TT) { MCRegisterInfo *X = new MCRegisterInfo(); - InitMSP430MCRegisterInfo(X, MSP430::PCW); + InitMSP430MCRegisterInfo(X, MSP430::PC); return X; } Index: lib/Target/MSP430/MSP430CallingConv.td =================================================================== --- lib/Target/MSP430/MSP430CallingConv.td +++ lib/Target/MSP430/MSP430CallingConv.td @@ -17,7 +17,7 @@ CCIfType<[i8], CCAssignToReg<[R15B, R14B, R13B, R12B]>>, // i16 are returned in registers R15, R14, R13, R12 - CCIfType<[i16], CCAssignToReg<[R15W, R14W, R13W, R12W]>> + CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>> ]>; //===----------------------------------------------------------------------===// Index: lib/Target/MSP430/MSP430FrameLowering.cpp =================================================================== --- lib/Target/MSP430/MSP430FrameLowering.cpp +++ lib/Target/MSP430/MSP430FrameLowering.cpp @@ -63,18 +63,18 @@ // Update the frame offset adjustment. MFI->setOffsetAdjustment(-NumBytes); - // Save FPW into the appropriate stack slot... + // Save FP into the appropriate stack slot... BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) - .addReg(MSP430::FPW, RegState::Kill); + .addReg(MSP430::FP, RegState::Kill); - // Update FPW with the new base value... - BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW) - .addReg(MSP430::SPW); + // Update FP with the new base value... + BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FP) + .addReg(MSP430::SP); // Mark the FramePtr as live-in in every block except the entry. for (MachineFunction::iterator I = std::next(MF.begin()), E = MF.end(); I != E; ++I) - I->addLiveIn(MSP430::FPW); + I->addLiveIn(MSP430::FP); } else NumBytes = StackSize - MSP430FI->getCalleeSavedFrameSize(); @@ -86,18 +86,18 @@ if (MBBI != MBB.end()) DL = MBBI->getDebugLoc(); - if (NumBytes) { // adjust stack pointer: SPW -= numbytes - // If there is an SUB16ri of SPW immediately before this instruction, merge + if (NumBytes) { // adjust stack pointer: SP -= numbytes + // If there is an SUB16ri of SP immediately before this instruction, merge // the two. //NumBytes -= mergeSPUpdates(MBB, MBBI, true); - // If there is an ADD16ri or SUB16ri of SPW immediately after this + // If there is an ADD16ri or SUB16ri of SP immediately after this // instruction, merge the two instructions. // mergeSPUpdatesDown(MBB, MBBI, &NumBytes); if (NumBytes) { MachineInstr *MI = - BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW) - .addReg(MSP430::SPW).addImm(NumBytes); + BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP) + .addReg(MSP430::SP).addImm(NumBytes); // The SRW implicit def is dead. MI->getOperand(3).setIsDead(); } @@ -132,8 +132,8 @@ uint64_t FrameSize = StackSize - 2; NumBytes = FrameSize - CSSize; - // pop FPW. - BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW); + // pop FP. + BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FP); } else NumBytes = StackSize - CSSize; @@ -148,28 +148,28 @@ DL = MBBI->getDebugLoc(); - // If there is an ADD16ri or SUB16ri of SPW immediately before this + // If there is an ADD16ri or SUB16ri of SP immediately before this // instruction, merge the two instructions. //if (NumBytes || MFI->hasVarSizedObjects()) // mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes); if (MFI->hasVarSizedObjects()) { BuildMI(MBB, MBBI, DL, - TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW); + TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::FP); if (CSSize) { MachineInstr *MI = BuildMI(MBB, MBBI, DL, - TII.get(MSP430::SUB16ri), MSP430::SPW) - .addReg(MSP430::SPW).addImm(CSSize); + TII.get(MSP430::SUB16ri), MSP430::SP) + .addReg(MSP430::SP).addImm(CSSize); // The SRW implicit def is dead. MI->getOperand(3).setIsDead(); } } else { - // adjust stack pointer back: SPW += numbytes + // adjust stack pointer back: SP += numbytes if (NumBytes) { MachineInstr *MI = - BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW) - .addReg(MSP430::SPW).addImm(NumBytes); + BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SP) + .addReg(MSP430::SP).addImm(NumBytes); // The SRW implicit def is dead. MI->getOperand(3).setIsDead(); } @@ -232,8 +232,8 @@ if (!hasReservedCallFrame(MF)) { // If the stack pointer can be changed after prologue, turn the - // adjcallstackup instruction into a 'sub SPW, ' and the - // adjcallstackdown instruction into 'add SPW, ' + // adjcallstackup instruction into a 'sub SP, ' and the + // adjcallstackdown instruction into 'add SP, ' // TODO: consider using push / pop instead of sub + store / add MachineInstr *Old = I; uint64_t Amount = Old->getOperand(0).getImm(); @@ -246,8 +246,8 @@ MachineInstr *New = nullptr; if (Old->getOpcode() == TII.getCallFrameSetupOpcode()) { New = BuildMI(MF, Old->getDebugLoc(), - TII.get(MSP430::SUB16ri), MSP430::SPW) - .addReg(MSP430::SPW).addImm(Amount); + TII.get(MSP430::SUB16ri), MSP430::SP) + .addReg(MSP430::SP).addImm(Amount); } else { assert(Old->getOpcode() == TII.getCallFrameDestroyOpcode()); // factor out the amount the callee already popped. @@ -255,8 +255,8 @@ Amount -= CalleeAmt; if (Amount) New = BuildMI(MF, Old->getDebugLoc(), - TII.get(MSP430::ADD16ri), MSP430::SPW) - .addReg(MSP430::SPW).addImm(Amount); + TII.get(MSP430::ADD16ri), MSP430::SP) + .addReg(MSP430::SP).addImm(Amount); } if (New) { @@ -274,7 +274,7 @@ MachineInstr *Old = I; MachineInstr *New = BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri), - MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt); + MSP430::SP).addReg(MSP430::SP).addImm(CalleeAmt); // The SRW implicit def is dead. New->getOperand(3).setIsDead(); @@ -288,11 +288,11 @@ void MSP430FrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *) const { - // Create a frame entry for the FPW register that must be saved. + // Create a frame entry for the FP register that must be saved. if (hasFP(MF)) { int FrameIdx = MF.getFrameInfo()->CreateFixedObject(2, -4, true); (void)FrameIdx; assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() && - "Slot for FPW register must be last in order to be found!"); + "Slot for FP register must be last in order to be found!"); } } Index: lib/Target/MSP430/MSP430ISelLowering.cpp =================================================================== --- lib/Target/MSP430/MSP430ISelLowering.cpp +++ lib/Target/MSP430/MSP430ISelLowering.cpp @@ -72,7 +72,7 @@ // Division is expensive setIntDivIsCheap(false); - setStackPointerRegisterToSaveRestore(MSP430::SPW); + setStackPointerRegisterToSaveRestore(MSP430::SP); setBooleanContents(ZeroOrOneBooleanContent); setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? @@ -282,7 +282,7 @@ SmallVectorImpl &ArgLocs, const SmallVectorImpl &Args) { static const MCPhysReg RegList[] = { - MSP430::R15W, MSP430::R14W, MSP430::R13W, MSP430::R12W + MSP430::R15, MSP430::R14, MSP430::R13, MSP430::R12 }; static const unsigned NbRegs = array_lengthof(RegList); @@ -627,7 +627,7 @@ assert(VA.isMemLoc()); if (!StackPtr.getNode()) - StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy()); + StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, getPointerTy()); SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, @@ -941,31 +941,31 @@ Convert = false; break; case MSP430CC::COND_HS: - // Res = SRW & 1, no processing is required + // Res = SR & 1, no processing is required break; case MSP430CC::COND_LO: - // Res = ~(SRW & 1) + // Res = ~(SR & 1) Invert = true; break; case MSP430CC::COND_NE: if (andCC) { - // C = ~Z, thus Res = SRW & 1, no processing is required + // C = ~Z, thus Res = SR & 1, no processing is required } else { - // Res = ~((SRW >> 1) & 1) + // Res = ~((SR >> 1) & 1) Shift = true; Invert = true; } break; case MSP430CC::COND_E: Shift = true; - // C = ~Z for AND instruction, thus we can put Res = ~(SRW & 1), however, - // Res = (SRW >> 1) & 1 is 1 word shorter. + // C = ~Z for AND instruction, thus we can put Res = ~(SR & 1), however, + // Res = (SR >> 1) & 1 is 1 word shorter. break; } EVT VT = Op.getValueType(); SDValue One = DAG.getConstant(1, VT); if (Convert) { - SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW, + SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR, MVT::i16, Flag); if (Shift) // FIXME: somewhere this is turned into a SRL, lower it MSP specific? @@ -1074,7 +1074,7 @@ SDLoc dl(Op); // FIXME probably not meaningful unsigned Depth = cast(Op.getOperand(0))->getZExtValue(); SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, - MSP430::FPW, VT); + MSP430::FP, VT); while (Depth--) FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, MachinePointerInfo(), Index: lib/Target/MSP430/MSP430InstrInfo.td =================================================================== --- lib/Target/MSP430/MSP430InstrInfo.td +++ lib/Target/MSP430/MSP430InstrInfo.td @@ -111,8 +111,8 @@ // a stack adjustment and the codegen must know that they may modify the stack // pointer before prolog-epilog rewriting occurs. // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become -// sub / add which can clobber SRW. -let Defs = [SPW, SRW], Uses = [SPW] in { +// sub / add which can clobber SR. +let Defs = [SP, SR], Uses = [SP] in { def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt), "#ADJCALLSTACKDOWN", [(MSP430callseq_start timm:$amt)]>; @@ -130,7 +130,7 @@ "# Select16 PSEUDO", [(set GR16:$dst, (MSP430selectcc GR16:$src, GR16:$src2, imm:$cc))]>; - let Defs = [SRW] in { + let Defs = [SR] in { def Shl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt), "# Shl8 PSEUDO", [(set GR8:$dst, (MSP430shl GR8:$src, GR8:$cnt))]>; @@ -192,7 +192,7 @@ } // Conditional branches -let Uses = [SRW] in +let Uses = [SR] in def JCC : CJForm<0, 0, (outs), (ins jmptarget:$dst, cc:$cc), "j$cc\t$dst", @@ -207,8 +207,8 @@ // a use to prevent stack-pointer assignments that appear immediately // before calls from potentially appearing dead. Uses for argument // registers are added manually. - let Defs = [R12W, R13W, R14W, R15W, SRW], - Uses = [SPW] in { + let Defs = [R12, R13, R14, R15, SR], + Uses = [SP] in { def CALLi : II16i<0x0, (outs), (ins i16imm:$dst), "call\t$dst", [(MSP430call imm:$dst)]>; @@ -224,7 +224,7 @@ //===----------------------------------------------------------------------===// // Miscellaneous Instructions... // -let Defs = [SPW], Uses = [SPW], neverHasSideEffects=1 in { +let Defs = [SP], Uses = [SP], neverHasSideEffects=1 in { let mayLoad = 1 in def POP16r : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes, (outs GR16:$reg), (ins), "pop.w\t$reg", []>; @@ -337,7 +337,7 @@ let Constraints = "$src = $dst" in { -let Defs = [SRW] in { +let Defs = [SR] in { let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y @@ -345,24 +345,24 @@ (outs GR8:$dst), (ins GR8:$src, GR8:$src2), "add.b\t{$src2, $dst}", [(set GR8:$dst, (add GR8:$src, GR8:$src2)), - (implicit SRW)]>; + (implicit SR)]>; def ADD16rr : I16rr<0x0, (outs GR16:$dst), (ins GR16:$src, GR16:$src2), "add.w\t{$src2, $dst}", [(set GR16:$dst, (add GR16:$src, GR16:$src2)), - (implicit SRW)]>; + (implicit SR)]>; } def ADD8rm : I8rm<0x0, (outs GR8:$dst), (ins GR8:$src, memsrc:$src2), "add.b\t{$src2, $dst}", [(set GR8:$dst, (add GR8:$src, (load addr:$src2))), - (implicit SRW)]>; + (implicit SR)]>; def ADD16rm : I16rm<0x0, (outs GR16:$dst), (ins GR16:$src, memsrc:$src2), "add.w\t{$src2, $dst}", [(set GR16:$dst, (add GR16:$src, (load addr:$src2))), - (implicit SRW)]>; + (implicit SR)]>; let mayLoad = 1, hasExtraDefRegAllocReq = 1, Constraints = "$base = $base_wb, $src = $dst" in { @@ -381,160 +381,160 @@ (outs GR8:$dst), (ins GR8:$src, i8imm:$src2), "add.b\t{$src2, $dst}", [(set GR8:$dst, (add GR8:$src, imm:$src2)), - (implicit SRW)]>; + (implicit SR)]>; def ADD16ri : I16ri<0x0, (outs GR16:$dst), (ins GR16:$src, i16imm:$src2), "add.w\t{$src2, $dst}", [(set GR16:$dst, (add GR16:$src, imm:$src2)), - (implicit SRW)]>; + (implicit SR)]>; let Constraints = "" in { def ADD8mr : I8mr<0x0, (outs), (ins memdst:$dst, GR8:$src), "add.b\t{$src, $dst}", [(store (add (load addr:$dst), GR8:$src), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def ADD16mr : I16mr<0x0, (outs), (ins memdst:$dst, GR16:$src), "add.w\t{$src, $dst}", [(store (add (load addr:$dst), GR16:$src), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def ADD8mi : I8mi<0x0, (outs), (ins memdst:$dst, i8imm:$src), "add.b\t{$src, $dst}", [(store (add (load addr:$dst), (i8 imm:$src)), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def ADD16mi : I16mi<0x0, (outs), (ins memdst:$dst, i16imm:$src), "add.w\t{$src, $dst}", [(store (add (load addr:$dst), (i16 imm:$src)), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def ADD8mm : I8mm<0x0, (outs), (ins memdst:$dst, memsrc:$src), "add.b\t{$src, $dst}", [(store (add (load addr:$dst), (i8 (load addr:$src))), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def ADD16mm : I16mm<0x0, (outs), (ins memdst:$dst, memsrc:$src), "add.w\t{$src, $dst}", [(store (add (load addr:$dst), (i16 (load addr:$src))), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; } -let Uses = [SRW] in { +let Uses = [SR] in { let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y def ADC8rr : I8rr<0x0, (outs GR8:$dst), (ins GR8:$src, GR8:$src2), "addc.b\t{$src2, $dst}", [(set GR8:$dst, (adde GR8:$src, GR8:$src2)), - (implicit SRW)]>; + (implicit SR)]>; def ADC16rr : I16rr<0x0, (outs GR16:$dst), (ins GR16:$src, GR16:$src2), "addc.w\t{$src2, $dst}", [(set GR16:$dst, (adde GR16:$src, GR16:$src2)), - (implicit SRW)]>; + (implicit SR)]>; } // isCommutable def ADC8ri : I8ri<0x0, (outs GR8:$dst), (ins GR8:$src, i8imm:$src2), "addc.b\t{$src2, $dst}", [(set GR8:$dst, (adde GR8:$src, imm:$src2)), - (implicit SRW)]>; + (implicit SR)]>; def ADC16ri : I16ri<0x0, (outs GR16:$dst), (ins GR16:$src, i16imm:$src2), "addc.w\t{$src2, $dst}", [(set GR16:$dst, (adde GR16:$src, imm:$src2)), - (implicit SRW)]>; + (implicit SR)]>; def ADC8rm : I8rm<0x0, (outs GR8:$dst), (ins GR8:$src, memsrc:$src2), "addc.b\t{$src2, $dst}", [(set GR8:$dst, (adde GR8:$src, (load addr:$src2))), - (implicit SRW)]>; + (implicit SR)]>; def ADC16rm : I16rm<0x0, (outs GR16:$dst), (ins GR16:$src, memsrc:$src2), "addc.w\t{$src2, $dst}", [(set GR16:$dst, (adde GR16:$src, (load addr:$src2))), - (implicit SRW)]>; + (implicit SR)]>; let Constraints = "" in { def ADC8mr : I8mr<0x0, (outs), (ins memdst:$dst, GR8:$src), "addc.b\t{$src, $dst}", [(store (adde (load addr:$dst), GR8:$src), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def ADC16mr : I16mr<0x0, (outs), (ins memdst:$dst, GR16:$src), "addc.w\t{$src, $dst}", [(store (adde (load addr:$dst), GR16:$src), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def ADC8mi : I8mi<0x0, (outs), (ins memdst:$dst, i8imm:$src), "addc.b\t{$src, $dst}", [(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def ADC16mi : I16mi<0x0, (outs), (ins memdst:$dst, i16imm:$src), "addc.w\t{$src, $dst}", [(store (adde (load addr:$dst), (i16 imm:$src)), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def ADC8mm : I8mm<0x0, (outs), (ins memdst:$dst, memsrc:$src), "addc.b\t{$src, $dst}", [(store (adde (load addr:$dst), (i8 (load addr:$src))), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def ADC16mm : I8mm<0x0, (outs), (ins memdst:$dst, memsrc:$src), "addc.w\t{$src, $dst}", [(store (adde (load addr:$dst), (i16 (load addr:$src))), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; } -} // Uses = [SRW] +} // Uses = [SR] let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y def AND8rr : I8rr<0x0, (outs GR8:$dst), (ins GR8:$src, GR8:$src2), "and.b\t{$src2, $dst}", [(set GR8:$dst, (and GR8:$src, GR8:$src2)), - (implicit SRW)]>; + (implicit SR)]>; def AND16rr : I16rr<0x0, (outs GR16:$dst), (ins GR16:$src, GR16:$src2), "and.w\t{$src2, $dst}", [(set GR16:$dst, (and GR16:$src, GR16:$src2)), - (implicit SRW)]>; + (implicit SR)]>; } def AND8ri : I8ri<0x0, (outs GR8:$dst), (ins GR8:$src, i8imm:$src2), "and.b\t{$src2, $dst}", [(set GR8:$dst, (and GR8:$src, imm:$src2)), - (implicit SRW)]>; + (implicit SR)]>; def AND16ri : I16ri<0x0, (outs GR16:$dst), (ins GR16:$src, i16imm:$src2), "and.w\t{$src2, $dst}", [(set GR16:$dst, (and GR16:$src, imm:$src2)), - (implicit SRW)]>; + (implicit SR)]>; def AND8rm : I8rm<0x0, (outs GR8:$dst), (ins GR8:$src, memsrc:$src2), "and.b\t{$src2, $dst}", [(set GR8:$dst, (and GR8:$src, (load addr:$src2))), - (implicit SRW)]>; + (implicit SR)]>; def AND16rm : I16rm<0x0, (outs GR16:$dst), (ins GR16:$src, memsrc:$src2), "and.w\t{$src2, $dst}", [(set GR16:$dst, (and GR16:$src, (load addr:$src2))), - (implicit SRW)]>; + (implicit SR)]>; let mayLoad = 1, hasExtraDefRegAllocReq = 1, Constraints = "$base = $base_wb, $src = $dst" in { @@ -553,36 +553,36 @@ (outs), (ins memdst:$dst, GR8:$src), "and.b\t{$src, $dst}", [(store (and (load addr:$dst), GR8:$src), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def AND16mr : I16mr<0x0, (outs), (ins memdst:$dst, GR16:$src), "and.w\t{$src, $dst}", [(store (and (load addr:$dst), GR16:$src), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def AND8mi : I8mi<0x0, (outs), (ins memdst:$dst, i8imm:$src), "and.b\t{$src, $dst}", [(store (and (load addr:$dst), (i8 imm:$src)), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def AND16mi : I16mi<0x0, (outs), (ins memdst:$dst, i16imm:$src), "and.w\t{$src, $dst}", [(store (and (load addr:$dst), (i16 imm:$src)), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def AND8mm : I8mm<0x0, (outs), (ins memdst:$dst, memsrc:$src), "and.b\t{$src, $dst}", [(store (and (load addr:$dst), (i8 (load addr:$src))), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def AND16mm : I16mm<0x0, (outs), (ins memdst:$dst, memsrc:$src), "and.w\t{$src, $dst}", [(store (and (load addr:$dst), (i16 (load addr:$src))), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; } let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y @@ -703,35 +703,35 @@ (outs GR8:$dst), (ins GR8:$src, GR8:$src2), "xor.b\t{$src2, $dst}", [(set GR8:$dst, (xor GR8:$src, GR8:$src2)), - (implicit SRW)]>; + (implicit SR)]>; def XOR16rr : I16rr<0x0, (outs GR16:$dst), (ins GR16:$src, GR16:$src2), "xor.w\t{$src2, $dst}", [(set GR16:$dst, (xor GR16:$src, GR16:$src2)), - (implicit SRW)]>; + (implicit SR)]>; } def XOR8ri : I8ri<0x0, (outs GR8:$dst), (ins GR8:$src, i8imm:$src2), "xor.b\t{$src2, $dst}", [(set GR8:$dst, (xor GR8:$src, imm:$src2)), - (implicit SRW)]>; + (implicit SR)]>; def XOR16ri : I16ri<0x0, (outs GR16:$dst), (ins GR16:$src, i16imm:$src2), "xor.w\t{$src2, $dst}", [(set GR16:$dst, (xor GR16:$src, imm:$src2)), - (implicit SRW)]>; + (implicit SR)]>; def XOR8rm : I8rm<0x0, (outs GR8:$dst), (ins GR8:$src, memsrc:$src2), "xor.b\t{$src2, $dst}", [(set GR8:$dst, (xor GR8:$src, (load addr:$src2))), - (implicit SRW)]>; + (implicit SR)]>; def XOR16rm : I16rm<0x0, (outs GR16:$dst), (ins GR16:$src, memsrc:$src2), "xor.w\t{$src2, $dst}", [(set GR16:$dst, (xor GR16:$src, (load addr:$src2))), - (implicit SRW)]>; + (implicit SR)]>; let mayLoad = 1, hasExtraDefRegAllocReq = 1, Constraints = "$base = $base_wb, $src = $dst" in { @@ -750,34 +750,34 @@ (outs), (ins memdst:$dst, GR8:$src), "xor.b\t{$src, $dst}", [(store (xor (load addr:$dst), GR8:$src), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def XOR16mr : I16mr<0x0, (outs), (ins memdst:$dst, GR16:$src), "xor.w\t{$src, $dst}", [(store (xor (load addr:$dst), GR16:$src), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def XOR8mi : I8mi<0x0, (outs), (ins memdst:$dst, i8imm:$src), "xor.b\t{$src, $dst}", [(store (xor (load addr:$dst), (i8 imm:$src)), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def XOR16mi : I16mi<0x0, (outs), (ins memdst:$dst, i16imm:$src), "xor.w\t{$src, $dst}", [(store (xor (load addr:$dst), (i16 imm:$src)), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def XOR8mm : I8mm<0x0, (outs), (ins memdst:$dst, memsrc:$src), "xor.b\t{$src, $dst}", [(store (xor (load addr:$dst), (i8 (load addr:$src))), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def XOR16mm : I16mm<0x0, (outs), (ins memdst:$dst, memsrc:$src), "xor.w\t{$src, $dst}", [(store (xor (load addr:$dst), (i16 (load addr:$src))), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; } @@ -785,34 +785,34 @@ (outs GR8:$dst), (ins GR8:$src, GR8:$src2), "sub.b\t{$src2, $dst}", [(set GR8:$dst, (sub GR8:$src, GR8:$src2)), - (implicit SRW)]>; + (implicit SR)]>; def SUB16rr : I16rr<0x0, (outs GR16:$dst), (ins GR16:$src, GR16:$src2), "sub.w\t{$src2, $dst}", [(set GR16:$dst, (sub GR16:$src, GR16:$src2)), - (implicit SRW)]>; + (implicit SR)]>; def SUB8ri : I8ri<0x0, (outs GR8:$dst), (ins GR8:$src, i8imm:$src2), "sub.b\t{$src2, $dst}", [(set GR8:$dst, (sub GR8:$src, imm:$src2)), - (implicit SRW)]>; + (implicit SR)]>; def SUB16ri : I16ri<0x0, (outs GR16:$dst), (ins GR16:$src, i16imm:$src2), "sub.w\t{$src2, $dst}", [(set GR16:$dst, (sub GR16:$src, imm:$src2)), - (implicit SRW)]>; + (implicit SR)]>; def SUB8rm : I8rm<0x0, (outs GR8:$dst), (ins GR8:$src, memsrc:$src2), "sub.b\t{$src2, $dst}", [(set GR8:$dst, (sub GR8:$src, (load addr:$src2))), - (implicit SRW)]>; + (implicit SR)]>; def SUB16rm : I16rm<0x0, (outs GR16:$dst), (ins GR16:$src, memsrc:$src2), "sub.w\t{$src2, $dst}", [(set GR16:$dst, (sub GR16:$src, (load addr:$src2))), - (implicit SRW)]>; + (implicit SR)]>; let mayLoad = 1, hasExtraDefRegAllocReq = 1, Constraints = "$base = $base_wb, $src = $dst" in { @@ -831,153 +831,153 @@ (outs), (ins memdst:$dst, GR8:$src), "sub.b\t{$src, $dst}", [(store (sub (load addr:$dst), GR8:$src), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def SUB16mr : I16mr<0x0, (outs), (ins memdst:$dst, GR16:$src), "sub.w\t{$src, $dst}", [(store (sub (load addr:$dst), GR16:$src), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def SUB8mi : I8mi<0x0, (outs), (ins memdst:$dst, i8imm:$src), "sub.b\t{$src, $dst}", [(store (sub (load addr:$dst), (i8 imm:$src)), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def SUB16mi : I16mi<0x0, (outs), (ins memdst:$dst, i16imm:$src), "sub.w\t{$src, $dst}", [(store (sub (load addr:$dst), (i16 imm:$src)), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def SUB8mm : I8mm<0x0, (outs), (ins memdst:$dst, memsrc:$src), "sub.b\t{$src, $dst}", [(store (sub (load addr:$dst), (i8 (load addr:$src))), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def SUB16mm : I16mm<0x0, (outs), (ins memdst:$dst, memsrc:$src), "sub.w\t{$src, $dst}", [(store (sub (load addr:$dst), (i16 (load addr:$src))), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; } -let Uses = [SRW] in { +let Uses = [SR] in { def SBC8rr : I8rr<0x0, (outs GR8:$dst), (ins GR8:$src, GR8:$src2), "subc.b\t{$src2, $dst}", [(set GR8:$dst, (sube GR8:$src, GR8:$src2)), - (implicit SRW)]>; + (implicit SR)]>; def SBC16rr : I16rr<0x0, (outs GR16:$dst), (ins GR16:$src, GR16:$src2), "subc.w\t{$src2, $dst}", [(set GR16:$dst, (sube GR16:$src, GR16:$src2)), - (implicit SRW)]>; + (implicit SR)]>; def SBC8ri : I8ri<0x0, (outs GR8:$dst), (ins GR8:$src, i8imm:$src2), "subc.b\t{$src2, $dst}", [(set GR8:$dst, (sube GR8:$src, imm:$src2)), - (implicit SRW)]>; + (implicit SR)]>; def SBC16ri : I16ri<0x0, (outs GR16:$dst), (ins GR16:$src, i16imm:$src2), "subc.w\t{$src2, $dst}", [(set GR16:$dst, (sube GR16:$src, imm:$src2)), - (implicit SRW)]>; + (implicit SR)]>; def SBC8rm : I8rm<0x0, (outs GR8:$dst), (ins GR8:$src, memsrc:$src2), "subc.b\t{$src2, $dst}", [(set GR8:$dst, (sube GR8:$src, (load addr:$src2))), - (implicit SRW)]>; + (implicit SR)]>; def SBC16rm : I16rm<0x0, (outs GR16:$dst), (ins GR16:$src, memsrc:$src2), "subc.w\t{$src2, $dst}", [(set GR16:$dst, (sube GR16:$src, (load addr:$src2))), - (implicit SRW)]>; + (implicit SR)]>; let Constraints = "" in { def SBC8mr : I8mr<0x0, (outs), (ins memdst:$dst, GR8:$src), "subc.b\t{$src, $dst}", [(store (sube (load addr:$dst), GR8:$src), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def SBC16mr : I16mr<0x0, (outs), (ins memdst:$dst, GR16:$src), "subc.w\t{$src, $dst}", [(store (sube (load addr:$dst), GR16:$src), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def SBC8mi : I8mi<0x0, (outs), (ins memdst:$dst, i8imm:$src), "subc.b\t{$src, $dst}", [(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def SBC16mi : I16mi<0x0, (outs), (ins memdst:$dst, i16imm:$src), "subc.w\t{$src, $dst}", [(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def SBC8mm : I8mm<0x0, (outs), (ins memdst:$dst, memsrc:$src), "subc.b\t{$src, $dst}", [(store (sube (load addr:$dst), (i8 (load addr:$src))), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; def SBC16mm : I16mm<0x0, (outs), (ins memdst:$dst, memsrc:$src), "subc.w\t{$src, $dst}", [(store (sube (load addr:$dst), (i16 (load addr:$src))), addr:$dst), - (implicit SRW)]>; + (implicit SR)]>; } -} // Uses = [SRW] +} // Uses = [SR] // FIXME: memory variant! def SAR8r1 : II8r<0x0, (outs GR8:$dst), (ins GR8:$src), "rra.b\t$dst", [(set GR8:$dst, (MSP430rra GR8:$src)), - (implicit SRW)]>; + (implicit SR)]>; def SAR16r1 : II16r<0x0, (outs GR16:$dst), (ins GR16:$src), "rra.w\t$dst", [(set GR16:$dst, (MSP430rra GR16:$src)), - (implicit SRW)]>; + (implicit SR)]>; def SHL8r1 : I8rr<0x0, (outs GR8:$dst), (ins GR8:$src), "rla.b\t$dst", [(set GR8:$dst, (MSP430rla GR8:$src)), - (implicit SRW)]>; + (implicit SR)]>; def SHL16r1 : I16rr<0x0, (outs GR16:$dst), (ins GR16:$src), "rla.w\t$dst", [(set GR16:$dst, (MSP430rla GR16:$src)), - (implicit SRW)]>; + (implicit SR)]>; def SAR8r1c : Pseudo<(outs GR8:$dst), (ins GR8:$src), "clrc\n\t" "rrc.b\t$dst", [(set GR8:$dst, (MSP430rrc GR8:$src)), - (implicit SRW)]>; + (implicit SR)]>; def SAR16r1c : Pseudo<(outs GR16:$dst), (ins GR16:$src), "clrc\n\t" "rrc.w\t$dst", [(set GR16:$dst, (MSP430rrc GR16:$src)), - (implicit SRW)]>; + (implicit SR)]>; // FIXME: Memory sext's ? def SEXT16r : II16r<0x0, (outs GR16:$dst), (ins GR16:$src), "sxt\t$dst", [(set GR16:$dst, (sext_inreg GR16:$src, i8)), - (implicit SRW)]>; + (implicit SR)]>; -} // Defs = [SRW] +} // Defs = [SR] def ZEXT16r : I8rr<0x0, (outs GR16:$dst), (ins GR16:$src), @@ -993,57 +993,57 @@ } // Constraints = "$src = $dst" // Integer comparisons -let Defs = [SRW] in { +let Defs = [SR] in { def CMP8rr : I8rr<0x0, (outs), (ins GR8:$src, GR8:$src2), "cmp.b\t{$src2, $src}", - [(MSP430cmp GR8:$src, GR8:$src2), (implicit SRW)]>; + [(MSP430cmp GR8:$src, GR8:$src2), (implicit SR)]>; def CMP16rr : I16rr<0x0, (outs), (ins GR16:$src, GR16:$src2), "cmp.w\t{$src2, $src}", - [(MSP430cmp GR16:$src, GR16:$src2), (implicit SRW)]>; + [(MSP430cmp GR16:$src, GR16:$src2), (implicit SR)]>; def CMP8ri : I8ri<0x0, (outs), (ins GR8:$src, i8imm:$src2), "cmp.b\t{$src2, $src}", - [(MSP430cmp GR8:$src, imm:$src2), (implicit SRW)]>; + [(MSP430cmp GR8:$src, imm:$src2), (implicit SR)]>; def CMP16ri : I16ri<0x0, (outs), (ins GR16:$src, i16imm:$src2), "cmp.w\t{$src2, $src}", - [(MSP430cmp GR16:$src, imm:$src2), (implicit SRW)]>; + [(MSP430cmp GR16:$src, imm:$src2), (implicit SR)]>; def CMP8mi : I8mi<0x0, (outs), (ins memsrc:$src, i8imm:$src2), "cmp.b\t{$src2, $src}", [(MSP430cmp (load addr:$src), - (i8 imm:$src2)), (implicit SRW)]>; + (i8 imm:$src2)), (implicit SR)]>; def CMP16mi : I16mi<0x0, (outs), (ins memsrc:$src, i16imm:$src2), "cmp.w\t{$src2, $src}", [(MSP430cmp (load addr:$src), - (i16 imm:$src2)), (implicit SRW)]>; + (i16 imm:$src2)), (implicit SR)]>; def CMP8rm : I8rm<0x0, (outs), (ins GR8:$src, memsrc:$src2), "cmp.b\t{$src2, $src}", [(MSP430cmp GR8:$src, (load addr:$src2)), - (implicit SRW)]>; + (implicit SR)]>; def CMP16rm : I16rm<0x0, (outs), (ins GR16:$src, memsrc:$src2), "cmp.w\t{$src2, $src}", [(MSP430cmp GR16:$src, (load addr:$src2)), - (implicit SRW)]>; + (implicit SR)]>; def CMP8mr : I8mr<0x0, (outs), (ins memsrc:$src, GR8:$src2), "cmp.b\t{$src2, $src}", [(MSP430cmp (load addr:$src), GR8:$src2), - (implicit SRW)]>; + (implicit SR)]>; def CMP16mr : I16mr<0x0, (outs), (ins memsrc:$src, GR16:$src2), "cmp.w\t{$src2, $src}", [(MSP430cmp (load addr:$src), GR16:$src2), - (implicit SRW)]>; + (implicit SR)]>; // BIT TESTS, just sets condition codes @@ -1053,56 +1053,56 @@ (outs), (ins GR8:$src, GR8:$src2), "bit.b\t{$src2, $src}", [(MSP430cmp (and_su GR8:$src, GR8:$src2), 0), - (implicit SRW)]>; + (implicit SR)]>; def BIT16rr : I16rr<0x0, (outs), (ins GR16:$src, GR16:$src2), "bit.w\t{$src2, $src}", [(MSP430cmp (and_su GR16:$src, GR16:$src2), 0), - (implicit SRW)]>; + (implicit SR)]>; } def BIT8ri : I8ri<0x0, (outs), (ins GR8:$src, i8imm:$src2), "bit.b\t{$src2, $src}", [(MSP430cmp (and_su GR8:$src, imm:$src2), 0), - (implicit SRW)]>; + (implicit SR)]>; def BIT16ri : I16ri<0x0, (outs), (ins GR16:$src, i16imm:$src2), "bit.w\t{$src2, $src}", [(MSP430cmp (and_su GR16:$src, imm:$src2), 0), - (implicit SRW)]>; + (implicit SR)]>; def BIT8rm : I8rm<0x0, (outs), (ins GR8:$src, memdst:$src2), "bit.b\t{$src2, $src}", [(MSP430cmp (and_su GR8:$src, (load addr:$src2)), 0), - (implicit SRW)]>; + (implicit SR)]>; def BIT16rm : I16rm<0x0, (outs), (ins GR16:$src, memdst:$src2), "bit.w\t{$src2, $src}", [(MSP430cmp (and_su GR16:$src, (load addr:$src2)), 0), - (implicit SRW)]>; + (implicit SR)]>; def BIT8mr : I8mr<0x0, (outs), (ins memsrc:$src, GR8:$src2), "bit.b\t{$src2, $src}", [(MSP430cmp (and_su (load addr:$src), GR8:$src2), 0), - (implicit SRW)]>; + (implicit SR)]>; def BIT16mr : I16mr<0x0, (outs), (ins memsrc:$src, GR16:$src2), "bit.w\t{$src2, $src}", [(MSP430cmp (and_su (load addr:$src), GR16:$src2), 0), - (implicit SRW)]>; + (implicit SR)]>; def BIT8mi : I8mi<0x0, (outs), (ins memsrc:$src, i8imm:$src2), "bit.b\t{$src2, $src}", [(MSP430cmp (and_su (load addr:$src), (i8 imm:$src2)), 0), - (implicit SRW)]>; + (implicit SR)]>; def BIT16mi : I16mi<0x0, (outs), (ins memsrc:$src, i16imm:$src2), "bit.w\t{$src2, $src}", [(MSP430cmp (and_su (load addr:$src), (i16 imm:$src2)), 0), - (implicit SRW)]>; + (implicit SR)]>; def BIT8mm : I8mm<0x0, (outs), (ins memsrc:$src, memsrc:$src2), @@ -1110,15 +1110,15 @@ [(MSP430cmp (and_su (i8 (load addr:$src)), (load addr:$src2)), 0), - (implicit SRW)]>; + (implicit SR)]>; def BIT16mm : I16mm<0x0, (outs), (ins memsrc:$src, memsrc:$src2), "bit.w\t{$src2, $src}", [(MSP430cmp (and_su (i16 (load addr:$src)), (load addr:$src2)), 0), - (implicit SRW)]>; -} // Defs = [SRW] + (implicit SR)]>; +} // Defs = [SR] //===----------------------------------------------------------------------===// // Non-Instruction Patterns Index: lib/Target/MSP430/MSP430RegisterInfo.cpp =================================================================== --- lib/Target/MSP430/MSP430RegisterInfo.cpp +++ lib/Target/MSP430/MSP430RegisterInfo.cpp @@ -33,32 +33,32 @@ // FIXME: Provide proper call frame setup / destroy opcodes. MSP430RegisterInfo::MSP430RegisterInfo() - : MSP430GenRegisterInfo(MSP430::PCW) {} + : MSP430GenRegisterInfo(MSP430::PC) {} const MCPhysReg* MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering(); const Function* F = MF->getFunction(); static const MCPhysReg CalleeSavedRegs[] = { - MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W, - MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W, + MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, + MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, 0 }; static const MCPhysReg CalleeSavedRegsFP[] = { - MSP430::R5W, MSP430::R6W, MSP430::R7W, - MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W, + MSP430::R5, MSP430::R6, MSP430::R7, + MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, 0 }; static const MCPhysReg CalleeSavedRegsIntr[] = { - MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W, - MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W, - MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W, + MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, + MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, + MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, 0 }; static const MCPhysReg CalleeSavedRegsIntrFP[] = { - MSP430::R5W, MSP430::R6W, MSP430::R7W, - MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W, - MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W, + MSP430::R5, MSP430::R6, MSP430::R7, + MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, + MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, 0 }; @@ -80,15 +80,15 @@ Reserved.set(MSP430::SPB); Reserved.set(MSP430::SRB); Reserved.set(MSP430::CGB); - Reserved.set(MSP430::PCW); - Reserved.set(MSP430::SPW); - Reserved.set(MSP430::SRW); - Reserved.set(MSP430::CGW); + Reserved.set(MSP430::PC); + Reserved.set(MSP430::SP); + Reserved.set(MSP430::SR); + Reserved.set(MSP430::CG); // Mark frame pointer as reserved if needed. if (TFI->hasFP(MF)) { Reserved.set(MSP430::FPB); - Reserved.set(MSP430::FPW); + Reserved.set(MSP430::FP); } return Reserved; @@ -113,7 +113,7 @@ DebugLoc dl = MI.getDebugLoc(); int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); - unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW); + unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FP : MSP430::SP); int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); // Skip the saved PC @@ -122,7 +122,7 @@ if (!TFI->hasFP(MF)) Offset += MF.getFrameInfo()->getStackSize(); else - Offset += 2; // Skip the saved FPW + Offset += 2; // Skip the saved FP // Fold imm into offset Offset += MI.getOperand(FIOperandNum + 1).getImm(); @@ -158,5 +158,5 @@ unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const { const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); - return TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW; + return TFI->hasFP(MF) ? MSP430::FP : MSP430::SP; } Index: lib/Target/MSP430/MSP430RegisterInfo.td =================================================================== --- lib/Target/MSP430/MSP430RegisterInfo.td +++ lib/Target/MSP430/MSP430RegisterInfo.td @@ -46,22 +46,22 @@ def subreg_8bit : SubRegIndex<8> { let Namespace = "MSP430"; } let SubRegIndices = [subreg_8bit] in { -def PCW : MSP430RegWithSubregs<0, "r0", [PCB]>; -def SPW : MSP430RegWithSubregs<1, "r1", [SPB]>; -def SRW : MSP430RegWithSubregs<2, "r2", [SRB]>; -def CGW : MSP430RegWithSubregs<3, "r3", [CGB]>; -def FPW : MSP430RegWithSubregs<4, "r4", [FPB]>; -def R5W : MSP430RegWithSubregs<5, "r5", [R5B]>; -def R6W : MSP430RegWithSubregs<6, "r6", [R6B]>; -def R7W : MSP430RegWithSubregs<7, "r7", [R7B]>; -def R8W : MSP430RegWithSubregs<8, "r8", [R8B]>; -def R9W : MSP430RegWithSubregs<9, "r9", [R9B]>; -def R10W : MSP430RegWithSubregs<10, "r10", [R10B]>; -def R11W : MSP430RegWithSubregs<11, "r11", [R11B]>; -def R12W : MSP430RegWithSubregs<12, "r12", [R12B]>; -def R13W : MSP430RegWithSubregs<13, "r13", [R13B]>; -def R14W : MSP430RegWithSubregs<14, "r14", [R14B]>; -def R15W : MSP430RegWithSubregs<15, "r15", [R15B]>; +def PC : MSP430RegWithSubregs<0, "r0", [PCB]>; +def SP : MSP430RegWithSubregs<1, "r1", [SPB]>; +def SR : MSP430RegWithSubregs<2, "r2", [SRB]>; +def CG : MSP430RegWithSubregs<3, "r3", [CGB]>; +def FP : MSP430RegWithSubregs<4, "r4", [FPB]>; +def R5 : MSP430RegWithSubregs<5, "r5", [R5B]>; +def R6 : MSP430RegWithSubregs<6, "r6", [R6B]>; +def R7 : MSP430RegWithSubregs<7, "r7", [R7B]>; +def R8 : MSP430RegWithSubregs<8, "r8", [R8B]>; +def R9 : MSP430RegWithSubregs<9, "r9", [R9B]>; +def R10 : MSP430RegWithSubregs<10, "r10", [R10B]>; +def R11 : MSP430RegWithSubregs<11, "r11", [R11B]>; +def R12 : MSP430RegWithSubregs<12, "r12", [R12B]>; +def R13 : MSP430RegWithSubregs<13, "r13", [R13B]>; +def R14 : MSP430RegWithSubregs<14, "r14", [R14B]>; +def R15 : MSP430RegWithSubregs<15, "r15", [R15B]>; } def GR8 : RegisterClass<"MSP430", [i8], 8, @@ -74,8 +74,8 @@ def GR16 : RegisterClass<"MSP430", [i16], 16, // Volatile registers - (add R12W, R13W, R14W, R15W, R11W, R10W, R9W, R8W, R7W, R6W, R5W, + (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5, // Frame pointer, sometimes allocable - FPW, + FP, // Volatile, but not allocable - PCW, SPW, SRW, CGW)>; + PC, SP, SR, CG)>; Index: test/CodeGen/MSP430/asm-clobbers.ll =================================================================== --- /dev/null +++ test/CodeGen/MSP430/asm-clobbers.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s | FileCheck %s + +target datalayout = "e-m:e-p:16:16-i32:16:32-a:16-n8:16" +target triple = "msp430---elf" + +define void @test() { +entry: +; CHECK-LABEL: test: +; CHECK: push.w r10 + call void asm sideeffect "", "~{r10}"() +; CHECK: pop.w r10 + ret void +}