Index: test/Transforms/InstCombine/stop_bad_undef_propagation.ll
===================================================================
--- /dev/null
+++ test/Transforms/InstCombine/stop_bad_undef_propagation.ll
@@ -0,0 +1,218 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define <3 x float> @udiv0(<3 x float> %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @udiv0(
+; CHECK-NEXT:  .entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
+; CHECK-NEXT:    ret <3 x float> [[TMP1]]
+;
+.entry:
+  %0 = insertelement <2 x i32> undef, i32 %y, i32 0
+  %1 = insertelement <2 x i32> %0, i32 %z, i32 1
+  %2 = udiv <2 x i32> %1, <i32 255, i32 255>
+  %3 = uitofp <2 x i32> %2 to <2 x float>
+  %4 = shufflevector <2 x float> %3, <2 x float> undef, <3 x i32> <i32 0, i32 1, i32 undef>
+  %5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
+  %6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
+  ret <3 x float> %6
+}
+
+define <3 x float> @udiv1(<3 x float> %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @udiv1(
+; CHECK-NEXT:  .entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
+; CHECK-NEXT:    ret <3 x float> [[TMP1]]
+;
+.entry:
+  %0 = insertelement <2 x i32> undef, i32 %y, i32 0
+  %1 = insertelement <2 x i32> %0, i32 %z, i32 1
+  %2 = udiv <2 x i32> %1, <i32 255, i32 255>
+  %3 = uitofp <2 x i32> %2 to <2 x float>
+  %4 = shufflevector <2 x float> %3, <2 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
+  %6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
+  ret <3 x float> %6
+}
+
+define <3 x float> @udiv2(<3 x float> %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @udiv2(
+; CHECK-NEXT:  .entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
+; CHECK-NEXT:    ret <3 x float> [[TMP1]]
+;
+.entry:
+  %0 = insertelement <2 x i32> undef, i32 %y, i32 0
+  %1 = insertelement <2 x i32> %0, i32 %z, i32 1
+  %2 = udiv <2 x i32> %1, <i32 255, i32 255>
+  %3 = uitofp <2 x i32> %2 to <2 x float>
+  %4 = shufflevector <2 x float> undef, <2 x float> %3, <3 x i32> <i32 2, i32 3, i32 undef>
+  %5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
+  %6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
+  ret <3 x float> %6
+}
+
+define <3 x float> @sdiv0(<3 x float> %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @sdiv0(
+; CHECK-NEXT:  .entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
+; CHECK-NEXT:    ret <3 x float> [[TMP1]]
+;
+.entry:
+  %0 = insertelement <2 x i32> undef, i32 %y, i32 0
+  %1 = insertelement <2 x i32> %0, i32 %z, i32 1
+  %2 = sdiv <2 x i32> %1, <i32 255, i32 255>
+  %3 = sitofp <2 x i32> %2 to <2 x float>
+  %4 = shufflevector <2 x float> %3, <2 x float> undef, <3 x i32> <i32 0, i32 1, i32 undef>
+  %5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
+  %6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
+  ret <3 x float> %6
+}
+
+define <3 x float> @sdiv1(<3 x float> %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @sdiv1(
+; CHECK-NEXT:  .entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
+; CHECK-NEXT:    ret <3 x float> [[TMP1]]
+;
+.entry:
+  %0 = insertelement <2 x i32> undef, i32 %y, i32 0
+  %1 = insertelement <2 x i32> %0, i32 %z, i32 1
+  %2 = sdiv <2 x i32> %1, <i32 255, i32 255>
+  %3 = sitofp <2 x i32> %2 to <2 x float>
+  %4 = shufflevector <2 x float> %3, <2 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
+  %6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
+  ret <3 x float> %6
+}
+
+define <3 x float> @sdiv2(<3 x float> %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @sdiv2(
+; CHECK-NEXT:  .entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
+; CHECK-NEXT:    ret <3 x float> [[TMP1]]
+;
+.entry:
+  %0 = insertelement <2 x i32> undef, i32 %y, i32 0
+  %1 = insertelement <2 x i32> %0, i32 %z, i32 1
+  %2 = sdiv <2 x i32> %1, <i32 255, i32 255>
+  %3 = sitofp <2 x i32> %2 to <2 x float>
+  %4 = shufflevector <2 x float> undef, <2 x float> %3, <3 x i32> <i32 2, i32 3, i32 undef>
+  %5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
+  %6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
+  ret <3 x float> %6
+}
+
+define <3 x float> @urem0(<3 x float> %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @urem0(
+; CHECK-NEXT:  .entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
+; CHECK-NEXT:    ret <3 x float> [[TMP1]]
+;
+.entry:
+  %0 = insertelement <2 x i32> undef, i32 %y, i32 0
+  %1 = insertelement <2 x i32> %0, i32 %z, i32 1
+  %2= urem <2 x i32> %1, <i32 255, i32 255>
+  %3 = uitofp <2 x i32> %2to <2 x float>
+  %4 = shufflevector <2 x float> %3, <2 x float> undef, <3 x i32> <i32 0, i32 1, i32 undef>
+  %5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
+  %6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
+  ret <3 x float> %6
+}
+
+define <3 x float> @urem1(<3 x float> %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @urem1(
+; CHECK-NEXT:  .entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
+; CHECK-NEXT:    ret <3 x float> [[TMP1]]
+;
+.entry:
+  %0 = insertelement <2 x i32> undef, i32 %y, i32 0
+  %1 = insertelement <2 x i32> %0, i32 %z, i32 1
+  %2= urem <2 x i32> %1, <i32 255, i32 255>
+  %3 = uitofp <2 x i32> %2to <2 x float>
+  %4 = shufflevector <2 x float> %3, <2 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
+  %6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
+  ret <3 x float> %6
+}
+
+define <3 x float> @urem2(<3 x float> %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @urem2(
+; CHECK-NEXT:  .entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
+; CHECK-NEXT:    ret <3 x float> [[TMP1]]
+;
+.entry:
+  %0 = insertelement <2 x i32> undef, i32 %y, i32 0
+  %1 = insertelement <2 x i32> %0, i32 %z, i32 1
+  %2= urem <2 x i32> %1, <i32 255, i32 255>
+  %3 = uitofp <2 x i32> %2to <2 x float>
+  %4 = shufflevector <2 x float> undef, <2 x float> %3, <3 x i32> <i32 2, i32 3, i32 undef>
+  %5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
+  %6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
+  ret <3 x float> %6
+}
+
+define <3 x float> @srem0(<3 x float> %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @srem0(
+; CHECK-NEXT:  .entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
+; CHECK-NEXT:    ret <3 x float> [[TMP1]]
+;
+.entry:
+  %0 = insertelement <2 x i32> undef, i32 %y, i32 0
+  %1 = insertelement <2 x i32> %0, i32 %z, i32 1
+  %2 = srem <2 x i32> %1, <i32 255, i32 255>
+  %3 = sitofp <2 x i32> %2 to <2 x float>
+  %4 = shufflevector <2 x float> %3, <2 x float> undef, <3 x i32> <i32 0, i32 1, i32 undef>
+  %5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
+  %6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
+  ret <3 x float> %6
+}
+
+define <3 x float> @srem1(<3 x float> %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @srem1(
+; CHECK-NEXT:  .entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
+; CHECK-NEXT:    ret <3 x float> [[TMP1]]
+;
+.entry:
+  %0 = insertelement <2 x i32> undef, i32 %y, i32 0
+  %1 = insertelement <2 x i32> %0, i32 %z, i32 1
+  %2 = srem <2 x i32> %1, <i32 255, i32 255>
+  %3 = sitofp <2 x i32> %2 to <2 x float>
+  %4 = shufflevector <2 x float> %3, <2 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
+  %6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
+  ret <3 x float> %6
+}
+
+define <3 x float> @srem2(<3 x float> %x, i32 %y, i32 %z) {
+; CHECK-LABEL: @srem2(
+; CHECK-NEXT:  .entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float 0.000000e+00, float 0.000000e+00, float undef>, <3 x i32> <i32 0, i32 3, i32 4>
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul reassoc nnan arcp contract <3 x float> [[TMP0]], [[X]]
+; CHECK-NEXT:    ret <3 x float> [[TMP1]]
+;
+.entry:
+  %0 = insertelement <2 x i32> undef, i32 %y, i32 0
+  %1 = insertelement <2 x i32> %0, i32 %z, i32 1
+  %2 = srem <2 x i32> %1, <i32 255, i32 255>
+  %3 = sitofp <2 x i32> %2 to <2 x float>
+  %4 = shufflevector <2 x float> undef, <2 x float> %3, <3 x i32> <i32 2, i32 3, i32 undef>
+  %5 = shufflevector <3 x float> %x, <3 x float> %4, <3 x i32> <i32 0, i32 3, i32 4>
+  %6 = fmul reassoc nnan arcp contract <3 x float> %x, %5
+  ret <3 x float> %6
+}