Index: lib/Target/AMDGPU/VOP3PInstructions.td =================================================================== --- lib/Target/AMDGPU/VOP3PInstructions.td +++ lib/Target/AMDGPU/VOP3PInstructions.td @@ -165,34 +165,40 @@ defm : MadFmaMixPats; } -class Srl : PatFrag<(ops node:$src), - (srl node:$src, (i32 N))>; +// Defines patterns that extract signed 4bit from each Idx[0]. +foreach Idx = [[0,28],[4,24],[8,20],[12,16],[16,12],[20,8],[24,4]] in + def ExtractSigned4bit_#Idx[0] : PatFrag<(ops node:$src), + (sra (shl node:$src, (i32 Idx[1])), (i32 28))>; -foreach Bits = 1-7 in - def srl#!shl(Bits, 2) : Srl; - -class Extract_U : PatFrag< +// Defines code pattern that extracts U(unsigned/signed) 4/8bit from FromBitIndex. +class Extract: PatFrag< (ops node:$src), - !if (!or (!and (!eq (BitMask, 255), !eq (FromBitIndex, 24)), - !and (!eq (BitMask, 15), !eq (FromBitIndex, 28))), // last element - (!cast("srl"#FromBitIndex) node:$src), + !if (!or (!and (!eq (BitMask, 255), !eq (FromBitIndex, 24)), !eq (FromBitIndex, 28)), // last element + !if (U, (srl node:$src, (i32 FromBitIndex)), (sra node:$src, (i32 FromBitIndex))), !if (!eq (FromBitIndex, 0), // first element - (and node:$src, (i32 BitMask)), - (and (!cast("srl"#FromBitIndex) node:$src), (i32 BitMask))))>; - -foreach Index = 0-3 in { - // Defines patterns that extract each Index'ed 8bit from an unsigned - // 32bit scalar value; - def U#Index#"_8bit" : Extract_U; - - // Defines multiplication patterns where the multiplication is happening on each - // Index'ed 8bit of a 32bit scalar value. - def MulU_Elt#Index : PatFrag< - (ops node:$src0, node:$src1), - (AMDGPUmul_u24_oneuse (!cast("U"#Index#"_8bit") node:$src0), - (!cast("U"#Index#"_8bit") node:$src1))>; -} + !if (U, (and node:$src, (i32 BitMask)), + !if (!eq (BitMask, 15), (!cast("ExtractSigned4bit_"#FromBitIndex) node:$src), + (sext_inreg node:$src, i8))), + !if (U, (and (srl node:$src, (i32 FromBitIndex)), (i32 BitMask)), + !if (!eq (BitMask, 15), (!cast("ExtractSigned4bit_"#FromBitIndex) node:$src), + (sext_inreg (srl node:$src, (i32 FromBitIndex)), i8)))))>; + + +foreach Type = ["I", "U"] in + foreach Index = 0-3 in { + // Defines patterns that extract each Index'ed 8bit from an unsigned + // 32bit scalar value; + def #Type#Index#"_8bit" : Extract; + + // Defines multiplication patterns where the multiplication is happening on each + // Index'ed 8bit of a 32bit scalar value. + + def Mul#Type#_Elt#Index : PatFrag< + (ops node:$src0, node:$src1), + (!cast(!if (!eq (Type, "I"), AMDGPUmul_i24_oneuse, AMDGPUmul_u24_oneuse)) + (!cast(#Type#Index#"_8bit") node:$src0), + (!cast(#Type#Index#"_8bit") node:$src1))>; + } // Different variants of dot8 patterns cause a huge increase in the compile time. // Define non-associative/commutative add/mul to prevent permutation in the dot8 @@ -203,19 +209,23 @@ def NonACAMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24" , SDTIntBinOp>; def NonACAMDGPUmul_u24_oneuse : HasOneUseBinOp; -foreach Index = 0-7 in { - // Defines patterns that extract each Index'ed 4bit from an unsigned - // 32bit scalar value; - def U#Index#"_4bit" : Extract_U; - - // Defines multiplication patterns where the multiplication is happening on each - // Index'ed 8bit of a 32bit scalar value. - def MulU#Index#"_4bit" : PatFrag< - (ops node:$src0, node:$src1), - (NonACAMDGPUmul_u24_oneuse (!cast("U"#Index#"_4bit") node:$src0), - (!cast("U"#Index#"_4bit") node:$src1))>; -} +def NonACAMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24" , SDTIntBinOp>; +def NonACAMDGPUmul_i24_oneuse : HasOneUseBinOp; + +foreach Type = ["I", "U"] in + foreach Index = 0-7 in { + // Defines patterns that extract each Index'ed 4bit from an unsigned + // 32bit scalar value; + def #Type#Index#"_4bit" : Extract; + + // Defines multiplication patterns where the multiplication is happening on each + // Index'ed 8bit of a 32bit scalar value. + def Mul#Type#Index#"_4bit" : PatFrag< + (ops node:$src0, node:$src1), + (!cast(!if (!eq (Type, "I"), NonACAMDGPUmul_i24_oneuse, NonACAMDGPUmul_u24_oneuse)) + (!cast(#Type#Index#"_4bit") node:$src0), + (!cast(#Type#Index#"_4bit") node:$src1))>; + } class UDot2Pat : GCNPat < (add (add_oneuse (AMDGPUmul_u24_oneuse (srl i32:$src0, (i32 16)), @@ -264,17 +274,18 @@ def : UDot2Pat; def : SDot2Pat; -def : GCNPat < - !cast(!foldl((i32 i32:$src2), [0, 1, 2, 3], lhs, y, - (add_oneuse lhs, (!cast("MulU_Elt"#y) i32:$src0, i32:$src1)))), - (V_DOT4_U32_U8 (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0)) ->; +foreach Type = ["U", "I"] in + def : GCNPat < + !cast(!foldl((i32 i32:$src2), [0, 1, 2, 3], lhs, y, + (add_oneuse lhs, (!cast("Mul"#Type#"_Elt"#y) i32:$src0, i32:$src1)))), + (!cast("V_DOT4_"#Type#"32_"#Type#8) (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))>; -def : GCNPat < - !cast(!foldl((add_oneuse i32:$src2, (MulU0_4bit i32:$src0, i32:$src1)), [1, 2, 3, 4, 5, 6, 7], lhs, y, - (NonACAdd_oneuse lhs, (!cast("MulU"#y#"_4bit") i32:$src0, i32:$src1)))), - (V_DOT8_U32_U4 (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0)) ->; +foreach Type = ["U", "I"] in + def : GCNPat < + !cast(!foldl((add_oneuse i32:$src2, (!cast("Mul"#Type#"0_4bit") i32:$src0, i32:$src1)), + [1, 2, 3, 4, 5, 6, 7], lhs, y, + (NonACAdd_oneuse lhs, (!cast("Mul"#Type#y#"_4bit") i32:$src0, i32:$src1)))), + (!cast("V_DOT8_"#Type#"32_"#Type#4) (i32 8), $src0, (i32 8), $src1, (i32 8), $src2, (i1 0))>; } // End SubtargetPredicate = HasDLInsts Index: test/CodeGen/AMDGPU/idot4.ll =================================================================== --- test/CodeGen/AMDGPU/idot4.ll +++ test/CodeGen/AMDGPU/idot4.ll @@ -1,56 +1,122 @@ -; RUN: llc -mtriple=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX789 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX789 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX789 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-DL %s - -; GCN-LABEL: {{^}}udot4_acc32: -; GCN: ; %bb.0: ; %entry -; GCN-NEXT: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}} -; GCN-NEXT: s_load_dwordx2 s{{\[}}[[SRC2_LO:[0-9]+]]:[[SRC2_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xd|0x34}} - -; GFX789-NEXT: s_movk_i32 s{{[0-9]+}}, 0xff -; GFX789: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0 -; GFX789-NEXT: s_load_dword [[S1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x0 -; GFX789-NEXT: s_load_dword [[S2:s[0-9]+]], s{{\[}}[[SRC2_LO]]:[[SRC2_HI]]{{\]}}, 0x0 -; GFX789-NEXT: s_waitcnt lgkmcnt(0) -; GFX789-NEXT: s_and_b32 [[V1E1:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}} -; GFX789-NEXT: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} -; GFX789-NEXT: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80008 -; GFX789-NEXT: v_mov_b32_e32 [[V2E1:v[0-9]+]], s{{[0-9]+}} -; GFX789-NEXT: v_mov_b32_e32 [[SRC2:v[0-9]+]], s{{[0-9]+}} -; GFX789-NEXT: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80010 -; GFX789-NEXT: v_mad_u32_u24 [[MAD1:v[0-9]+]], [[V1E1]], [[V2E1]], [[SRC2]] - -; GFX789-NEXT: s_bfe_u32 [[V1E2:s[0-9]+]], s{{[0-9]+}}, 0x80008 -; GFX789-NEXT: v_mov_b32_e32 [[V2E2:v[0-9]+]], s{{[0-9]+}} -; GFX789-NEXT: s_bfe_u32 [[V1E3:s[0-9]+]], s{{[0-9]+}}, 0x80010 -; GFX789-NEXT: v_mad_u32_u24 [[MAD2:v[0-9]+]], [[V1E2]], [[V2E2]], [[MAD1]] - -; GFX789-NEXT: v_mov_b32_e32 [[V2E3:v[0-9]+]], s{{[0-9]+}} -; GFX789-NEXT: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 24 -; GFX789-NEXT: v_mad_u32_u24 [[MAD3:v[0-9]+]], [[V1E3]], [[V2E3]], [[MAD2]] - -; GFX789-NEXT: s_lshr_b32 [[V1E4:s[0-9]+]], s{{[0-9]+}}, 24 -; GFX789-NEXT: v_mov_b32_e32 [[V2E4:v[0-9]+]], s{{[0-9]+}} -; GFX789-NEXT: v_mad_u32_u24 [[RES:v[0-9]+]], [[V1E4]], [[V2E4]], [[MAD3]] -; GFX789: {{buffer|flat|global}}_store_dword -; GFX789-NEXT: s_endpgm - -; GCN-DL: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: s_load_dword [[SRC0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x0 -; GCN-DL-NEXT: s_load_dword [[S1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x0 -; GCN-DL-NEXT: s_load_dword [[S2:s[0-9]+]], s{{\[}}[[SRC2_LO]]:[[SRC2_HI]]{{\]}}, 0x0 -; GCN-DL-NEXT: v_mov_b32_e32 v[[STLO:[0-9]+]], s[[SRC2_LO]] -; GCN-DL-NEXT: v_mov_b32_e32 v[[STHI:[0-9]+]], s[[SRC2_HI]] -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: v_mov_b32_e32 [[SRC1:v[0-9]+]], [[S1]] -; GCN-DL-NEXT: v_mov_b32_e32 [[SRC2:v[0-9]+]], [[S2]] -; GCN-DL-NEXT: v_dot4_u32_u8 [[DOT:v[0-9]+]], [[SRC0]], [[SRC1]], [[SRC2]] -; GCN-DL-NEXT: global_store_dword v{{\[}}[[STLO]]:[[STHI]]{{\]}}, [[DOT]], off -; GCN-DL-NEXT: s_endpgm - +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX7 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8 %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9-NODL %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9-DL %s define amdgpu_kernel void @udot4_acc32(<4 x i8> addrspace(1)* %src1, +; GFX7-LABEL: udot4_acc32: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_movk_i32 s8, 0xff +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 +; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0 +; GFX7-NEXT: s_load_dword s6, s[0:1], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_and_b32 s7, s4, s8 +; GFX7-NEXT: s_and_b32 s8, s5, s8 +; GFX7-NEXT: s_bfe_u32 s10, s5, 0x80008 +; GFX7-NEXT: v_mov_b32_e32 v0, s8 +; GFX7-NEXT: v_mov_b32_e32 v1, s6 +; GFX7-NEXT: s_bfe_u32 s12, s5, 0x80010 +; GFX7-NEXT: v_mad_u32_u24 v0, s7, v0, v1 +; GFX7-NEXT: s_bfe_u32 s9, s4, 0x80008 +; GFX7-NEXT: v_mov_b32_e32 v1, s10 +; GFX7-NEXT: s_bfe_u32 s11, s4, 0x80010 +; GFX7-NEXT: v_mad_u32_u24 v0, s9, v1, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, s12 +; GFX7-NEXT: s_lshr_b32 s5, s5, 24 +; GFX7-NEXT: v_mad_u32_u24 v0, s11, v1, v0 +; GFX7-NEXT: s_lshr_b32 s4, s4, 24 +; GFX7-NEXT: v_mov_b32_e32 v1, s5 +; GFX7-NEXT: v_mad_u32_u24 v0, s4, v1, v0 +; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: udot4_acc32: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_movk_i32 s2, 0xff +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_load_dword s3, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX8-NEXT: s_load_dword s5, s[0:1], 0x0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_and_b32 s6, s3, s2 +; GFX8-NEXT: s_and_b32 s2, s4, s2 +; GFX8-NEXT: s_bfe_u32 s8, s4, 0x80008 +; GFX8-NEXT: v_mov_b32_e32 v0, s2 +; GFX8-NEXT: v_mov_b32_e32 v1, s5 +; GFX8-NEXT: s_bfe_u32 s10, s4, 0x80010 +; GFX8-NEXT: v_mad_u32_u24 v0, s6, v0, v1 +; GFX8-NEXT: s_bfe_u32 s7, s3, 0x80008 +; GFX8-NEXT: v_mov_b32_e32 v1, s8 +; GFX8-NEXT: s_bfe_u32 s9, s3, 0x80010 +; GFX8-NEXT: v_mad_u32_u24 v0, s7, v1, v0 +; GFX8-NEXT: v_mov_b32_e32 v1, s10 +; GFX8-NEXT: s_lshr_b32 s4, s4, 24 +; GFX8-NEXT: v_mad_u32_u24 v0, s9, v1, v0 +; GFX8-NEXT: s_lshr_b32 s3, s3, 24 +; GFX8-NEXT: v_mov_b32_e32 v1, s4 +; GFX8-NEXT: v_mad_u32_u24 v2, s3, v1, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: udot4_acc32: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NODL-NEXT: s_movk_i32 s2, 0xff +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_load_dword s3, s[4:5], 0x0 +; GFX9-NODL-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-NODL-NEXT: s_load_dword s5, s[0:1], 0x0 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_and_b32 s6, s3, s2 +; GFX9-NODL-NEXT: s_and_b32 s2, s4, s2 +; GFX9-NODL-NEXT: s_bfe_u32 s8, s4, 0x80008 +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-NODL-NEXT: s_bfe_u32 s10, s4, 0x80010 +; GFX9-NODL-NEXT: v_mad_u32_u24 v0, s6, v0, v1 +; GFX9-NODL-NEXT: s_bfe_u32 s7, s3, 0x80008 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s8 +; GFX9-NODL-NEXT: s_bfe_u32 s9, s3, 0x80010 +; GFX9-NODL-NEXT: v_mad_u32_u24 v0, s7, v1, v0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s10 +; GFX9-NODL-NEXT: s_lshr_b32 s4, s4, 24 +; GFX9-NODL-NEXT: v_mad_u32_u24 v0, s9, v1, v0 +; GFX9-NODL-NEXT: s_lshr_b32 s3, s3, 24 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s3, v1, v0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NODL-NEXT: global_store_dword v[0:1], v2, off +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: udot4_acc32: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s3, s[6:7], 0x0 +; GFX9-DL-NEXT: s_load_dword s4, s[0:1], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: v_mov_b32_e32 v2, s3 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s4 +; GFX9-DL-NEXT: v_dot4_u32_u8 v2, s2, v2, v3 +; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm <4 x i8> addrspace(1)* %src2, i32 addrspace(1)* nocapture %dst) { entry: @@ -92,44 +158,118 @@ } define amdgpu_kernel void @udot4_acc16(<4 x i8> addrspace(1)* %src1, -; GCN-LABEL: udot4_acc16: -; GCN: ; %bb.0: ; %entry -; GCN-NEXT: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}} -; GCN-NEXT: s_load_dwordx2 s{{\[}}[[SRC2_LO:[0-9]+]]:[[SRC2_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xd|0x34}} - -; GFX789: {{buffer|flat|global}}_load_ushort [[SRC2:v[0-9]+]] -; GFX789: s_load_dword -; GFX789: s_waitcnt lgkmcnt(0) -; GFX789: s_and_b32 -; GFX789: s_bfe_u32 [[V1E2:s[0-9]+]], s{{[0-9]+}}, 0x80008 -; GFX789: s_bfe_u32 -; GFX789: s_bfe_u32 -; GFX789-NEXT: v_mov_b32_e32 [[V2E2:v[0-9]+]], s{{[0-9]+}} -; GFX789-NEXT: s_bfe_u32 [[V1E3:s[0-9]+]], s{{[0-9]+}}, 0x80010 -; GFX789-NEXT: s_lshr_b32 [[V1E4:s[0-9]+]], s{{[0-9]+}}, 24 -; GFX789-NEXT: v_mov_b32_e32 [[V2E3:v[0-9]+]] -; GFX789-NEXT: s_lshr_b32 [[V1E4:s[0-9]+]], s{{[0-9]+}}, 24 -; GFX789-NEXT: s_waitcnt vmcnt(0) -; GFX789-NEXT: v_mad_u32_u24 [[MAD1:v[0-9]+]], {{s[0-9]+}}, {{v[0-9]+}}, [[SRC2]] -; GFX789-NEXT: v_mad_u32_u24 [[MAD2:v[0-9]+]], {{s[0-9]+}}, [[V2E2]], [[MAD1]] -; GFX789-NEXT: v_mad_u32_u24 [[MAD3:v[0-9]+]], [[V1E3]], [[V2E3]], [[MAD2]] -; GFX789-NEXT: v_mov_b32_e32 [[V2E4:v[0-9]+]], s{{[0-9]+}} -; GFX789-NEXT: v_mad_u32_u24 [[MAD4:v[0-9]+]], [[V1E4]], [[V2E4]], [[MAD3]] -; GFX789-NEXT: {{buffer|flat|global}}_store_short -; GFX789-NEXT: s_endpgm - -; GCN-DL: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: s_load_dword [[SRC0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x0 -; GCN-DL-NEXT: s_load_dword [[S1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x0 -; GCN-DL-NEXT: v_mov_b32_e32 v[[STLO:[0-9]+]], s[[SRC2_LO]] -; GCN-DL-NEXT: v_mov_b32_e32 v[[STHI:[0-9]+]], s[[SRC2_HI]] -; GCN-DL-NEXT: global_load_ushort [[SRC2:v[0-9]+]], v{{\[}}[[STLO]]:[[STHI]]{{\]}}, off -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: v_mov_b32_e32 [[SRC1:v[0-9]+]], [[S1]] -; GCN-DL-NEXT: s_waitcnt vmcnt(0) -; GCN-DL-NEXT: v_dot4_u32_u8 [[DOT:v[0-9]+]], [[SRC0]], [[SRC1]], [[SRC2]] -; GCN-DL-NEXT: global_store_short v{{\[}}[[STLO]]:[[STHI]]{{\]}}, [[DOT]], off -; GCN-DL-NEXT: s_endpgm +; GFX7-LABEL: udot4_acc16: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_movk_i32 s8, 0xff +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 +; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0 +; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_and_b32 s7, s4, s8 +; GFX7-NEXT: s_bfe_u32 s9, s4, 0x80008 +; GFX7-NEXT: s_and_b32 s6, s5, s8 +; GFX7-NEXT: s_bfe_u32 s8, s5, 0x80008 +; GFX7-NEXT: v_mov_b32_e32 v1, s6 +; GFX7-NEXT: s_bfe_u32 s10, s5, 0x80010 +; GFX7-NEXT: v_mov_b32_e32 v2, s8 +; GFX7-NEXT: s_bfe_u32 s11, s4, 0x80010 +; GFX7-NEXT: s_lshr_b32 s5, s5, 24 +; GFX7-NEXT: v_mov_b32_e32 v3, s10 +; GFX7-NEXT: s_lshr_b32 s4, s4, 24 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_mad_u32_u24 v0, s7, v1, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s9, v2, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s11, v3, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, s5 +; GFX7-NEXT: v_mad_u32_u24 v0, s4, v1, v0 +; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: udot4_acc16: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ushort v2, v[0:1] +; GFX8-NEXT: s_load_dword s1, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s2, s[6:7], 0x0 +; GFX8-NEXT: s_movk_i32 s0, 0xff +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_and_b32 s3, s1, s0 +; GFX8-NEXT: s_and_b32 s0, s2, s0 +; GFX8-NEXT: s_bfe_u32 s5, s2, 0x80008 +; GFX8-NEXT: v_mov_b32_e32 v3, s0 +; GFX8-NEXT: s_bfe_u32 s7, s2, 0x80010 +; GFX8-NEXT: s_bfe_u32 s4, s1, 0x80008 +; GFX8-NEXT: v_mov_b32_e32 v4, s5 +; GFX8-NEXT: s_bfe_u32 s6, s1, 0x80010 +; GFX8-NEXT: s_lshr_b32 s2, s2, 24 +; GFX8-NEXT: v_mov_b32_e32 v5, s7 +; GFX8-NEXT: s_lshr_b32 s1, s1, 24 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_mad_u32_u24 v2, s3, v3, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, s4, v4, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, s6, v5, v2 +; GFX8-NEXT: v_mov_b32_e32 v3, s2 +; GFX8-NEXT: v_mad_u32_u24 v2, s1, v3, v2 +; GFX8-NEXT: flat_store_short v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: udot4_acc16: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NODL-NEXT: global_load_ushort v2, v[0:1], off +; GFX9-NODL-NEXT: s_load_dword s1, s[4:5], 0x0 +; GFX9-NODL-NEXT: s_load_dword s2, s[6:7], 0x0 +; GFX9-NODL-NEXT: s_movk_i32 s0, 0xff +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_and_b32 s3, s1, s0 +; GFX9-NODL-NEXT: s_and_b32 s0, s2, s0 +; GFX9-NODL-NEXT: s_bfe_u32 s5, s2, 0x80008 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NODL-NEXT: s_bfe_u32 s7, s2, 0x80010 +; GFX9-NODL-NEXT: s_bfe_u32 s4, s1, 0x80008 +; GFX9-NODL-NEXT: v_mov_b32_e32 v4, s5 +; GFX9-NODL-NEXT: s_bfe_u32 s6, s1, 0x80010 +; GFX9-NODL-NEXT: s_lshr_b32 s2, s2, 24 +; GFX9-NODL-NEXT: v_mov_b32_e32 v5, s7 +; GFX9-NODL-NEXT: s_lshr_b32 s1, s1, 24 +; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s3, v3, v2 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s4, v4, v2 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s6, v5, v2 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s2 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s1, v3, v2 +; GFX9-NODL-NEXT: global_store_short v[0:1], v2, off +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: udot4_acc16: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s3, s[6:7], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_load_ushort v2, v[0:1], off +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s3 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_dot4_u32_u8 v2, s2, v3, v2 +; GFX9-DL-NEXT: global_store_short v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm <4 x i8> addrspace(1)* %src2, i16 addrspace(1)* nocapture %dst) { entry: @@ -171,46 +311,118 @@ } define amdgpu_kernel void @udot4_acc8(<4 x i8> addrspace(1)* %src1, -; GCN-LABEL: udot4_acc8: -; GCN: ; %bb.0: ; %entry -; GCN-NEXT: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}} -; GCN-NEXT: s_load_dwordx2 s{{\[}}[[SRC2_LO:[0-9]+]]:[[SRC2_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xd|0x34}} -; GFX789: s_movk_i32 s{{[0-9]+}}, 0xff -; GFX789: s_waitcnt lgkmcnt(0) -; GFX789: {{buffer|flat|global}}_load_ubyte [[SRC2:v[0-9]+]] -; GFX789: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}} -; GFX789: s_waitcnt lgkmcnt(0) -; GFX789: s_bfe_u32 [[V1E2:s[0-9]+]], s{{[0-9]+}}, 0x80008 -; GFX789: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} -; GFX789: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80008 -; GFX789: v_mov_b32_e32 [[V2E1:v[0-9]+]] -; GFX789: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80010 -; GFX789-NEXT: v_mov_b32_e32 [[V2E2:v[0-9]+]] -; GFX789-NEXT: s_bfe_u32 [[V1E3:s[0-9]+]], s{{[0-9]+}}, 0x80010 -; GFX789-NEXT: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 24 -; GFX789-NEXT: v_mov_b32_e32 [[V2E3:v[0-9]+]] -; GFX789-NEXT: s_lshr_b32 [[V1E4:s[0-9]+]], s{{[0-9]+}}, 24 -; GFX789-NEXT: s_waitcnt vmcnt(0) -; GFX789-NEXT: v_mad_u32_u24 [[MAD1:v[0-9]+]], s{{[0-9]+}}, [[V2E1]], [[SRC2]] -; GFX789-NEXT: v_mad_u32_u24 [[MAD2:v[0-9]+]], [[V1E2]], [[V2E2]], [[MAD1]] -; GFX789-NEXT: v_mad_u32_u24 [[MAD3:v[0-9]+]], [[V1E3]], [[V2E3]], [[MAD2]] -; GFX789-NEXT: v_mov_b32_e32 [[V2E4:v[0-9]+]] -; GFX789-NEXT: v_mad_u32_u24 [[MAD4:v[0-9]+]], [[V1E4]], [[V2E4]], [[MAD3]] -; GFX789-NEXT: {{buffer|flat|global}}_store_byte -; GFX789-NEXT: s_endpgm - -; GCN-DL: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: s_load_dword [[SRC0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}} -; GCN-DL-NEXT: s_load_dword [[S1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}} -; GCN-DL-NEXT: v_mov_b32_e32 v[[STLO:[0-9]+]], s[[SRC2_LO]] -; GCN-DL-NEXT: v_mov_b32_e32 v[[STHI:[0-9]+]], s[[SRC2_HI]] -; GCN-DL-NEXT: global_load_ubyte [[SRC2:v[0-9]+]], v{{\[}}[[STLO]]:[[STHI]]{{\]}}, off -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: v_mov_b32_e32 [[SRC1:v[0-9]+]], [[S1]] -; GCN-DL-NEXT: s_waitcnt vmcnt(0) -; GCN-DL-NEXT: v_dot4_u32_u8 [[DOT:v[0-9]+]], [[SRC0]], [[SRC1]], [[SRC2]] -; GCN-DL-NEXT: global_store_byte v{{\[}}[[STLO]]:[[STHI]]{{\]}}, [[DOT]], off -; GCN-DL-NEXT: s_endpgm +; GFX7-LABEL: udot4_acc8: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_movk_i32 s8, 0xff +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 +; GFX7-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 +; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_and_b32 s7, s4, s8 +; GFX7-NEXT: s_bfe_u32 s9, s4, 0x80008 +; GFX7-NEXT: s_and_b32 s6, s5, s8 +; GFX7-NEXT: s_bfe_u32 s8, s5, 0x80008 +; GFX7-NEXT: v_mov_b32_e32 v1, s6 +; GFX7-NEXT: s_bfe_u32 s10, s5, 0x80010 +; GFX7-NEXT: v_mov_b32_e32 v2, s8 +; GFX7-NEXT: s_bfe_u32 s11, s4, 0x80010 +; GFX7-NEXT: s_lshr_b32 s5, s5, 24 +; GFX7-NEXT: v_mov_b32_e32 v3, s10 +; GFX7-NEXT: s_lshr_b32 s4, s4, 24 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_mad_u32_u24 v0, s7, v1, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s9, v2, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s11, v3, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, s5 +; GFX7-NEXT: v_mad_u32_u24 v0, s4, v1, v0 +; GFX7-NEXT: buffer_store_byte v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: udot4_acc8: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_movk_i32 s2, 0xff +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ubyte v2, v[0:1] +; GFX8-NEXT: s_load_dword s0, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s1, s[6:7], 0x0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_bfe_u32 s4, s0, 0x80008 +; GFX8-NEXT: s_and_b32 s3, s1, s2 +; GFX8-NEXT: s_bfe_u32 s5, s1, 0x80008 +; GFX8-NEXT: s_and_b32 s2, s0, s2 +; GFX8-NEXT: v_mov_b32_e32 v3, s3 +; GFX8-NEXT: s_bfe_u32 s6, s1, 0x80010 +; GFX8-NEXT: v_mov_b32_e32 v4, s5 +; GFX8-NEXT: s_bfe_u32 s7, s0, 0x80010 +; GFX8-NEXT: s_lshr_b32 s1, s1, 24 +; GFX8-NEXT: v_mov_b32_e32 v5, s6 +; GFX8-NEXT: s_lshr_b32 s0, s0, 24 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_mad_u32_u24 v2, s2, v3, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, s4, v4, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, s7, v5, v2 +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_mad_u32_u24 v2, s0, v3, v2 +; GFX8-NEXT: flat_store_byte v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: udot4_acc8: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NODL-NEXT: s_movk_i32 s2, 0xff +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NODL-NEXT: global_load_ubyte v2, v[0:1], off +; GFX9-NODL-NEXT: s_load_dword s0, s[4:5], 0x0 +; GFX9-NODL-NEXT: s_load_dword s1, s[6:7], 0x0 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_bfe_u32 s4, s0, 0x80008 +; GFX9-NODL-NEXT: s_and_b32 s3, s1, s2 +; GFX9-NODL-NEXT: s_bfe_u32 s5, s1, 0x80008 +; GFX9-NODL-NEXT: s_and_b32 s2, s0, s2 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s3 +; GFX9-NODL-NEXT: s_bfe_u32 s6, s1, 0x80010 +; GFX9-NODL-NEXT: v_mov_b32_e32 v4, s5 +; GFX9-NODL-NEXT: s_bfe_u32 s7, s0, 0x80010 +; GFX9-NODL-NEXT: s_lshr_b32 s1, s1, 24 +; GFX9-NODL-NEXT: v_mov_b32_e32 v5, s6 +; GFX9-NODL-NEXT: s_lshr_b32 s0, s0, 24 +; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s2, v3, v2 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s4, v4, v2 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s7, v5, v2 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s0, v3, v2 +; GFX9-NODL-NEXT: global_store_byte v[0:1], v2, off +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: udot4_acc8: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s3, s[6:7], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_load_ubyte v2, v[0:1], off +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s3 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_dot4_u32_u8 v2, s2, v3, v2 +; GFX9-DL-NEXT: global_store_byte v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm <4 x i8> addrspace(1)* %src2, i8 addrspace(1)* nocapture %dst) { entry: @@ -245,26 +457,103 @@ ; TODO: Generate udot4? define amdgpu_kernel void @udot2_8(<4 x i8> addrspace(1)* %src1, -; GCN-LABEL: udot2_8: -; GCN-NEXT: ; %bb.0: ; %entry -; GCN-NEXT: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}} -; GCN-NEXT: s_load_dwordx2 s{{\[}}[[SRC2_LO:[0-9]+]]:[[SRC2_HI:[0-9]+]]{{\]}} -; GCN: s_movk_i32 [[FF:s[0-9]+]], 0xff -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN: s_load_dword [[V1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x0 -; GCN: s_load_dword [[V2:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN: s_and_b32 [[V1E1:s[0-9]+]], [[V1]], [[FF]] -; GCN: s_bfe_u32 [[VE2:s[0-9]+]], {{s[0-9]+}}, 0x80008 -; GCN: s_bfe_u32 [[V1E2:s[0-9]+]], {{s[0-9]+}}, 0x80008 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_mad_u32_u24 [[MAD1:v[0-9]+]], [[V1E1]] -; GCN-NEXT: v_mov_b32_e32 [[V2E2:v[0-9]+]] -; GCN-NEXT: v_mad_u32_u24 [[MAD2:v[0-9]+]], {{s[0-9]+}}, [[V2E2]], [[MAD1]] -; GCN-NEXT: {{buffer|flat|global}}_store_byte -; GCN-NEXT: s_endpgm - <4 x i8> addrspace(1)* %src2, - i8 addrspace(1)* nocapture %dst) { +; GFX7-LABEL: udot2_8: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_movk_i32 s8, 0xff +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 +; GFX7-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 +; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_and_b32 s7, s4, s8 +; GFX7-NEXT: s_bfe_u32 s4, s4, 0x80008 +; GFX7-NEXT: s_and_b32 s6, s5, s8 +; GFX7-NEXT: v_mov_b32_e32 v1, s6 +; GFX7-NEXT: s_bfe_u32 s5, s5, 0x80008 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_mad_u32_u24 v0, s7, v1, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, s5 +; GFX7-NEXT: v_mad_u32_u24 v0, s4, v1, v0 +; GFX7-NEXT: buffer_store_byte v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: udot2_8: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_movk_i32 s2, 0xff +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ubyte v2, v[0:1] +; GFX8-NEXT: s_load_dword s0, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s1, s[6:7], 0x0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_and_b32 s3, s1, s2 +; GFX8-NEXT: s_and_b32 s2, s0, s2 +; GFX8-NEXT: v_mov_b32_e32 v3, s3 +; GFX8-NEXT: s_bfe_u32 s1, s1, 0x80008 +; GFX8-NEXT: s_bfe_u32 s0, s0, 0x80008 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_mad_u32_u24 v2, s2, v3, v2 +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_mad_u32_u24 v2, s0, v3, v2 +; GFX8-NEXT: flat_store_byte v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: udot2_8: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NODL-NEXT: s_movk_i32 s2, 0xff +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NODL-NEXT: global_load_ubyte v2, v[0:1], off +; GFX9-NODL-NEXT: s_load_dword s0, s[4:5], 0x0 +; GFX9-NODL-NEXT: s_load_dword s1, s[6:7], 0x0 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_and_b32 s3, s1, s2 +; GFX9-NODL-NEXT: s_and_b32 s2, s0, s2 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s3 +; GFX9-NODL-NEXT: s_bfe_u32 s1, s1, 0x80008 +; GFX9-NODL-NEXT: s_bfe_u32 s0, s0, 0x80008 +; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s2, v3, v2 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s0, v3, v2 +; GFX9-NODL-NEXT: global_store_byte v[0:1], v2, off +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: udot2_8: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_movk_i32 s2, 0xff +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_load_ubyte v2, v[0:1], off +; GFX9-DL-NEXT: s_load_dword s0, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s1, s[6:7], 0x0 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_and_b32 s3, s1, s2 +; GFX9-DL-NEXT: s_and_b32 s2, s0, s2 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s3 +; GFX9-DL-NEXT: s_bfe_u32 s1, s1, 0x80008 +; GFX9-DL-NEXT: s_bfe_u32 s0, s0, 0x80008 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s2, v3, v2 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s0, v3, v2 +; GFX9-DL-NEXT: global_store_byte v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm + <4 x i8> addrspace(1)* %src2, + i8 addrspace(1)* nocapture %dst) { entry: %vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1 %vec2 = load <4 x i8>, <4 x i8> addrspace(1)* %src2 @@ -285,46 +574,120 @@ } define amdgpu_kernel void @udot4_CommutationInsideMAD(<4 x i8> addrspace(1)* %src1, -; GCN-LABEL: udot4_CommutationInsideMAD: -; GCN: ; %bb.0: ; %entry -; GCN-NEXT: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}} -; GCN-NEXT: s_load_dwordx2 s{{\[}}[[SRC2_LO:[0-9]+]]:[[SRC2_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xd|0x34}} -; GFX789: s_waitcnt lgkmcnt(0) -; GFX789: {{buffer|flat|global}}_load_ubyte [[SRC2:v[0-9]+]] -; GFX789: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}} -; GFX789: s_waitcnt lgkmcnt(0) -; GFX789: s_bfe_u32 -; GFX789: s_bfe_u32 -; GFX789-NEXT: s_bfe_u32 [[V1E2:s[0-9]+]], s{{[0-9]+}}, 0x80008 -; GFX789-NEXT: v_mov_b32_e32 [[V2E2:v[0-9]+]] -; GFX789-NEXT: s_bfe_u32 [[V1E3:s[0-9]+]], s{{[0-9]+}}, 0x80010 -; GFX789-NEXT: s_lshr_b32 [[VE4:s[0-9]+]], s{{[0-9]+}}, 24 -; GFX789-NEXT: v_mov_b32_e32 [[V2E3:v[0-9]+]] -; GFX789-NEXT: s_lshr_b32 [[V1E4:s[0-9]+]], s{{[0-9]+}}, 24 -; GFX789-NEXT: s_waitcnt vmcnt(0) - -; GFX789-NEXT: v_mad_u32_u24 [[MAD1:v[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}, [[SRC2]] -; GFX789-NEXT: v_mad_u32_u24 [[MAD2:v[0-9]+]], [[V1E2]], [[V2E2]], [[MAD1]] -; GFX789-NEXT: v_mad_u32_u24 [[MAD3:v[0-9]+]], [[V1E3]], [[V2E3]], [[MAD2]] -; GFX789-NEXT: v_mov_b32_e32 [[V2E4:v[0-9]+]], [[VE4]] -; GFX789-NEXT: v_mad_u32_u24 [[MAD4:v[0-9]+]], [[V1E4]], [[V2E4]], [[MAD3]] -; GFX789-NEXT: {{buffer|flat|global}}_store_byte -; GFX789-NEXT: s_endpgm - -; GCN-DL: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: s_load_dword [[S1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}} -; GCN-DL-NEXT: s_load_dword [[SRC0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}} -; GCN-DL-NEXT: v_mov_b32_e32 v[[STLO:[0-9]+]], s[[SRC2_LO]] -; GCN-DL-NEXT: v_mov_b32_e32 v[[STHI:[0-9]+]], s[[SRC2_HI]] -; GCN-DL-NEXT: global_load_ubyte [[SRC2:v[0-9]+]], v{{\[}}[[STLO]]:[[STHI]]{{\]}}, off -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: v_mov_b32_e32 [[SRC1:v[0-9]+]], [[S1]] -; GCN-DL-NEXT: s_waitcnt vmcnt(0) -; GCN-DL-NEXT: v_dot4_u32_u8 [[DOT:v[0-9]+]], [[SRC0]], [[SRC1]], [[SRC2]] -; GCN-DL-NEXT: global_store_byte v{{\[}}[[STLO]]:[[STHI]]{{\]}}, [[DOT]], off -; GCN-DL-NEXT: s_endpgm - <4 x i8> addrspace(1)* %src2, - i8 addrspace(1)* nocapture %dst) { +; GFX7-LABEL: udot4_CommutationInsideMAD: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_movk_i32 s8, 0xff +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 +; GFX7-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 +; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_and_b32 s6, s4, s8 +; GFX7-NEXT: v_mov_b32_e32 v1, s6 +; GFX7-NEXT: s_and_b32 s7, s5, s8 +; GFX7-NEXT: s_bfe_u32 s8, s4, 0x80008 +; GFX7-NEXT: s_bfe_u32 s10, s4, 0x80010 +; GFX7-NEXT: s_bfe_u32 s9, s5, 0x80008 +; GFX7-NEXT: v_mov_b32_e32 v2, s8 +; GFX7-NEXT: s_bfe_u32 s11, s5, 0x80010 +; GFX7-NEXT: s_lshr_b32 s4, s4, 24 +; GFX7-NEXT: v_mov_b32_e32 v3, s10 +; GFX7-NEXT: s_lshr_b32 s5, s5, 24 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_mad_u32_u24 v0, s7, v1, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s9, v2, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s11, v3, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, s4 +; GFX7-NEXT: v_mad_u32_u24 v0, s5, v1, v0 +; GFX7-NEXT: buffer_store_byte v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: udot4_CommutationInsideMAD: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ubyte v2, v[0:1] +; GFX8-NEXT: s_load_dword s1, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s2, s[6:7], 0x0 +; GFX8-NEXT: s_movk_i32 s0, 0xff +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_and_b32 s3, s1, s0 +; GFX8-NEXT: s_bfe_u32 s5, s1, 0x80008 +; GFX8-NEXT: s_and_b32 s0, s2, s0 +; GFX8-NEXT: v_mov_b32_e32 v3, s3 +; GFX8-NEXT: s_bfe_u32 s6, s1, 0x80010 +; GFX8-NEXT: s_bfe_u32 s4, s2, 0x80008 +; GFX8-NEXT: v_mov_b32_e32 v4, s5 +; GFX8-NEXT: s_bfe_u32 s7, s2, 0x80010 +; GFX8-NEXT: s_lshr_b32 s1, s1, 24 +; GFX8-NEXT: v_mov_b32_e32 v5, s6 +; GFX8-NEXT: s_lshr_b32 s2, s2, 24 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_mad_u32_u24 v2, s0, v3, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, s4, v4, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, s7, v5, v2 +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_mad_u32_u24 v2, s2, v3, v2 +; GFX8-NEXT: flat_store_byte v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: udot4_CommutationInsideMAD: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NODL-NEXT: global_load_ubyte v2, v[0:1], off +; GFX9-NODL-NEXT: s_load_dword s1, s[4:5], 0x0 +; GFX9-NODL-NEXT: s_load_dword s2, s[6:7], 0x0 +; GFX9-NODL-NEXT: s_movk_i32 s0, 0xff +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_and_b32 s3, s1, s0 +; GFX9-NODL-NEXT: s_bfe_u32 s5, s1, 0x80008 +; GFX9-NODL-NEXT: s_and_b32 s0, s2, s0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s3 +; GFX9-NODL-NEXT: s_bfe_u32 s6, s1, 0x80010 +; GFX9-NODL-NEXT: s_bfe_u32 s4, s2, 0x80008 +; GFX9-NODL-NEXT: v_mov_b32_e32 v4, s5 +; GFX9-NODL-NEXT: s_bfe_u32 s7, s2, 0x80010 +; GFX9-NODL-NEXT: s_lshr_b32 s1, s1, 24 +; GFX9-NODL-NEXT: v_mov_b32_e32 v5, s6 +; GFX9-NODL-NEXT: s_lshr_b32 s2, s2, 24 +; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s0, v3, v2 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s4, v4, v2 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s7, v5, v2 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s2, v3, v2 +; GFX9-NODL-NEXT: global_store_byte v[0:1], v2, off +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: udot4_CommutationInsideMAD: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s3, s[6:7], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_load_ubyte v2, v[0:1], off +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s2 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_dot4_u32_u8 v2, s3, v3, v2 +; GFX9-DL-NEXT: global_store_byte v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm + <4 x i8> addrspace(1)* %src2, + i8 addrspace(1)* nocapture %dst) { entry: %vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1 %vec2 = load <4 x i8>, <4 x i8> addrspace(1)* %src2 @@ -357,29 +720,133 @@ ; TODO: Support commutation accross the adds. define amdgpu_kernel void @udot4_CommutationAccrossMADs(<4 x i8> addrspace(1)* %src1, -; GCN-LABEL: udot4_CommutationAccrossMADs: -; GCN: ; %bb.0: ; %entry -; GCN-NEXT: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}} -; GCN-NEXT: s_load_dwordx2 s{{\[}}[[SRC2_LO:[0-9]+]]:[[SRC2_HI:[0-9]+]]{{\]}} -; GCN: s_waitcnt lgkmcnt(0) -; GCN: {{buffer|flat|global}}_load_ubyte [[SRC2:v[0-9]+]] -; GCN: s_load_dword [[V2:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x0 -; GCN: s_waitcnt lgkmcnt(0) -; GCN: s_bfe_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0x80008 -; GCN: s_bfe_u32 {{s[0-9]+}}, {{s[0-9]+}}, 0x80008 -; GCN: v_mov_b32_e32 [[V2E1:v[0-9]+]] -; GCN: s_bfe_u32 [[V1E3:s[0-9]+]], {{s[0-9]+}}, 0x80010 -; GCN: s_lshr_b32 [[VE4:s[0-9]+]], {{s[0-9]+}}, 24 -; GCN-NEXT: v_mov_b32_e32 [[V2E3:v[0-9]+]], {{s[0-9]+}} -; GCN-NEXT: s_lshr_b32 [[V1E4:s[0-9]+]], {{s[0-9]+}}, 24 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_mad_u32_u24 [[MAD1:v[0-9]+]], {{s[0-9]+}}, [[V2E1]], [[SRC2]] -; GCN-NEXT: v_mad_u32_u24 [[MAD2:v[0-9]+]], {{s[0-9]+}}, {{v[0-9]+}}, [[MAD1]] -; GCN-NEXT: v_mad_u32_u24 [[MAD3:v[0-9]+]], {{s[0-9]+}}, {{v[0-9]+}}, [[MAD2]] -; GCN-NEXT: v_mov_b32_e32 [[V2E4:v[0-9]+]], [[VE4]] -; GCN-NEXT: v_mad_u32_u24 [[MAD4:v[0-9]+]], [[V1E4]], [[V2E4]], [[MAD3]] -; GCN-NEXT: {{buffer|flat|global}}_store_byte -; GCN-NEXT: s_endpgm +; GFX7-LABEL: udot4_CommutationAccrossMADs: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_movk_i32 s8, 0xff +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 +; GFX7-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 +; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_and_b32 s6, s4, s8 +; GFX7-NEXT: s_bfe_u32 s10, s4, 0x80010 +; GFX7-NEXT: s_and_b32 s7, s5, s8 +; GFX7-NEXT: s_bfe_u32 s8, s4, 0x80008 +; GFX7-NEXT: s_bfe_u32 s9, s5, 0x80008 +; GFX7-NEXT: v_mov_b32_e32 v1, s8 +; GFX7-NEXT: v_mov_b32_e32 v2, s6 +; GFX7-NEXT: s_bfe_u32 s11, s5, 0x80010 +; GFX7-NEXT: s_lshr_b32 s4, s4, 24 +; GFX7-NEXT: v_mov_b32_e32 v3, s10 +; GFX7-NEXT: s_lshr_b32 s5, s5, 24 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_mad_u32_u24 v0, s9, v1, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s7, v2, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s11, v3, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, s4 +; GFX7-NEXT: v_mad_u32_u24 v0, s5, v1, v0 +; GFX7-NEXT: buffer_store_byte v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: udot4_CommutationAccrossMADs: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ubyte v2, v[0:1] +; GFX8-NEXT: s_load_dword s1, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s2, s[6:7], 0x0 +; GFX8-NEXT: s_movk_i32 s0, 0xff +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_bfe_u32 s4, s1, 0x80008 +; GFX8-NEXT: s_and_b32 s3, s2, s0 +; GFX8-NEXT: s_and_b32 s0, s1, s0 +; GFX8-NEXT: s_bfe_u32 s5, s2, 0x80008 +; GFX8-NEXT: v_mov_b32_e32 v3, s4 +; GFX8-NEXT: s_bfe_u32 s6, s1, 0x80010 +; GFX8-NEXT: v_mov_b32_e32 v4, s0 +; GFX8-NEXT: s_bfe_u32 s7, s2, 0x80010 +; GFX8-NEXT: s_lshr_b32 s1, s1, 24 +; GFX8-NEXT: v_mov_b32_e32 v5, s6 +; GFX8-NEXT: s_lshr_b32 s2, s2, 24 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_mad_u32_u24 v2, s5, v3, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, s3, v4, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, s7, v5, v2 +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_mad_u32_u24 v2, s2, v3, v2 +; GFX8-NEXT: flat_store_byte v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: udot4_CommutationAccrossMADs: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NODL-NEXT: global_load_ubyte v2, v[0:1], off +; GFX9-NODL-NEXT: s_load_dword s1, s[4:5], 0x0 +; GFX9-NODL-NEXT: s_load_dword s2, s[6:7], 0x0 +; GFX9-NODL-NEXT: s_movk_i32 s0, 0xff +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_bfe_u32 s4, s1, 0x80008 +; GFX9-NODL-NEXT: s_and_b32 s3, s2, s0 +; GFX9-NODL-NEXT: s_and_b32 s0, s1, s0 +; GFX9-NODL-NEXT: s_bfe_u32 s5, s2, 0x80008 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s4 +; GFX9-NODL-NEXT: s_bfe_u32 s6, s1, 0x80010 +; GFX9-NODL-NEXT: v_mov_b32_e32 v4, s0 +; GFX9-NODL-NEXT: s_bfe_u32 s7, s2, 0x80010 +; GFX9-NODL-NEXT: s_lshr_b32 s1, s1, 24 +; GFX9-NODL-NEXT: v_mov_b32_e32 v5, s6 +; GFX9-NODL-NEXT: s_lshr_b32 s2, s2, 24 +; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s5, v3, v2 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s3, v4, v2 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s7, v5, v2 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s2, v3, v2 +; GFX9-NODL-NEXT: global_store_byte v[0:1], v2, off +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: udot4_CommutationAccrossMADs: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_load_ubyte v2, v[0:1], off +; GFX9-DL-NEXT: s_load_dword s1, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s2, s[6:7], 0x0 +; GFX9-DL-NEXT: s_movk_i32 s0, 0xff +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_bfe_u32 s4, s1, 0x80008 +; GFX9-DL-NEXT: s_and_b32 s3, s2, s0 +; GFX9-DL-NEXT: s_and_b32 s0, s1, s0 +; GFX9-DL-NEXT: s_bfe_u32 s5, s2, 0x80008 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s4 +; GFX9-DL-NEXT: s_bfe_u32 s6, s1, 0x80010 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s0 +; GFX9-DL-NEXT: s_bfe_u32 s7, s2, 0x80010 +; GFX9-DL-NEXT: s_lshr_b32 s1, s1, 24 +; GFX9-DL-NEXT: v_mov_b32_e32 v5, s6 +; GFX9-DL-NEXT: s_lshr_b32 s2, s2, 24 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s5, v3, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s3, v4, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s7, v5, v2 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s2, v3, v2 +; GFX9-DL-NEXT: global_store_byte v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm <4 x i8> addrspace(1)* %src2, i8 addrspace(1)* nocapture %dst) { entry: @@ -413,37 +880,137 @@ } define amdgpu_kernel void @udot4_multiuse_mul1(<4 x i8> addrspace(1)* %src1, -; GCN-LABEL: udot4_multiuse_mul1: -; GCN: ; %bb.0: ; %entry -; GCN-NEXT: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}} -; GCN-NEXT: s_load_dwordx2 s{{\[}}[[SRC2_LO:[0-9]+]]:[[SRC2_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xd|0x34}} -; GCN-NEXT: s_movk_i32 [[FF:s[0-9]+]], 0xff -; GCN: s_load_dword [[S0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x0 -; GCN-NEXT: s_load_dword [[S1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x0 -; GCN-NEXT: s_load_dword [[S2:s[0-9]+]], s{{\[}}[[SRC2_LO]]:[[SRC2_HI]]{{\]}}, 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_and_b32 [[V1E1:s[0-9]+]], [[S0]], [[FF]] -; GCN-NEXT: s_and_b32 [[SV2E1:s[0-9]+]], [[S1]], [[FF]] -; GCN-NEXT: s_bfe_u32 [[SV2E2:s[0-9]+]], [[S1]], 0x80008 -; GCN-NEXT: v_mov_b32_e32 [[V2E1:v[0-9]+]], [[SV2E1]] -; GCN-NEXT: v_mov_b32_e32 [[SRC2:v[0-9]+]], [[S2]] -; GCN-NEXT: s_bfe_u32 [[V1E2:s[0-9]+]], [[S0]], 0x80008 -; GCN-NEXT: v_mad_u32_u24 [[MAD1:v[0-9]+]], [[V1E1]], [[V2E1]], [[SRC2]] -; GCN-NEXT: v_mov_b32_e32 [[V2E2:v[0-9]+]], [[SV2E2]] -; GCN-NEXT: s_bfe_u32 [[VE4:s[0-9]+]], [[S1]], 0x80010 -; GCN-NEXT: v_mad_u32_u24 [[MAD2:v[0-9]+]], [[V1E2]], [[V2E2]], [[MAD1]] -; GCN-NEXT: s_bfe_u32 [[V1E3:s[0-9]+]], [[S0]], 0x80010 -; GCN-NEXT: v_mad_u32_u24 [[MAD3:v[0-9]+]], [[V1E1]], [[V2E1]], [[MAD2]] -; GCN-NEXT: v_mov_b32_e32 [[V2E3:v[0-9]+]], [[VE4]] -; GCN-NEXT: s_lshr_b32 [[VE4:s[0-9]+]], [[S1]], 24 -; GCN-NEXT: v_mad_u32_u24 [[MAD4:v[0-9]+]], [[V1E3]], [[V2E3]], [[MAD3]] -; GCN-NEXT: s_lshr_b32 [[V1E4:s[0-9]+]], [[S0]], 24 -; GCN-NEXT: v_mov_b32_e32 [[V2E4:v[0-9]+]] -; GCN-NEXT: v_mad_u32_u24 [[MAD5:v[0-9]+]], [[V1E4]], [[V2E4]], [[MAD4]] -; GCN: {{buffer|flat|global}}_store_dword -; GCN-NEXT: s_endpgm - - +; GFX7-LABEL: udot4_multiuse_mul1: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_movk_i32 s8, 0xff +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 +; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0 +; GFX7-NEXT: s_load_dword s6, s[0:1], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_and_b32 s7, s4, s8 +; GFX7-NEXT: s_and_b32 s8, s5, s8 +; GFX7-NEXT: s_bfe_u32 s10, s5, 0x80008 +; GFX7-NEXT: v_mov_b32_e32 v0, s8 +; GFX7-NEXT: v_mov_b32_e32 v1, s6 +; GFX7-NEXT: s_bfe_u32 s9, s4, 0x80008 +; GFX7-NEXT: v_mad_u32_u24 v1, s7, v0, v1 +; GFX7-NEXT: v_mov_b32_e32 v2, s10 +; GFX7-NEXT: s_bfe_u32 s12, s5, 0x80010 +; GFX7-NEXT: v_mad_u32_u24 v1, s9, v2, v1 +; GFX7-NEXT: s_bfe_u32 s11, s4, 0x80010 +; GFX7-NEXT: v_mad_u32_u24 v0, s7, v0, v1 +; GFX7-NEXT: v_mov_b32_e32 v1, s12 +; GFX7-NEXT: s_lshr_b32 s5, s5, 24 +; GFX7-NEXT: v_mad_u32_u24 v0, s11, v1, v0 +; GFX7-NEXT: s_lshr_b32 s4, s4, 24 +; GFX7-NEXT: v_mov_b32_e32 v1, s5 +; GFX7-NEXT: v_mad_u32_u24 v0, s4, v1, v0 +; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: udot4_multiuse_mul1: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_movk_i32 s2, 0xff +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_load_dword s3, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX8-NEXT: s_load_dword s5, s[0:1], 0x0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_and_b32 s6, s3, s2 +; GFX8-NEXT: s_and_b32 s2, s4, s2 +; GFX8-NEXT: s_bfe_u32 s8, s4, 0x80008 +; GFX8-NEXT: v_mov_b32_e32 v0, s2 +; GFX8-NEXT: v_mov_b32_e32 v1, s5 +; GFX8-NEXT: s_bfe_u32 s7, s3, 0x80008 +; GFX8-NEXT: v_mad_u32_u24 v1, s6, v0, v1 +; GFX8-NEXT: v_mov_b32_e32 v2, s8 +; GFX8-NEXT: s_bfe_u32 s10, s4, 0x80010 +; GFX8-NEXT: v_mad_u32_u24 v1, s7, v2, v1 +; GFX8-NEXT: s_bfe_u32 s9, s3, 0x80010 +; GFX8-NEXT: v_mad_u32_u24 v0, s6, v0, v1 +; GFX8-NEXT: v_mov_b32_e32 v1, s10 +; GFX8-NEXT: s_lshr_b32 s4, s4, 24 +; GFX8-NEXT: v_mad_u32_u24 v0, s9, v1, v0 +; GFX8-NEXT: s_lshr_b32 s3, s3, 24 +; GFX8-NEXT: v_mov_b32_e32 v1, s4 +; GFX8-NEXT: v_mad_u32_u24 v2, s3, v1, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: udot4_multiuse_mul1: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NODL-NEXT: s_movk_i32 s2, 0xff +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_load_dword s3, s[4:5], 0x0 +; GFX9-NODL-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-NODL-NEXT: s_load_dword s5, s[0:1], 0x0 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_and_b32 s6, s3, s2 +; GFX9-NODL-NEXT: s_and_b32 s2, s4, s2 +; GFX9-NODL-NEXT: s_bfe_u32 s8, s4, 0x80008 +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-NODL-NEXT: s_bfe_u32 s7, s3, 0x80008 +; GFX9-NODL-NEXT: v_mad_u32_u24 v1, s6, v0, v1 +; GFX9-NODL-NEXT: v_mov_b32_e32 v2, s8 +; GFX9-NODL-NEXT: s_bfe_u32 s10, s4, 0x80010 +; GFX9-NODL-NEXT: v_mad_u32_u24 v1, s7, v2, v1 +; GFX9-NODL-NEXT: s_bfe_u32 s9, s3, 0x80010 +; GFX9-NODL-NEXT: v_mad_u32_u24 v0, s6, v0, v1 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s10 +; GFX9-NODL-NEXT: s_lshr_b32 s4, s4, 24 +; GFX9-NODL-NEXT: v_mad_u32_u24 v0, s9, v1, v0 +; GFX9-NODL-NEXT: s_lshr_b32 s3, s3, 24 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s3, v1, v0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NODL-NEXT: global_store_dword v[0:1], v2, off +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: udot4_multiuse_mul1: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_movk_i32 s2, 0xff +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s3, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-DL-NEXT: s_load_dword s5, s[0:1], 0x0 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_and_b32 s6, s3, s2 +; GFX9-DL-NEXT: s_and_b32 s2, s4, s2 +; GFX9-DL-NEXT: s_bfe_u32 s8, s4, 0x80008 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-DL-NEXT: s_bfe_u32 s7, s3, 0x80008 +; GFX9-DL-NEXT: v_mad_u32_u24 v1, s6, v0, v1 +; GFX9-DL-NEXT: v_mov_b32_e32 v2, s8 +; GFX9-DL-NEXT: s_bfe_u32 s10, s4, 0x80010 +; GFX9-DL-NEXT: v_mad_u32_u24 v1, s7, v2, v1 +; GFX9-DL-NEXT: s_bfe_u32 s9, s3, 0x80010 +; GFX9-DL-NEXT: v_mad_u32_u24 v0, s6, v0, v1 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s10 +; GFX9-DL-NEXT: s_lshr_b32 s4, s4, 24 +; GFX9-DL-NEXT: v_mad_u32_u24 v0, s9, v1, v0 +; GFX9-DL-NEXT: s_lshr_b32 s3, s3, 24 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s3, v1, v0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm <4 x i8> addrspace(1)* %src2, i32 addrspace(1)* nocapture %dst) { entry: @@ -486,38 +1053,143 @@ } define amdgpu_kernel void @udot4_multiuse_add1(<4 x i8> addrspace(1)* %src1, -; GCN-LABEL: udot4_multiuse_add1: -; GCN: ; %bb.0: ; %entry -; GCN-NEXT: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}} -; GCN-NEXT: s_load_dwordx2 s{{\[}}[[SRC2_LO:[0-9]+]]:[[SRC2_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xd|0x34}} -; GCN-NEXT: s_movk_i32 [[FF:s[0-9]+]], 0xff -; GCN: s_load_dword [[S0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x0 -; GCN-NEXT: s_load_dword [[S1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x0 -; GCN-NEXT: s_load_dword [[S2:s[0-9]+]], s{{\[}}[[SRC2_LO]]:[[SRC2_HI]]{{\]}}, 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_and_b32 [[V1E2:s[0-9]+]], [[S0]], [[FF]] -; GCN-NEXT: s_bfe_u32 [[SV2E1:s[0-9]+]], [[S1]], 0x80008 -; GCN-NEXT: s_and_b32 [[SV2E2:s[0-9]+]], [[S1]], [[FF]] -; GCN-NEXT: s_bfe_u32 [[V1E1:s[0-9]+]], [[S0]], 0x80008 -; GCN-NEXT: v_mov_b32_e32 [[V2E1:v[0-9]+]], [[SV2E1]] -; GCN-NEXT: v_mov_b32_e32 [[SRC2:v[0-9]+]], [[S2]] -; GCN-NEXT: v_mad_u32_u24 [[MAD1:v[0-9]+]], [[V1E1]], [[V2E1]], [[SRC2]] -; GCN-NEXT: s_bfe_u32 [[SV2E3:s[0-9]+]], [[S1]], 0x80010 -; GCN-NEXT: v_mov_b32_e32 [[V2E2:v[0-9]+]], [[SV2E2]] -; GCN-NEXT: s_bfe_u32 [[V1E3:s[0-9]+]], [[S0]], 0x80010 -; GCN-NEXT: v_add_{{i|u}}32_e32 [[ADD1:v[0-9]+]] -; GCN-NEXT: v_mad_u32_u24 [[MAD2:v[0-9]+]], [[V1E2]], [[V2E2]], [[MAD1]] -; GCN-NEXT: v_mov_b32_e32 [[V2E3:v[0-9]+]], [[SV2E3]] -; GCN-NEXT: s_lshr_b32 [[SV2E4:s[0-9]+]], [[S1]], 24 -; GCN-NEXT: v_mad_u32_u24 [[MAD3:v[0-9]+]], [[V1E3]], [[V2E3]], [[MAD2]] -; GCN-NEXT: s_lshr_b32 [[V1E4:s[0-9]+]], [[S0]], 24 -; GCN-NEXT: v_mov_b32_e32 [[V2E4:v[0-9]+]], [[SV2E4]] -; GCN-NEXT: v_mad_u32_u24 [[MAD4:v[0-9]+]], [[V1E4]], [[V2E4]], [[MAD3]] -; GCN-NEXT: v_add_{{i|u}}32_e32 [[RES:v[0-9]+]] -; GCN: {{buffer|flat|global}}_store_dword -; GCN-NEXT: s_endpgm - <4 x i8> addrspace(1)* %src2, - i32 addrspace(1)* nocapture %dst) { +; GFX7-LABEL: udot4_multiuse_add1: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_movk_i32 s8, 0xff +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 +; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0 +; GFX7-NEXT: s_load_dword s6, s[0:1], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_and_b32 s7, s4, s8 +; GFX7-NEXT: s_bfe_u32 s10, s5, 0x80008 +; GFX7-NEXT: s_and_b32 s8, s5, s8 +; GFX7-NEXT: s_bfe_u32 s9, s4, 0x80008 +; GFX7-NEXT: v_mov_b32_e32 v0, s10 +; GFX7-NEXT: v_mov_b32_e32 v1, s6 +; GFX7-NEXT: v_mad_u32_u24 v0, s9, v0, v1 +; GFX7-NEXT: s_bfe_u32 s12, s5, 0x80010 +; GFX7-NEXT: v_mov_b32_e32 v2, s8 +; GFX7-NEXT: s_bfe_u32 s11, s4, 0x80010 +; GFX7-NEXT: v_add_i32_e32 v1, vcc, s6, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s7, v2, v0 +; GFX7-NEXT: v_mov_b32_e32 v2, s12 +; GFX7-NEXT: s_lshr_b32 s5, s5, 24 +; GFX7-NEXT: v_mad_u32_u24 v0, s11, v2, v0 +; GFX7-NEXT: s_lshr_b32 s4, s4, 24 +; GFX7-NEXT: v_mov_b32_e32 v2, s5 +; GFX7-NEXT: v_mad_u32_u24 v0, s4, v2, v0 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: udot4_multiuse_add1: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_movk_i32 s2, 0xff +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_load_dword s3, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX8-NEXT: s_load_dword s5, s[0:1], 0x0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_and_b32 s6, s3, s2 +; GFX8-NEXT: s_bfe_u32 s8, s4, 0x80008 +; GFX8-NEXT: s_and_b32 s2, s4, s2 +; GFX8-NEXT: s_bfe_u32 s7, s3, 0x80008 +; GFX8-NEXT: v_mov_b32_e32 v0, s8 +; GFX8-NEXT: v_mov_b32_e32 v1, s5 +; GFX8-NEXT: v_mad_u32_u24 v0, s7, v0, v1 +; GFX8-NEXT: s_bfe_u32 s10, s4, 0x80010 +; GFX8-NEXT: v_mov_b32_e32 v2, s2 +; GFX8-NEXT: s_bfe_u32 s9, s3, 0x80010 +; GFX8-NEXT: v_add_u32_e32 v1, vcc, s5, v0 +; GFX8-NEXT: v_mad_u32_u24 v0, s6, v2, v0 +; GFX8-NEXT: v_mov_b32_e32 v2, s10 +; GFX8-NEXT: s_lshr_b32 s4, s4, 24 +; GFX8-NEXT: v_mad_u32_u24 v0, s9, v2, v0 +; GFX8-NEXT: s_lshr_b32 s3, s3, 24 +; GFX8-NEXT: v_mov_b32_e32 v2, s4 +; GFX8-NEXT: v_mad_u32_u24 v0, s3, v2, v0 +; GFX8-NEXT: v_add_u32_e32 v2, vcc, v0, v1 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: udot4_multiuse_add1: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NODL-NEXT: s_movk_i32 s2, 0xff +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_load_dword s3, s[4:5], 0x0 +; GFX9-NODL-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-NODL-NEXT: s_load_dword s5, s[0:1], 0x0 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_and_b32 s6, s3, s2 +; GFX9-NODL-NEXT: s_bfe_u32 s8, s4, 0x80008 +; GFX9-NODL-NEXT: s_and_b32 s2, s4, s2 +; GFX9-NODL-NEXT: s_bfe_u32 s7, s3, 0x80008 +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s8 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-NODL-NEXT: v_mad_u32_u24 v0, s7, v0, v1 +; GFX9-NODL-NEXT: s_bfe_u32 s10, s4, 0x80010 +; GFX9-NODL-NEXT: v_mov_b32_e32 v2, s2 +; GFX9-NODL-NEXT: s_bfe_u32 s9, s3, 0x80010 +; GFX9-NODL-NEXT: v_add_u32_e32 v1, s5, v0 +; GFX9-NODL-NEXT: v_mad_u32_u24 v0, s6, v2, v0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v2, s10 +; GFX9-NODL-NEXT: s_lshr_b32 s4, s4, 24 +; GFX9-NODL-NEXT: v_mad_u32_u24 v0, s9, v2, v0 +; GFX9-NODL-NEXT: s_lshr_b32 s3, s3, 24 +; GFX9-NODL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-NODL-NEXT: v_mad_u32_u24 v0, s3, v2, v0 +; GFX9-NODL-NEXT: v_add_u32_e32 v2, v0, v1 +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NODL-NEXT: global_store_dword v[0:1], v2, off +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: udot4_multiuse_add1: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_movk_i32 s2, 0xff +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s3, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-DL-NEXT: s_load_dword s5, s[0:1], 0x0 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_and_b32 s6, s3, s2 +; GFX9-DL-NEXT: s_bfe_u32 s8, s4, 0x80008 +; GFX9-DL-NEXT: s_and_b32 s2, s4, s2 +; GFX9-DL-NEXT: s_bfe_u32 s7, s3, 0x80008 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s8 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s5 +; GFX9-DL-NEXT: v_mad_u32_u24 v0, s7, v0, v1 +; GFX9-DL-NEXT: s_bfe_u32 s10, s4, 0x80010 +; GFX9-DL-NEXT: v_mov_b32_e32 v2, s2 +; GFX9-DL-NEXT: s_bfe_u32 s9, s3, 0x80010 +; GFX9-DL-NEXT: v_add_u32_e32 v1, s5, v0 +; GFX9-DL-NEXT: v_mad_u32_u24 v0, s6, v2, v0 +; GFX9-DL-NEXT: v_mov_b32_e32 v2, s10 +; GFX9-DL-NEXT: s_lshr_b32 s4, s4, 24 +; GFX9-DL-NEXT: v_mad_u32_u24 v0, s9, v2, v0 +; GFX9-DL-NEXT: s_lshr_b32 s3, s3, 24 +; GFX9-DL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-DL-NEXT: v_mad_u32_u24 v0, s3, v2, v0 +; GFX9-DL-NEXT: v_add_u32_e32 v2, v0, v1 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm + <4 x i8> addrspace(1)* %src2, + i32 addrspace(1)* nocapture %dst) { entry: %vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1 %vec2 = load <4 x i8>, <4 x i8> addrspace(1)* %src2 @@ -558,31 +1230,141 @@ } define amdgpu_kernel void @notdot4_mixedtypes(<4 x i8> addrspace(1)* %src1, -; GCN-LABEL: notdot4_mixedtypes: -; GCN: ; %bb.0: ; %entry -; GCN-NEXT: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x9|0x24}} -; GCN-NEXT: s_load_dwordx2 s{{\[}}[[SRC2_LO:[0-9]+]]:[[SRC2_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xd|0x34}} -; GCN: s_mov_b32 [[FFFF:s[0-9]+]], 0xffff -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN: {{buffer|flat|global}}_load_ushort [[SRC2:v[0-9]+]] -; GCN: s_load_dword [[S1:s[0-9]+]], s[6:7], 0x0 -; GCN: s_waitcnt lgkmcnt(0) -; GCN: s_bfe_u32 [[SV2E1:s[0-9]+]], [[S1]], 0x80008 -; GCN: v_mov_b32_e32 [[V2E1:v[0-9]+]], [[SV2E1]] -; GCN: s_bfe_u32 [[SV2E3:s[0-9]+]], [[S1]], 0x80010 -; GCN: v_mov_b32_e32 [[V2E2:v[0-9]+]] -; GCN: s_bfe_u32 [[V1E3:s[0-9]+]], {{s[0-9]+}}, 0x80010 -; GCN-NEXT: s_lshr_b32 [[SV2E4:s[0-9]+]], [[S1]], 24 -; GCN-NEXT: v_mov_b32_e32 [[V2E3:v[0-9]+]], [[SV2E3]] -; GCN-NEXT: s_lshr_b32 [[V1E4:s[0-9]+]], {{s[0-9]+}}, 24 -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_mad_u32_u24 [[MAD1:v[0-9]+]], {{s[0-9]+}}, [[V2E1]], [[SRC2]] -; GCN-NEXT: v_mad_u32_u24 [[MAD2:v[0-9]+]], {{s[0-9]+}}, [[V2E2]], [[MAD1]] -; GCN-NEXT: v_mad_u32_u24 [[MAD3:v[0-9]+]], [[V1E3]], [[V2E3]], [[MAD2]] -; GCN-NEXT: v_mov_b32_e32 [[V2E4:v[0-9]+]], [[SV2E4]] -; GCN-NEXT: v_mad_u32_u24 [[MAD4:v[0-9]+]], [[V1E4]], [[V2E4]], [[MAD3]] -; GCN-NEXT: {{buffer|flat|global}}_store_short -; GCN-NEXT: s_endpgm +; GFX7-LABEL: notdot4_mixedtypes: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s8, 0xffff +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 +; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0 +; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_sext_i32_i8 s6, s4 +; GFX7-NEXT: s_bfe_u32 s10, s4, 0x80008 +; GFX7-NEXT: s_sext_i32_i8 s7, s5 +; GFX7-NEXT: s_bfe_u32 s9, s5, 0x80008 +; GFX7-NEXT: s_and_b32 s7, s7, s8 +; GFX7-NEXT: v_mov_b32_e32 v1, s9 +; GFX7-NEXT: s_bfe_u32 s11, s5, 0x80010 +; GFX7-NEXT: s_and_b32 s6, s6, s8 +; GFX7-NEXT: v_mov_b32_e32 v3, s7 +; GFX7-NEXT: s_bfe_u32 s12, s4, 0x80010 +; GFX7-NEXT: s_lshr_b32 s5, s5, 24 +; GFX7-NEXT: v_mov_b32_e32 v2, s11 +; GFX7-NEXT: s_lshr_b32 s4, s4, 24 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_mad_u32_u24 v0, s10, v1, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s6, v3, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s12, v2, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, s5 +; GFX7-NEXT: v_mad_u32_u24 v0, s4, v1, v0 +; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: notdot4_mixedtypes: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_mov_b32 s2, 0xffff +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ushort v2, v[0:1] +; GFX8-NEXT: s_load_dword s0, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s1, s[6:7], 0x0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_bfe_i32 s3, s0, 0x80000 +; GFX8-NEXT: s_bfe_u32 s6, s1, 0x80008 +; GFX8-NEXT: s_bfe_i32 s4, s1, 0x80000 +; GFX8-NEXT: s_and_b32 s3, s2, s3 +; GFX8-NEXT: s_and_b32 s2, s2, s4 +; GFX8-NEXT: s_bfe_u32 s5, s0, 0x80008 +; GFX8-NEXT: v_mov_b32_e32 v3, s6 +; GFX8-NEXT: s_bfe_u32 s8, s1, 0x80010 +; GFX8-NEXT: v_mov_b32_e32 v5, s2 +; GFX8-NEXT: s_bfe_u32 s7, s0, 0x80010 +; GFX8-NEXT: s_lshr_b32 s1, s1, 24 +; GFX8-NEXT: v_mov_b32_e32 v4, s8 +; GFX8-NEXT: s_lshr_b32 s0, s0, 24 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_mad_u32_u24 v2, s5, v3, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, s3, v5, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, s7, v4, v2 +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_mad_u32_u24 v2, s0, v3, v2 +; GFX8-NEXT: flat_store_short v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: notdot4_mixedtypes: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NODL-NEXT: s_mov_b32 s2, 0xffff +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NODL-NEXT: global_load_ushort v2, v[0:1], off +; GFX9-NODL-NEXT: s_load_dword s0, s[4:5], 0x0 +; GFX9-NODL-NEXT: s_load_dword s1, s[6:7], 0x0 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_bfe_i32 s3, s0, 0x80000 +; GFX9-NODL-NEXT: s_bfe_u32 s6, s1, 0x80008 +; GFX9-NODL-NEXT: s_bfe_i32 s4, s1, 0x80000 +; GFX9-NODL-NEXT: s_and_b32 s3, s2, s3 +; GFX9-NODL-NEXT: s_and_b32 s2, s2, s4 +; GFX9-NODL-NEXT: s_bfe_u32 s5, s0, 0x80008 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s6 +; GFX9-NODL-NEXT: s_bfe_u32 s8, s1, 0x80010 +; GFX9-NODL-NEXT: v_mov_b32_e32 v5, s2 +; GFX9-NODL-NEXT: s_bfe_u32 s7, s0, 0x80010 +; GFX9-NODL-NEXT: s_lshr_b32 s1, s1, 24 +; GFX9-NODL-NEXT: v_mov_b32_e32 v4, s8 +; GFX9-NODL-NEXT: s_lshr_b32 s0, s0, 24 +; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s5, v3, v2 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s3, v5, v2 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s7, v4, v2 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s0, v3, v2 +; GFX9-NODL-NEXT: global_store_short v[0:1], v2, off +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: notdot4_mixedtypes: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_mov_b32 s2, 0xffff +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_load_ushort v2, v[0:1], off +; GFX9-DL-NEXT: s_load_dword s0, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s1, s[6:7], 0x0 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_bfe_i32 s3, s0, 0x80000 +; GFX9-DL-NEXT: s_bfe_u32 s6, s1, 0x80008 +; GFX9-DL-NEXT: s_bfe_i32 s4, s1, 0x80000 +; GFX9-DL-NEXT: s_and_b32 s3, s2, s3 +; GFX9-DL-NEXT: s_and_b32 s2, s2, s4 +; GFX9-DL-NEXT: s_bfe_u32 s5, s0, 0x80008 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s6 +; GFX9-DL-NEXT: s_bfe_u32 s8, s1, 0x80010 +; GFX9-DL-NEXT: v_mov_b32_e32 v5, s2 +; GFX9-DL-NEXT: s_bfe_u32 s7, s0, 0x80010 +; GFX9-DL-NEXT: s_lshr_b32 s1, s1, 24 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s8 +; GFX9-DL-NEXT: s_lshr_b32 s0, s0, 24 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s5, v3, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s3, v5, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s7, v4, v2 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s0, v3, v2 +; GFX9-DL-NEXT: global_store_short v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm <4 x i8> addrspace(1)* %src2, i16 addrspace(1)* nocapture %dst) { entry: @@ -622,3 +1404,1504 @@ store i16 %add4, i16 addrspace(1)* %dst, align 2 ret void } + +define amdgpu_kernel void @idot4_acc32(<4 x i8> addrspace(1)* %src1, +; GFX7-LABEL: idot4_acc32: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 +; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0 +; GFX7-NEXT: s_load_dword s6, s[0:1], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_sext_i32_i8 s7, s4 +; GFX7-NEXT: s_sext_i32_i8 s8, s5 +; GFX7-NEXT: s_bfe_i32 s10, s5, 0x80008 +; GFX7-NEXT: v_mov_b32_e32 v0, s8 +; GFX7-NEXT: v_mov_b32_e32 v1, s6 +; GFX7-NEXT: s_bfe_i32 s12, s5, 0x80010 +; GFX7-NEXT: v_mad_i32_i24 v0, s7, v0, v1 +; GFX7-NEXT: s_bfe_i32 s9, s4, 0x80008 +; GFX7-NEXT: v_mov_b32_e32 v1, s10 +; GFX7-NEXT: s_bfe_i32 s11, s4, 0x80010 +; GFX7-NEXT: v_mad_i32_i24 v0, s9, v1, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, s12 +; GFX7-NEXT: s_ashr_i32 s5, s5, 24 +; GFX7-NEXT: v_mad_i32_i24 v0, s11, v1, v0 +; GFX7-NEXT: s_ashr_i32 s4, s4, 24 +; GFX7-NEXT: v_mov_b32_e32 v1, s5 +; GFX7-NEXT: v_mad_i32_i24 v0, s4, v1, v0 +; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: idot4_acc32: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s3, s[6:7], 0x0 +; GFX8-NEXT: s_load_dword s4, s[0:1], 0x0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_sext_i32_i8 s0, s2 +; GFX8-NEXT: s_sext_i32_i8 s1, s3 +; GFX8-NEXT: s_bfe_i32 s6, s3, 0x80008 +; GFX8-NEXT: v_mov_b32_e32 v2, s1 +; GFX8-NEXT: v_mov_b32_e32 v3, s4 +; GFX8-NEXT: s_bfe_i32 s8, s3, 0x80010 +; GFX8-NEXT: v_mad_i32_i24 v2, s0, v2, v3 +; GFX8-NEXT: s_bfe_i32 s5, s2, 0x80008 +; GFX8-NEXT: v_mov_b32_e32 v3, s6 +; GFX8-NEXT: s_bfe_i32 s7, s2, 0x80010 +; GFX8-NEXT: v_mad_i32_i24 v2, s5, v3, v2 +; GFX8-NEXT: v_mov_b32_e32 v3, s8 +; GFX8-NEXT: s_ashr_i32 s3, s3, 24 +; GFX8-NEXT: v_mad_i32_i24 v2, s7, v3, v2 +; GFX8-NEXT: s_ashr_i32 s2, s2, 24 +; GFX8-NEXT: v_mov_b32_e32 v3, s3 +; GFX8-NEXT: v_mad_i32_i24 v2, s2, v3, v2 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: idot4_acc32: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-NODL-NEXT: s_load_dword s3, s[6:7], 0x0 +; GFX9-NODL-NEXT: s_load_dword s4, s[0:1], 0x0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_sext_i32_i8 s0, s2 +; GFX9-NODL-NEXT: s_sext_i32_i8 s1, s3 +; GFX9-NODL-NEXT: s_bfe_i32 s6, s3, 0x80008 +; GFX9-NODL-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s4 +; GFX9-NODL-NEXT: s_bfe_i32 s8, s3, 0x80010 +; GFX9-NODL-NEXT: v_mad_i32_i24 v2, s0, v2, v3 +; GFX9-NODL-NEXT: s_bfe_i32 s5, s2, 0x80008 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s6 +; GFX9-NODL-NEXT: s_bfe_i32 s7, s2, 0x80010 +; GFX9-NODL-NEXT: v_mad_i32_i24 v2, s5, v3, v2 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s8 +; GFX9-NODL-NEXT: s_ashr_i32 s3, s3, 24 +; GFX9-NODL-NEXT: v_mad_i32_i24 v2, s7, v3, v2 +; GFX9-NODL-NEXT: s_ashr_i32 s2, s2, 24 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s3 +; GFX9-NODL-NEXT: v_mad_i32_i24 v2, s2, v3, v2 +; GFX9-NODL-NEXT: global_store_dword v[0:1], v2, off +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: idot4_acc32: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s3, s[6:7], 0x0 +; GFX9-DL-NEXT: s_load_dword s4, s[0:1], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: v_mov_b32_e32 v2, s3 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s4 +; GFX9-DL-NEXT: v_dot4_i32_i8 v2, s2, v2, v3 +; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm + <4 x i8> addrspace(1)* %src2, + i32 addrspace(1)* nocapture %dst) { +entry: + %vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1 + %vec2 = load <4 x i8>, <4 x i8> addrspace(1)* %src2 + + %v1e0 = extractelement <4 x i8> %vec1, i64 0 + %cv1e0 = sext i8 %v1e0 to i32 + %v2e0 = extractelement <4 x i8> %vec2, i64 0 + %cv2e0 = sext i8 %v2e0 to i32 + %mul1 = mul nuw nsw i32 %cv1e0, %cv2e0 + + %v1e1 = extractelement <4 x i8> %vec1, i64 1 + %cv1e1 = sext i8 %v1e1 to i32 + %v2e1 = extractelement <4 x i8> %vec2, i64 1 + %cv2e1 = sext i8 %v2e1 to i32 + %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1 + + %v1e2 = extractelement <4 x i8> %vec1, i64 2 + %cv1e2 = sext i8 %v1e2 to i32 + %v2e2 = extractelement <4 x i8> %vec2, i64 2 + %cv2e2 = sext i8 %v2e2 to i32 + %mul3 = mul nuw nsw i32 %cv1e2, %cv2e2 + + %v1e3 = extractelement <4 x i8> %vec1, i64 3 + %cv1e3 = sext i8 %v1e3 to i32 + %v2e3 = extractelement <4 x i8> %vec2, i64 3 + %cv2e3 = sext i8 %v2e3 to i32 + %mul4 = mul nuw nsw i32 %cv1e3, %cv2e3 + + %acc = load i32, i32 addrspace(1)* %dst, align 4 + %add1 = add i32 %mul1, %acc + %add2 = add i32 %add1, %mul2 + %add3 = add i32 %add2, %mul3 + %add4 = add i32 %add3, %mul4 + store i32 %add4, i32 addrspace(1)* %dst, align 4 + ret void +} + +; TODO: Currently, vector elements{0 and 3} get zero_extended from i16 to i32 which should +; be sign_extended directly to i32; prevents the pattern recognizer to recognize this pattern. +define amdgpu_kernel void @idot4_acc16(<4 x i8> addrspace(1)* %src1, +; GFX7-LABEL: idot4_acc16: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s8, 0xffff +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 +; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0 +; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_sext_i32_i8 s6, s4 +; GFX7-NEXT: s_bfe_i32 s9, s4, 0x80008 +; GFX7-NEXT: s_sext_i32_i8 s7, s5 +; GFX7-NEXT: s_bfe_i32 s10, s5, 0x80008 +; GFX7-NEXT: s_and_b32 s7, s7, s8 +; GFX7-NEXT: s_bfe_i32 s12, s5, 0x80010 +; GFX7-NEXT: s_and_b32 s10, s10, s8 +; GFX7-NEXT: s_and_b32 s6, s6, s8 +; GFX7-NEXT: v_mov_b32_e32 v1, s7 +; GFX7-NEXT: s_bfe_i32 s11, s4, 0x80010 +; GFX7-NEXT: s_ashr_i32 s5, s5, 24 +; GFX7-NEXT: s_and_b32 s12, s12, s8 +; GFX7-NEXT: s_and_b32 s9, s9, s8 +; GFX7-NEXT: v_mov_b32_e32 v2, s10 +; GFX7-NEXT: s_ashr_i32 s4, s4, 24 +; GFX7-NEXT: s_and_b32 s11, s11, s8 +; GFX7-NEXT: s_and_b32 s5, s5, s8 +; GFX7-NEXT: v_mov_b32_e32 v3, s12 +; GFX7-NEXT: s_and_b32 s4, s4, s8 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_mad_u32_u24 v0, s6, v1, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s9, v2, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s11, v3, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, s5 +; GFX7-NEXT: v_mad_u32_u24 v0, s4, v1, v0 +; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: idot4_acc16: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ushort v2, v[0:1] +; GFX8-NEXT: s_load_dword s1, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s2, s[6:7], 0x0 +; GFX8-NEXT: s_mov_b32 s0, 0xffff +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_lshr_b32 s5, s1, 8 +; GFX8-NEXT: s_lshr_b32 s6, s2, 8 +; GFX8-NEXT: s_sext_i32_i8 s4, s2 +; GFX8-NEXT: s_bfe_i32 s5, s5, 0x80000 +; GFX8-NEXT: s_bfe_i32 s6, s6, 0x80000 +; GFX8-NEXT: s_bfe_i32 s8, s2, 0x80010 +; GFX8-NEXT: s_lshr_b32 s2, s2, 24 +; GFX8-NEXT: v_mov_b32_e32 v3, s4 +; GFX8-NEXT: s_sext_i32_i8 s3, s1 +; GFX8-NEXT: s_bfe_i32 s7, s1, 0x80010 +; GFX8-NEXT: s_lshr_b32 s1, s1, 24 +; GFX8-NEXT: s_and_b32 s4, s0, s5 +; GFX8-NEXT: s_and_b32 s5, s0, s6 +; GFX8-NEXT: s_bfe_i32 s1, s1, 0x80000 +; GFX8-NEXT: s_bfe_i32 s2, s2, 0x80000 +; GFX8-NEXT: v_mov_b32_e32 v5, s5 +; GFX8-NEXT: s_and_b32 s1, s0, s1 +; GFX8-NEXT: v_mov_b32_e32 v4, s8 +; GFX8-NEXT: s_and_b32 s0, s0, s2 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_mad_i32_i24 v2, s3, v3, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, s4, v5, v2 +; GFX8-NEXT: v_mad_i32_i24 v2, s7, v4, v2 +; GFX8-NEXT: v_mov_b32_e32 v3, s0 +; GFX8-NEXT: v_mad_u32_u24 v2, s1, v3, v2 +; GFX8-NEXT: flat_store_short v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: idot4_acc16: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NODL-NEXT: global_load_ushort v2, v[0:1], off +; GFX9-NODL-NEXT: s_load_dword s1, s[4:5], 0x0 +; GFX9-NODL-NEXT: s_load_dword s2, s[6:7], 0x0 +; GFX9-NODL-NEXT: s_mov_b32 s0, 0xffff +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_lshr_b32 s5, s1, 8 +; GFX9-NODL-NEXT: s_lshr_b32 s6, s2, 8 +; GFX9-NODL-NEXT: s_sext_i32_i8 s4, s2 +; GFX9-NODL-NEXT: s_bfe_i32 s5, s5, 0x80000 +; GFX9-NODL-NEXT: s_bfe_i32 s6, s6, 0x80000 +; GFX9-NODL-NEXT: s_bfe_i32 s8, s2, 0x80010 +; GFX9-NODL-NEXT: s_lshr_b32 s2, s2, 24 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s4 +; GFX9-NODL-NEXT: s_sext_i32_i8 s3, s1 +; GFX9-NODL-NEXT: s_bfe_i32 s7, s1, 0x80010 +; GFX9-NODL-NEXT: s_lshr_b32 s1, s1, 24 +; GFX9-NODL-NEXT: s_and_b32 s4, s0, s5 +; GFX9-NODL-NEXT: s_and_b32 s5, s0, s6 +; GFX9-NODL-NEXT: s_bfe_i32 s1, s1, 0x80000 +; GFX9-NODL-NEXT: s_bfe_i32 s2, s2, 0x80000 +; GFX9-NODL-NEXT: v_mov_b32_e32 v5, s5 +; GFX9-NODL-NEXT: s_and_b32 s1, s0, s1 +; GFX9-NODL-NEXT: v_mov_b32_e32 v4, s8 +; GFX9-NODL-NEXT: s_and_b32 s0, s0, s2 +; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) +; GFX9-NODL-NEXT: v_mad_i32_i24 v2, s3, v3, v2 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s4, v5, v2 +; GFX9-NODL-NEXT: v_mad_i32_i24 v2, s7, v4, v2 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s1, v3, v2 +; GFX9-NODL-NEXT: global_store_short v[0:1], v2, off +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: idot4_acc16: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_load_ushort v2, v[0:1], off +; GFX9-DL-NEXT: s_load_dword s1, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s2, s[6:7], 0x0 +; GFX9-DL-NEXT: s_mov_b32 s0, 0xffff +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_lshr_b32 s5, s1, 8 +; GFX9-DL-NEXT: s_lshr_b32 s6, s2, 8 +; GFX9-DL-NEXT: s_sext_i32_i8 s4, s2 +; GFX9-DL-NEXT: s_bfe_i32 s5, s5, 0x80000 +; GFX9-DL-NEXT: s_bfe_i32 s6, s6, 0x80000 +; GFX9-DL-NEXT: s_bfe_i32 s8, s2, 0x80010 +; GFX9-DL-NEXT: s_lshr_b32 s2, s2, 24 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s4 +; GFX9-DL-NEXT: s_sext_i32_i8 s3, s1 +; GFX9-DL-NEXT: s_bfe_i32 s7, s1, 0x80010 +; GFX9-DL-NEXT: s_lshr_b32 s1, s1, 24 +; GFX9-DL-NEXT: s_and_b32 s4, s0, s5 +; GFX9-DL-NEXT: s_and_b32 s5, s0, s6 +; GFX9-DL-NEXT: s_bfe_i32 s1, s1, 0x80000 +; GFX9-DL-NEXT: s_bfe_i32 s2, s2, 0x80000 +; GFX9-DL-NEXT: v_mov_b32_e32 v5, s5 +; GFX9-DL-NEXT: s_and_b32 s1, s0, s1 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s8 +; GFX9-DL-NEXT: s_and_b32 s0, s0, s2 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s3, v3, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s4, v5, v2 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s7, v4, v2 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s0 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s1, v3, v2 +; GFX9-DL-NEXT: global_store_short v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm + <4 x i8> addrspace(1)* %src2, + i16 addrspace(1)* nocapture %dst) { +entry: + %vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1 + %vec2 = load <4 x i8>, <4 x i8> addrspace(1)* %src2 + + %v1e0 = extractelement <4 x i8> %vec1, i64 0 + %cv1e0 = sext i8 %v1e0 to i16 + %v2e0 = extractelement <4 x i8> %vec2, i64 0 + %cv2e0 = sext i8 %v2e0 to i16 + %mul1 = mul nsw i16 %cv1e0, %cv2e0 + + %v1e1 = extractelement <4 x i8> %vec1, i64 1 + %cv1e1 = sext i8 %v1e1 to i16 + %v2e1 = extractelement <4 x i8> %vec2, i64 1 + %cv2e1 = sext i8 %v2e1 to i16 + %mul2 = mul nsw i16 %cv1e1, %cv2e1 + + %v1e2 = extractelement <4 x i8> %vec1, i64 2 + %cv1e2 = sext i8 %v1e2 to i16 + %v2e2 = extractelement <4 x i8> %vec2, i64 2 + %cv2e2 = sext i8 %v2e2 to i16 + %mul3 = mul nsw i16 %cv1e2, %cv2e2 + + %v1e3 = extractelement <4 x i8> %vec1, i64 3 + %cv1e3 = sext i8 %v1e3 to i16 + %v2e3 = extractelement <4 x i8> %vec2, i64 3 + %cv2e3 = sext i8 %v2e3 to i16 + %mul4 = mul nsw i16 %cv1e3, %cv2e3 + + %acc = load i16, i16 addrspace(1)* %dst, align 2 + %add1 = add i16 %mul1, %acc + %add2 = add i16 %add1, %mul2 + %add3 = add i16 %add2, %mul3 + %add4 = add i16 %add3, %mul4 + store i16 %add4, i16 addrspace(1)* %dst, align 2 + ret void +} + +define amdgpu_kernel void @idot4_acc8(<4 x i8> addrspace(1)* %src1, +; GFX7-LABEL: idot4_acc8: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_movk_i32 s8, 0xff +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 +; GFX7-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 +; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_and_b32 s7, s4, s8 +; GFX7-NEXT: s_bfe_u32 s9, s4, 0x80008 +; GFX7-NEXT: s_and_b32 s6, s5, s8 +; GFX7-NEXT: s_bfe_u32 s8, s5, 0x80008 +; GFX7-NEXT: v_mov_b32_e32 v1, s6 +; GFX7-NEXT: s_bfe_u32 s10, s5, 0x80010 +; GFX7-NEXT: v_mov_b32_e32 v2, s8 +; GFX7-NEXT: s_bfe_u32 s11, s4, 0x80010 +; GFX7-NEXT: s_lshr_b32 s5, s5, 24 +; GFX7-NEXT: v_mov_b32_e32 v3, s10 +; GFX7-NEXT: s_lshr_b32 s4, s4, 24 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_mad_u32_u24 v0, s7, v1, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s9, v2, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s11, v3, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, s5 +; GFX7-NEXT: v_mad_u32_u24 v0, s4, v1, v0 +; GFX7-NEXT: buffer_store_byte v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: idot4_acc8: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_movk_i32 s2, 0xff +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ubyte v2, v[0:1] +; GFX8-NEXT: s_load_dword s0, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s1, s[6:7], 0x0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_bfe_u32 s4, s0, 0x80008 +; GFX8-NEXT: s_and_b32 s3, s1, s2 +; GFX8-NEXT: s_bfe_u32 s5, s1, 0x80008 +; GFX8-NEXT: s_and_b32 s2, s0, s2 +; GFX8-NEXT: v_mov_b32_e32 v3, s3 +; GFX8-NEXT: s_bfe_u32 s6, s1, 0x80010 +; GFX8-NEXT: v_mov_b32_e32 v4, s5 +; GFX8-NEXT: s_bfe_u32 s7, s0, 0x80010 +; GFX8-NEXT: s_lshr_b32 s1, s1, 24 +; GFX8-NEXT: v_mov_b32_e32 v5, s6 +; GFX8-NEXT: s_lshr_b32 s0, s0, 24 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_mad_u32_u24 v2, s2, v3, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, s4, v4, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, s7, v5, v2 +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_mad_u32_u24 v2, s0, v3, v2 +; GFX8-NEXT: flat_store_byte v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: idot4_acc8: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NODL-NEXT: s_movk_i32 s2, 0xff +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NODL-NEXT: global_load_ubyte v2, v[0:1], off +; GFX9-NODL-NEXT: s_load_dword s0, s[4:5], 0x0 +; GFX9-NODL-NEXT: s_load_dword s1, s[6:7], 0x0 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_bfe_u32 s4, s0, 0x80008 +; GFX9-NODL-NEXT: s_and_b32 s3, s1, s2 +; GFX9-NODL-NEXT: s_bfe_u32 s5, s1, 0x80008 +; GFX9-NODL-NEXT: s_and_b32 s2, s0, s2 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s3 +; GFX9-NODL-NEXT: s_bfe_u32 s6, s1, 0x80010 +; GFX9-NODL-NEXT: v_mov_b32_e32 v4, s5 +; GFX9-NODL-NEXT: s_bfe_u32 s7, s0, 0x80010 +; GFX9-NODL-NEXT: s_lshr_b32 s1, s1, 24 +; GFX9-NODL-NEXT: v_mov_b32_e32 v5, s6 +; GFX9-NODL-NEXT: s_lshr_b32 s0, s0, 24 +; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s2, v3, v2 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s4, v4, v2 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s7, v5, v2 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s0, v3, v2 +; GFX9-NODL-NEXT: global_store_byte v[0:1], v2, off +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: idot4_acc8: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s3, s[6:7], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_load_ubyte v2, v[0:1], off +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s3 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_dot4_u32_u8 v2, s2, v3, v2 +; GFX9-DL-NEXT: global_store_byte v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm + <4 x i8> addrspace(1)* %src2, + i8 addrspace(1)* nocapture %dst) { +entry: + %vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1 + %vec2 = load <4 x i8>, <4 x i8> addrspace(1)* %src2 + + %v1e0 = extractelement <4 x i8> %vec1, i64 0 + %v2e0 = extractelement <4 x i8> %vec2, i64 0 + %mul1 = mul i8 %v1e0, %v2e0 + + %v1e1 = extractelement <4 x i8> %vec1, i64 1 + %v2e1 = extractelement <4 x i8> %vec2, i64 1 + %mul2 = mul i8 %v1e1, %v2e1 + + %v1e2 = extractelement <4 x i8> %vec1, i64 2 + %v2e2 = extractelement <4 x i8> %vec2, i64 2 + %mul3 = mul i8 %v1e2, %v2e2 + + %v1e3 = extractelement <4 x i8> %vec1, i64 3 + %v2e3 = extractelement <4 x i8> %vec2, i64 3 + %mul4 = mul i8 %v1e3, %v2e3 + + %acc = load i8, i8 addrspace(1)* %dst, align 2 + %add1 = add i8 %mul1, %acc + %add2 = add i8 %add1, %mul2 + %add3 = add i8 %add2, %mul3 + %add4 = add nsw i8 %add3, %mul4 + store i8 %add4, i8 addrspace(1)* %dst, align 2 + ret void +} + +define amdgpu_kernel void @idot4_multiuse_mul1(<4 x i8> addrspace(1)* %src1, +; GFX7-LABEL: idot4_multiuse_mul1: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 +; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0 +; GFX7-NEXT: s_load_dword s6, s[0:1], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_sext_i32_i8 s7, s4 +; GFX7-NEXT: s_sext_i32_i8 s8, s5 +; GFX7-NEXT: s_bfe_i32 s10, s5, 0x80008 +; GFX7-NEXT: v_mov_b32_e32 v0, s8 +; GFX7-NEXT: v_mov_b32_e32 v1, s6 +; GFX7-NEXT: s_bfe_i32 s9, s4, 0x80008 +; GFX7-NEXT: v_mad_i32_i24 v1, s7, v0, v1 +; GFX7-NEXT: v_mov_b32_e32 v2, s10 +; GFX7-NEXT: s_bfe_i32 s12, s5, 0x80010 +; GFX7-NEXT: v_mad_i32_i24 v1, s9, v2, v1 +; GFX7-NEXT: s_bfe_i32 s11, s4, 0x80010 +; GFX7-NEXT: v_mad_i32_i24 v0, s7, v0, v1 +; GFX7-NEXT: v_mov_b32_e32 v1, s12 +; GFX7-NEXT: s_ashr_i32 s5, s5, 24 +; GFX7-NEXT: v_mad_i32_i24 v0, s11, v1, v0 +; GFX7-NEXT: s_ashr_i32 s4, s4, 24 +; GFX7-NEXT: v_mov_b32_e32 v1, s5 +; GFX7-NEXT: v_mad_i32_i24 v0, s4, v1, v0 +; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: idot4_multiuse_mul1: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s3, s[6:7], 0x0 +; GFX8-NEXT: s_load_dword s4, s[0:1], 0x0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_sext_i32_i8 s0, s2 +; GFX8-NEXT: s_sext_i32_i8 s1, s3 +; GFX8-NEXT: s_bfe_i32 s6, s3, 0x80008 +; GFX8-NEXT: v_mov_b32_e32 v2, s1 +; GFX8-NEXT: v_mov_b32_e32 v3, s4 +; GFX8-NEXT: s_bfe_i32 s5, s2, 0x80008 +; GFX8-NEXT: v_mad_i32_i24 v3, s0, v2, v3 +; GFX8-NEXT: v_mov_b32_e32 v4, s6 +; GFX8-NEXT: s_bfe_i32 s8, s3, 0x80010 +; GFX8-NEXT: v_mad_i32_i24 v3, s5, v4, v3 +; GFX8-NEXT: s_bfe_i32 s7, s2, 0x80010 +; GFX8-NEXT: v_mad_i32_i24 v2, s0, v2, v3 +; GFX8-NEXT: v_mov_b32_e32 v3, s8 +; GFX8-NEXT: s_ashr_i32 s3, s3, 24 +; GFX8-NEXT: v_mad_i32_i24 v2, s7, v3, v2 +; GFX8-NEXT: s_ashr_i32 s2, s2, 24 +; GFX8-NEXT: v_mov_b32_e32 v3, s3 +; GFX8-NEXT: v_mad_i32_i24 v2, s2, v3, v2 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: idot4_multiuse_mul1: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-NODL-NEXT: s_load_dword s3, s[6:7], 0x0 +; GFX9-NODL-NEXT: s_load_dword s4, s[0:1], 0x0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_sext_i32_i8 s0, s2 +; GFX9-NODL-NEXT: s_sext_i32_i8 s1, s3 +; GFX9-NODL-NEXT: s_bfe_i32 s6, s3, 0x80008 +; GFX9-NODL-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s4 +; GFX9-NODL-NEXT: s_bfe_i32 s5, s2, 0x80008 +; GFX9-NODL-NEXT: v_mad_i32_i24 v3, s0, v2, v3 +; GFX9-NODL-NEXT: v_mov_b32_e32 v4, s6 +; GFX9-NODL-NEXT: s_bfe_i32 s8, s3, 0x80010 +; GFX9-NODL-NEXT: v_mad_i32_i24 v3, s5, v4, v3 +; GFX9-NODL-NEXT: s_bfe_i32 s7, s2, 0x80010 +; GFX9-NODL-NEXT: v_mad_i32_i24 v2, s0, v2, v3 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s8 +; GFX9-NODL-NEXT: s_ashr_i32 s3, s3, 24 +; GFX9-NODL-NEXT: v_mad_i32_i24 v2, s7, v3, v2 +; GFX9-NODL-NEXT: s_ashr_i32 s2, s2, 24 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s3 +; GFX9-NODL-NEXT: v_mad_i32_i24 v2, s2, v3, v2 +; GFX9-NODL-NEXT: global_store_dword v[0:1], v2, off +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: idot4_multiuse_mul1: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s3, s[6:7], 0x0 +; GFX9-DL-NEXT: s_load_dword s4, s[0:1], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_sext_i32_i8 s0, s2 +; GFX9-DL-NEXT: s_sext_i32_i8 s1, s3 +; GFX9-DL-NEXT: s_bfe_i32 s6, s3, 0x80008 +; GFX9-DL-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s4 +; GFX9-DL-NEXT: s_bfe_i32 s5, s2, 0x80008 +; GFX9-DL-NEXT: v_mad_i32_i24 v3, s0, v2, v3 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s6 +; GFX9-DL-NEXT: s_bfe_i32 s8, s3, 0x80010 +; GFX9-DL-NEXT: v_mad_i32_i24 v3, s5, v4, v3 +; GFX9-DL-NEXT: s_bfe_i32 s7, s2, 0x80010 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s0, v2, v3 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s8 +; GFX9-DL-NEXT: s_ashr_i32 s3, s3, 24 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s7, v3, v2 +; GFX9-DL-NEXT: s_ashr_i32 s2, s2, 24 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s3 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s2, v3, v2 +; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm + <4 x i8> addrspace(1)* %src2, + i32 addrspace(1)* nocapture %dst) { +entry: + %vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1 + %vec2 = load <4 x i8>, <4 x i8> addrspace(1)* %src2 + + %v1e0 = extractelement <4 x i8> %vec1, i64 0 + %cv1e0 = sext i8 %v1e0 to i32 + %v2e0 = extractelement <4 x i8> %vec2, i64 0 + %cv2e0 = sext i8 %v2e0 to i32 + %mul1 = mul nuw nsw i32 %cv1e0, %cv2e0 + + %v1e1 = extractelement <4 x i8> %vec1, i64 1 + %cv1e1 = sext i8 %v1e1 to i32 + %v2e1 = extractelement <4 x i8> %vec2, i64 1 + %cv2e1 = sext i8 %v2e1 to i32 + %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1 + + %v1e2 = extractelement <4 x i8> %vec1, i64 2 + %cv1e2 = sext i8 %v1e2 to i32 + %v2e2 = extractelement <4 x i8> %vec2, i64 2 + %cv2e2 = sext i8 %v2e2 to i32 + %mul3 = mul nuw nsw i32 %cv1e2, %cv2e2 + + %v1e3 = extractelement <4 x i8> %vec1, i64 3 + %cv1e3 = sext i8 %v1e3 to i32 + %v2e3 = extractelement <4 x i8> %vec2, i64 3 + %cv2e3 = sext i8 %v2e3 to i32 + %mul4 = mul nuw nsw i32 %cv1e3, %cv2e3 + + %acc = load i32, i32 addrspace(1)* %dst, align 4 + %add = add i32 %mul1, %acc + %add1 = add i32 %mul2, %add + %add2 = add i32 %add1, %mul1 + %add3 = add i32 %add2, %mul3 + %add4 = add i32 %add3, %mul4 + + store i32 %add4, i32 addrspace(1)* %dst, align 4 + ret void +} + +; TODO: cleanup s_lshr_b32 and support this pattern. +define amdgpu_kernel void @udot4_acc32_vecMul(<4 x i8> addrspace(1)* %src1, +; GFX7-LABEL: udot4_acc32_vecMul: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_movk_i32 s12, 0xff +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 +; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0 +; GFX7-NEXT: s_load_dword s6, s[0:1], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_lshr_b32 s7, s4, 24 +; GFX7-NEXT: s_lshr_b32 s9, s5, 24 +; GFX7-NEXT: s_bfe_u32 s10, s5, 0x80008 +; GFX7-NEXT: s_bfe_u32 s13, s5, 0x80010 +; GFX7-NEXT: s_and_b32 s5, s5, s12 +; GFX7-NEXT: s_bfe_u32 s8, s4, 0x80008 +; GFX7-NEXT: s_bfe_u32 s11, s4, 0x80010 +; GFX7-NEXT: s_and_b32 s4, s4, s12 +; GFX7-NEXT: v_mov_b32_e32 v0, s5 +; GFX7-NEXT: v_mov_b32_e32 v1, s6 +; GFX7-NEXT: v_mad_u32_u24 v0, s4, v0, v1 +; GFX7-NEXT: v_mov_b32_e32 v1, s10 +; GFX7-NEXT: v_mad_u32_u24 v0, s8, v1, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, s13 +; GFX7-NEXT: v_mad_u32_u24 v0, s11, v1, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, s9 +; GFX7-NEXT: v_mad_u32_u24 v0, s7, v1, v0 +; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: udot4_acc32_vecMul: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_movk_i32 s2, 0xff +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_load_dword s3, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX8-NEXT: s_load_dword s5, s[0:1], 0x0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_lshr_b32 s6, s3, 24 +; GFX8-NEXT: s_bfe_u32 s8, s3, 0x80010 +; GFX8-NEXT: v_lshrrev_b16_e64 v0, 8, s3 +; GFX8-NEXT: s_and_b32 s3, s3, s2 +; GFX8-NEXT: s_and_b32 s2, s4, s2 +; GFX8-NEXT: v_mov_b32_e32 v2, s2 +; GFX8-NEXT: v_mov_b32_e32 v3, s5 +; GFX8-NEXT: s_bfe_u32 s9, s4, 0x80010 +; GFX8-NEXT: v_lshrrev_b16_e64 v1, 8, s4 +; GFX8-NEXT: v_mad_u32_u24 v2, s3, v2, v3 +; GFX8-NEXT: v_mad_u32_u24 v0, v0, v1, v2 +; GFX8-NEXT: v_mov_b32_e32 v1, s9 +; GFX8-NEXT: s_lshr_b32 s7, s4, 24 +; GFX8-NEXT: v_mad_u32_u24 v0, s8, v1, v0 +; GFX8-NEXT: v_mov_b32_e32 v1, s7 +; GFX8-NEXT: v_mad_u32_u24 v2, s6, v1, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: udot4_acc32_vecMul: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NODL-NEXT: s_movk_i32 s2, 0xff +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_load_dword s3, s[4:5], 0x0 +; GFX9-NODL-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-NODL-NEXT: s_load_dword s5, s[0:1], 0x0 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_lshr_b32 s6, s3, 24 +; GFX9-NODL-NEXT: s_bfe_u32 s8, s3, 0x80010 +; GFX9-NODL-NEXT: v_lshrrev_b16_e64 v0, 8, s3 +; GFX9-NODL-NEXT: s_and_b32 s3, s3, s2 +; GFX9-NODL-NEXT: s_and_b32 s2, s4, s2 +; GFX9-NODL-NEXT: v_mov_b32_e32 v2, s2 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-NODL-NEXT: s_bfe_u32 s9, s4, 0x80010 +; GFX9-NODL-NEXT: v_lshrrev_b16_e64 v1, 8, s4 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s3, v2, v3 +; GFX9-NODL-NEXT: v_mad_u32_u24 v0, v0, v1, v2 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s9 +; GFX9-NODL-NEXT: s_lshr_b32 s7, s4, 24 +; GFX9-NODL-NEXT: v_mad_u32_u24 v0, s8, v1, v0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s7 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, s6, v1, v0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NODL-NEXT: global_store_dword v[0:1], v2, off +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: udot4_acc32_vecMul: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_movk_i32 s2, 0xff +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s3, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-DL-NEXT: s_load_dword s5, s[0:1], 0x0 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_lshr_b32 s6, s3, 24 +; GFX9-DL-NEXT: s_bfe_u32 s8, s3, 0x80010 +; GFX9-DL-NEXT: v_lshrrev_b16_e64 v0, 8, s3 +; GFX9-DL-NEXT: s_and_b32 s3, s3, s2 +; GFX9-DL-NEXT: s_and_b32 s2, s4, s2 +; GFX9-DL-NEXT: v_mov_b32_e32 v2, s2 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-DL-NEXT: s_bfe_u32 s9, s4, 0x80010 +; GFX9-DL-NEXT: v_lshrrev_b16_e64 v1, 8, s4 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s3, v2, v3 +; GFX9-DL-NEXT: v_mad_u32_u24 v0, v0, v1, v2 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s9 +; GFX9-DL-NEXT: s_lshr_b32 s7, s4, 24 +; GFX9-DL-NEXT: v_mad_u32_u24 v0, s8, v1, v0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s7 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s6, v1, v0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm + <4 x i8> addrspace(1)* %src2, + i32 addrspace(1)* nocapture %dst) { +entry: + %vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1 + %vec2 = load <4 x i8>, <4 x i8> addrspace(1)* %src2 + + %cvec1 = zext <4 x i8> %vec1 to <4 x i32> + %cvec2 = zext <4 x i8> %vec2 to <4 x i32> + + %mul = mul <4 x i32> %cvec1, %cvec2 + %mul0 = extractelement <4 x i32> %mul, i64 0 + %mul1 = extractelement <4 x i32> %mul, i64 1 + %mul2 = extractelement <4 x i32> %mul, i64 2 + %mul3 = extractelement <4 x i32> %mul, i64 3 + + %acc = load i32, i32 addrspace(1)* %dst, align 4 + %add1 = add i32 %mul0, %acc + %add2 = add i32 %add1, %mul1 + %add3 = add i32 %add2, %mul2 + %add4 = add i32 %add3, %mul3 + + store i32 %add4, i32 addrspace(1)* %dst, align 4 + ret void +} + +; TODO: Support this pattern. +define amdgpu_kernel void @idot4_acc32_vecMul(<4 x i8> addrspace(1)* %src1, +; GFX7-LABEL: idot4_acc32_vecMul: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 +; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0 +; GFX7-NEXT: s_load_dword s6, s[0:1], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_ashr_i32 s7, s4, 24 +; GFX7-NEXT: s_ashr_i32 s10, s5, 24 +; GFX7-NEXT: s_bfe_i32 s11, s5, 0x80010 +; GFX7-NEXT: s_bfe_i32 s12, s5, 0x80008 +; GFX7-NEXT: s_sext_i32_i8 s5, s5 +; GFX7-NEXT: s_bfe_i32 s8, s4, 0x80010 +; GFX7-NEXT: s_bfe_i32 s9, s4, 0x80008 +; GFX7-NEXT: s_sext_i32_i8 s4, s4 +; GFX7-NEXT: v_mov_b32_e32 v0, s5 +; GFX7-NEXT: v_mov_b32_e32 v1, s6 +; GFX7-NEXT: v_mad_i32_i24 v0, s4, v0, v1 +; GFX7-NEXT: v_mov_b32_e32 v1, s12 +; GFX7-NEXT: v_mad_i32_i24 v0, s9, v1, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, s11 +; GFX7-NEXT: v_mad_i32_i24 v0, s8, v1, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, s10 +; GFX7-NEXT: v_mad_i32_i24 v0, s7, v1, v0 +; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: idot4_acc32_vecMul: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s3, s[6:7], 0x0 +; GFX8-NEXT: s_load_dword s4, s[0:1], 0x0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_lshrrev_b16_e64 v2, 8, s2 +; GFX8-NEXT: v_lshrrev_b16_e64 v3, 8, s3 +; GFX8-NEXT: s_ashr_i32 s5, s3, 24 +; GFX8-NEXT: s_bfe_i32 s6, s3, 0x80010 +; GFX8-NEXT: s_sext_i32_i8 s3, s3 +; GFX8-NEXT: s_ashr_i32 s0, s2, 24 +; GFX8-NEXT: s_bfe_i32 s1, s2, 0x80010 +; GFX8-NEXT: s_sext_i32_i8 s2, s2 +; GFX8-NEXT: v_mov_b32_e32 v4, s3 +; GFX8-NEXT: v_mov_b32_e32 v5, s4 +; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 8 +; GFX8-NEXT: v_bfe_i32 v3, v3, 0, 8 +; GFX8-NEXT: v_mad_i32_i24 v4, s2, v4, v5 +; GFX8-NEXT: v_mad_i32_i24 v2, v2, v3, v4 +; GFX8-NEXT: v_mov_b32_e32 v3, s6 +; GFX8-NEXT: v_mad_i32_i24 v2, s1, v3, v2 +; GFX8-NEXT: v_mov_b32_e32 v3, s5 +; GFX8-NEXT: v_mad_i32_i24 v2, s0, v3, v2 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: idot4_acc32_vecMul: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-NODL-NEXT: s_load_dword s3, s[6:7], 0x0 +; GFX9-NODL-NEXT: s_load_dword s4, s[0:1], 0x0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: v_lshrrev_b16_e64 v2, 8, s2 +; GFX9-NODL-NEXT: v_lshrrev_b16_e64 v3, 8, s3 +; GFX9-NODL-NEXT: s_ashr_i32 s5, s3, 24 +; GFX9-NODL-NEXT: s_bfe_i32 s6, s3, 0x80010 +; GFX9-NODL-NEXT: s_sext_i32_i8 s3, s3 +; GFX9-NODL-NEXT: s_ashr_i32 s0, s2, 24 +; GFX9-NODL-NEXT: s_bfe_i32 s1, s2, 0x80010 +; GFX9-NODL-NEXT: s_sext_i32_i8 s2, s2 +; GFX9-NODL-NEXT: v_mov_b32_e32 v4, s3 +; GFX9-NODL-NEXT: v_mov_b32_e32 v5, s4 +; GFX9-NODL-NEXT: v_bfe_i32 v2, v2, 0, 8 +; GFX9-NODL-NEXT: v_bfe_i32 v3, v3, 0, 8 +; GFX9-NODL-NEXT: v_mad_i32_i24 v4, s2, v4, v5 +; GFX9-NODL-NEXT: v_mad_i32_i24 v2, v2, v3, v4 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s6 +; GFX9-NODL-NEXT: v_mad_i32_i24 v2, s1, v3, v2 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-NODL-NEXT: v_mad_i32_i24 v2, s0, v3, v2 +; GFX9-NODL-NEXT: global_store_dword v[0:1], v2, off +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: idot4_acc32_vecMul: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s3, s[6:7], 0x0 +; GFX9-DL-NEXT: s_load_dword s4, s[0:1], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: v_lshrrev_b16_e64 v2, 8, s2 +; GFX9-DL-NEXT: v_lshrrev_b16_e64 v3, 8, s3 +; GFX9-DL-NEXT: s_ashr_i32 s5, s3, 24 +; GFX9-DL-NEXT: s_bfe_i32 s6, s3, 0x80010 +; GFX9-DL-NEXT: s_sext_i32_i8 s3, s3 +; GFX9-DL-NEXT: s_ashr_i32 s0, s2, 24 +; GFX9-DL-NEXT: s_bfe_i32 s1, s2, 0x80010 +; GFX9-DL-NEXT: s_sext_i32_i8 s2, s2 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s3 +; GFX9-DL-NEXT: v_mov_b32_e32 v5, s4 +; GFX9-DL-NEXT: v_bfe_i32 v2, v2, 0, 8 +; GFX9-DL-NEXT: v_bfe_i32 v3, v3, 0, 8 +; GFX9-DL-NEXT: v_mad_i32_i24 v4, s2, v4, v5 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, v2, v3, v4 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s6 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s1, v3, v2 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s0, v3, v2 +; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm + <4 x i8> addrspace(1)* %src2, + i32 addrspace(1)* nocapture %dst) { +entry: + %vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1 + %vec2 = load <4 x i8>, <4 x i8> addrspace(1)* %src2 + + %cvec1 = sext <4 x i8> %vec1 to <4 x i32> + %cvec2 = sext <4 x i8> %vec2 to <4 x i32> + + %mul = mul <4 x i32> %cvec1, %cvec2 + %mul0 = extractelement <4 x i32> %mul, i64 0 + %mul1 = extractelement <4 x i32> %mul, i64 1 + %mul2 = extractelement <4 x i32> %mul, i64 2 + %mul3 = extractelement <4 x i32> %mul, i64 3 + + %acc = load i32, i32 addrspace(1)* %dst, align 4 + %add1 = add i32 %mul0, %acc + %add2 = add i32 %add1, %mul1 + %add3 = add i32 %add2, %mul2 + %add4 = add i32 %add3, %mul3 + + store i32 %add4, i32 addrspace(1)* %dst, align 4 + ret void +} + +; TODO: This pattern should be recognized. +define amdgpu_kernel void @udot4_acc16_vecMul(<4 x i8> addrspace(1)* %src1, +; GFX7-LABEL: udot4_acc16_vecMul: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_movk_i32 s8, 0xff +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 +; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0 +; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_and_b32 s11, s4, s8 +; GFX7-NEXT: s_bfe_u32 s6, s4, 0x80008 +; GFX7-NEXT: s_bfe_u32 s9, s5, 0x80008 +; GFX7-NEXT: s_lshr_b32 s10, s5, 24 +; GFX7-NEXT: s_and_b32 s8, s5, s8 +; GFX7-NEXT: v_mov_b32_e32 v4, s9 +; GFX7-NEXT: s_lshr_b32 s7, s4, 24 +; GFX7-NEXT: v_mov_b32_e32 v2, s10 +; GFX7-NEXT: s_bfe_u32 s5, s5, 0x80010 +; GFX7-NEXT: v_mov_b32_e32 v3, s8 +; GFX7-NEXT: v_mul_u32_u24_e32 v2, s7, v2 +; GFX7-NEXT: v_mul_u32_u24_e32 v4, s6, v4 +; GFX7-NEXT: s_bfe_u32 s4, s4, 0x80010 +; GFX7-NEXT: v_mov_b32_e32 v1, s5 +; GFX7-NEXT: v_mul_u32_u24_e32 v1, s4, v1 +; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GFX7-NEXT: v_mul_u32_u24_e32 v3, s11, v3 +; GFX7-NEXT: v_lshlrev_b32_e32 v4, 16, v4 +; GFX7-NEXT: v_or_b32_e32 v1, v1, v2 +; GFX7-NEXT: v_or_b32_e32 v2, v3, v4 +; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v1 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v3, v0 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v4, v0 +; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: udot4_acc16_vecMul: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ushort v2, v[0:1] +; GFX8-NEXT: s_load_dword s1, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s2, s[6:7], 0x0 +; GFX8-NEXT: s_movk_i32 s0, 0xff +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_and_b32 s6, s1, s0 +; GFX8-NEXT: s_and_b32 s0, s2, s0 +; GFX8-NEXT: v_mov_b32_e32 v5, s0 +; GFX8-NEXT: s_bfe_u32 s7, s2, 0x80010 +; GFX8-NEXT: v_lshrrev_b16_e64 v3, 8, s2 +; GFX8-NEXT: v_lshrrev_b16_e64 v4, 8, s1 +; GFX8-NEXT: s_lshr_b32 s4, s2, 24 +; GFX8-NEXT: s_bfe_u32 s5, s1, 0x80010 +; GFX8-NEXT: v_mov_b32_e32 v6, s7 +; GFX8-NEXT: s_lshr_b32 s3, s1, 24 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_mad_u32_u24 v2, s6, v5, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, v4, v3, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, s5, v6, v2 +; GFX8-NEXT: v_mov_b32_e32 v3, s4 +; GFX8-NEXT: v_mad_u32_u24 v2, s3, v3, v2 +; GFX8-NEXT: flat_store_short v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: udot4_acc16_vecMul: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0xffff +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-NODL-NEXT: s_load_dword s3, s[6:7], 0x0 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_lshr_b32 s5, s2, 16 +; GFX9-NODL-NEXT: s_lshr_b32 s7, s3, 16 +; GFX9-NODL-NEXT: s_lshr_b32 s4, s2, 24 +; GFX9-NODL-NEXT: v_and_b32_sdwa v4, v0, s5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 +; GFX9-NODL-NEXT: s_lshr_b32 s6, s3, 24 +; GFX9-NODL-NEXT: v_and_b32_sdwa v3, v0, s7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 +; GFX9-NODL-NEXT: v_lshl_or_b32 v3, s6, 16, v3 +; GFX9-NODL-NEXT: v_lshl_or_b32 v4, s4, 16, v4 +; GFX9-NODL-NEXT: v_pk_mul_lo_u16 v3, v4, v3 +; GFX9-NODL-NEXT: v_and_b32_sdwa v4, v0, s3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 +; GFX9-NODL-NEXT: v_lshrrev_b16_e64 v2, 8, s3 +; GFX9-NODL-NEXT: v_lshrrev_b16_e64 v1, 8, s2 +; GFX9-NODL-NEXT: v_and_b32_sdwa v0, v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 +; GFX9-NODL-NEXT: v_lshl_or_b32 v2, v2, 16, v4 +; GFX9-NODL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 +; GFX9-NODL-NEXT: v_pk_mul_lo_u16 v2, v0, v2 +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NODL-NEXT: global_load_ushort v4, v[0:1], off +; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) +; GFX9-NODL-NEXT: v_add_u32_e32 v4, v2, v4 +; GFX9-NODL-NEXT: v_add_u32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NODL-NEXT: v_add_u32_e32 v2, v2, v3 +; GFX9-NODL-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NODL-NEXT: global_store_short v[0:1], v2, off +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: udot4_acc16_vecMul: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0xffff +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s3, s[6:7], 0x0 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_lshr_b32 s5, s2, 16 +; GFX9-DL-NEXT: s_lshr_b32 s7, s3, 16 +; GFX9-DL-NEXT: s_lshr_b32 s4, s2, 24 +; GFX9-DL-NEXT: v_and_b32_sdwa v4, v0, s5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 +; GFX9-DL-NEXT: s_lshr_b32 s6, s3, 24 +; GFX9-DL-NEXT: v_and_b32_sdwa v3, v0, s7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 +; GFX9-DL-NEXT: v_lshl_or_b32 v3, s6, 16, v3 +; GFX9-DL-NEXT: v_lshl_or_b32 v4, s4, 16, v4 +; GFX9-DL-NEXT: v_pk_mul_lo_u16 v3, v4, v3 +; GFX9-DL-NEXT: v_and_b32_sdwa v4, v0, s3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 +; GFX9-DL-NEXT: v_lshrrev_b16_e64 v2, 8, s3 +; GFX9-DL-NEXT: v_lshrrev_b16_e64 v1, 8, s2 +; GFX9-DL-NEXT: v_and_b32_sdwa v0, v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0 +; GFX9-DL-NEXT: v_lshl_or_b32 v2, v2, 16, v4 +; GFX9-DL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 +; GFX9-DL-NEXT: v_pk_mul_lo_u16 v2, v0, v2 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_load_ushort v4, v[0:1], off +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_add_u32_e32 v4, v2, v4 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v3 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-DL-NEXT: global_store_short v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm + <4 x i8> addrspace(1)* %src2, + i16 addrspace(1)* nocapture %dst) { +entry: + %vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1 + %vec2 = load <4 x i8>, <4 x i8> addrspace(1)* %src2 + + %cvec1 = zext <4 x i8> %vec1 to <4 x i16> + %cvec2 = zext <4 x i8> %vec2 to <4 x i16> + + %mul = mul <4 x i16> %cvec1, %cvec2 + %mul0 = extractelement <4 x i16> %mul, i64 0 + %mul1 = extractelement <4 x i16> %mul, i64 1 + %mul2 = extractelement <4 x i16> %mul, i64 2 + %mul3 = extractelement <4 x i16> %mul, i64 3 + + %acc = load i16, i16 addrspace(1)* %dst, align 4 + %add1 = add i16 %mul0, %acc + %add2 = add i16 %add1, %mul1 + %add3 = add i16 %add2, %mul2 + %add4 = add i16 %add3, %mul3 + + store i16 %add4, i16 addrspace(1)* %dst, align 4 + ret void +} + +define amdgpu_kernel void @idot4_acc16_vecMul(<4 x i8> addrspace(1)* %src1, +; GFX7-LABEL: idot4_acc16_vecMul: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_mov_b32 s8, 0xffff +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 +; GFX7-NEXT: buffer_load_ushort v0, off, s[0:3], 0 +; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_sext_i32_i8 s6, s4 +; GFX7-NEXT: s_bfe_i32 s7, s4, 0x80008 +; GFX7-NEXT: s_sext_i32_i8 s10, s5 +; GFX7-NEXT: s_bfe_i32 s11, s5, 0x80008 +; GFX7-NEXT: s_bfe_i32 s12, s5, 0x80010 +; GFX7-NEXT: s_ashr_i32 s5, s5, 24 +; GFX7-NEXT: v_mov_b32_e32 v3, s11 +; GFX7-NEXT: v_mov_b32_e32 v4, s10 +; GFX7-NEXT: s_bfe_i32 s9, s4, 0x80010 +; GFX7-NEXT: v_mov_b32_e32 v2, s12 +; GFX7-NEXT: s_ashr_i32 s4, s4, 24 +; GFX7-NEXT: v_mov_b32_e32 v1, s5 +; GFX7-NEXT: v_mul_i32_i24_e32 v1, s4, v1 +; GFX7-NEXT: v_mul_i32_i24_e32 v2, s9, v2 +; GFX7-NEXT: v_mul_i32_i24_e32 v3, s7, v3 +; GFX7-NEXT: v_mul_i32_i24_e32 v4, s6, v4 +; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX7-NEXT: v_and_b32_e32 v2, s8, v2 +; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GFX7-NEXT: v_and_b32_e32 v4, s8, v4 +; GFX7-NEXT: v_or_b32_e32 v1, v2, v1 +; GFX7-NEXT: v_or_b32_e32 v2, v4, v3 +; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v2 +; GFX7-NEXT: v_lshrrev_b32_e32 v4, 16, v1 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v3, v0 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v4, v0 +; GFX7-NEXT: buffer_store_short v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: idot4_acc16_vecMul: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ushort v2, v[0:1] +; GFX8-NEXT: s_load_dword s1, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s2, s[6:7], 0x0 +; GFX8-NEXT: s_mov_b32 s0, 0xffff +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_lshr_b32 s3, s1, 16 +; GFX8-NEXT: s_bfe_i32 s6, s2, 0x80000 +; GFX8-NEXT: s_lshr_b32 s4, s2, 16 +; GFX8-NEXT: s_bfe_i32 s5, s1, 0x80000 +; GFX8-NEXT: v_ashrrev_i16_e64 v4, 8, s1 +; GFX8-NEXT: s_bfe_i32 s1, s3, 0x80000 +; GFX8-NEXT: v_ashrrev_i16_e64 v6, 8, s3 +; GFX8-NEXT: s_and_b32 s3, s0, s6 +; GFX8-NEXT: v_ashrrev_i16_e64 v3, 8, s2 +; GFX8-NEXT: s_bfe_i32 s2, s4, 0x80000 +; GFX8-NEXT: v_ashrrev_i16_e64 v5, 8, s4 +; GFX8-NEXT: s_and_b32 s4, s0, s5 +; GFX8-NEXT: v_mov_b32_e32 v7, s3 +; GFX8-NEXT: s_and_b32 s2, s0, s2 +; GFX8-NEXT: s_and_b32 s0, s0, s1 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_mad_u32_u24 v2, s4, v7, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, v4, v3, v2 +; GFX8-NEXT: v_mov_b32_e32 v3, s2 +; GFX8-NEXT: v_mad_u32_u24 v2, s0, v3, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, v6, v5, v2 +; GFX8-NEXT: flat_store_short v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: idot4_acc16_vecMul: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NODL-NEXT: v_mov_b32_e32 v4, 0xffff +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-NODL-NEXT: s_load_dword s3, s[6:7], 0x0 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_lshr_b32 s4, s2, 16 +; GFX9-NODL-NEXT: s_lshr_b32 s5, s3, 16 +; GFX9-NODL-NEXT: v_ashrrev_i16_e64 v3, 8, s5 +; GFX9-NODL-NEXT: s_bfe_i32 s5, s5, 0x80000 +; GFX9-NODL-NEXT: v_ashrrev_i16_e64 v2, 8, s4 +; GFX9-NODL-NEXT: v_and_b32_e32 v5, s5, v4 +; GFX9-NODL-NEXT: s_bfe_i32 s4, s4, 0x80000 +; GFX9-NODL-NEXT: v_lshl_or_b32 v3, v3, 16, v5 +; GFX9-NODL-NEXT: v_and_b32_e32 v5, s4, v4 +; GFX9-NODL-NEXT: v_lshl_or_b32 v2, v2, 16, v5 +; GFX9-NODL-NEXT: v_ashrrev_i16_e64 v1, 8, s3 +; GFX9-NODL-NEXT: s_bfe_i32 s3, s3, 0x80000 +; GFX9-NODL-NEXT: v_ashrrev_i16_e64 v0, 8, s2 +; GFX9-NODL-NEXT: v_pk_mul_lo_u16 v2, v2, v3 +; GFX9-NODL-NEXT: v_and_b32_e32 v3, s3, v4 +; GFX9-NODL-NEXT: s_bfe_i32 s2, s2, 0x80000 +; GFX9-NODL-NEXT: v_lshl_or_b32 v1, v1, 16, v3 +; GFX9-NODL-NEXT: v_and_b32_e32 v3, s2, v4 +; GFX9-NODL-NEXT: v_lshl_or_b32 v0, v0, 16, v3 +; GFX9-NODL-NEXT: v_pk_mul_lo_u16 v3, v0, v1 +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NODL-NEXT: global_load_ushort v4, v[0:1], off +; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) +; GFX9-NODL-NEXT: v_add_u32_e32 v4, v3, v4 +; GFX9-NODL-NEXT: v_add_u32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NODL-NEXT: v_add_u32_e32 v3, v3, v2 +; GFX9-NODL-NEXT: v_add_u32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NODL-NEXT: global_store_short v[0:1], v2, off +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: idot4_acc16_vecMul: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, 0xffff +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s3, s[6:7], 0x0 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_lshr_b32 s4, s2, 16 +; GFX9-DL-NEXT: s_lshr_b32 s5, s3, 16 +; GFX9-DL-NEXT: v_ashrrev_i16_e64 v3, 8, s5 +; GFX9-DL-NEXT: s_bfe_i32 s5, s5, 0x80000 +; GFX9-DL-NEXT: v_ashrrev_i16_e64 v2, 8, s4 +; GFX9-DL-NEXT: v_and_b32_e32 v5, s5, v4 +; GFX9-DL-NEXT: s_bfe_i32 s4, s4, 0x80000 +; GFX9-DL-NEXT: v_lshl_or_b32 v3, v3, 16, v5 +; GFX9-DL-NEXT: v_and_b32_e32 v5, s4, v4 +; GFX9-DL-NEXT: v_lshl_or_b32 v2, v2, 16, v5 +; GFX9-DL-NEXT: v_ashrrev_i16_e64 v1, 8, s3 +; GFX9-DL-NEXT: s_bfe_i32 s3, s3, 0x80000 +; GFX9-DL-NEXT: v_ashrrev_i16_e64 v0, 8, s2 +; GFX9-DL-NEXT: v_pk_mul_lo_u16 v2, v2, v3 +; GFX9-DL-NEXT: v_and_b32_e32 v3, s3, v4 +; GFX9-DL-NEXT: s_bfe_i32 s2, s2, 0x80000 +; GFX9-DL-NEXT: v_lshl_or_b32 v1, v1, 16, v3 +; GFX9-DL-NEXT: v_and_b32_e32 v3, s2, v4 +; GFX9-DL-NEXT: v_lshl_or_b32 v0, v0, 16, v3 +; GFX9-DL-NEXT: v_pk_mul_lo_u16 v3, v0, v1 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_load_ushort v4, v[0:1], off +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_add_u32_e32 v4, v3, v4 +; GFX9-DL-NEXT: v_add_u32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-DL-NEXT: v_add_u32_e32 v3, v3, v2 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-DL-NEXT: global_store_short v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm + <4 x i8> addrspace(1)* %src2, + i16 addrspace(1)* nocapture %dst) { +entry: + %vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1 + %vec2 = load <4 x i8>, <4 x i8> addrspace(1)* %src2 + + %cvec1 = sext <4 x i8> %vec1 to <4 x i16> + %cvec2 = sext <4 x i8> %vec2 to <4 x i16> + + %mul = mul <4 x i16> %cvec1, %cvec2 + %mul0 = extractelement <4 x i16> %mul, i64 0 + %mul1 = extractelement <4 x i16> %mul, i64 1 + %mul2 = extractelement <4 x i16> %mul, i64 2 + %mul3 = extractelement <4 x i16> %mul, i64 3 + + %acc = load i16, i16 addrspace(1)* %dst, align 4 + %add1 = add i16 %mul0, %acc + %add2 = add i16 %add1, %mul1 + %add3 = add i16 %add2, %mul2 + %add4 = add i16 %add3, %mul3 + + store i16 %add4, i16 addrspace(1)* %dst, align 4 + ret void +} + +; TODO: Support this pattern. +define amdgpu_kernel void @udot4_acc8_vecMul(<4 x i8> addrspace(1)* %src1, +; GFX7-LABEL: udot4_acc8_vecMul: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_movk_i32 s8, 0xff +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s4, s[4:5], 0x0 +; GFX7-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 +; GFX7-NEXT: s_load_dword s5, s[6:7], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_bfe_u32 s6, s4, 0x80008 +; GFX7-NEXT: s_lshr_b32 s7, s4, 16 +; GFX7-NEXT: s_bfe_u32 s10, s5, 0x80008 +; GFX7-NEXT: s_lshr_b32 s11, s5, 16 +; GFX7-NEXT: s_lshr_b32 s12, s5, 24 +; GFX7-NEXT: v_mov_b32_e32 v2, s11 +; GFX7-NEXT: v_mov_b32_e32 v3, s10 +; GFX7-NEXT: s_lshr_b32 s9, s4, 24 +; GFX7-NEXT: v_mov_b32_e32 v1, s12 +; GFX7-NEXT: s_mul_i32 s4, s4, s5 +; GFX7-NEXT: v_mul_u32_u24_e32 v1, s9, v1 +; GFX7-NEXT: v_mul_u32_u24_e32 v2, s7, v2 +; GFX7-NEXT: v_mul_u32_u24_e32 v3, s6, v3 +; GFX7-NEXT: s_and_b32 s4, s4, s8 +; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1 +; GFX7-NEXT: v_and_b32_e32 v2, s8, v2 +; GFX7-NEXT: v_lshlrev_b32_e32 v3, 8, v3 +; GFX7-NEXT: v_or_b32_e32 v1, v2, v1 +; GFX7-NEXT: v_or_b32_e32 v2, s4, v3 +; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GFX7-NEXT: v_or_b32_e32 v1, v2, v1 +; GFX7-NEXT: v_lshrrev_b32_e32 v2, 8, v1 +; GFX7-NEXT: v_lshrrev_b32_e32 v3, 16, v1 +; GFX7-NEXT: v_lshrrev_b32_e32 v4, 24, v1 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v2, v0 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v3, v0 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v4, v0 +; GFX7-NEXT: buffer_store_byte v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: udot4_acc8_vecMul: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ubyte v2, v[0:1] +; GFX8-NEXT: s_load_dword s1, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s2, s[6:7], 0x0 +; GFX8-NEXT: s_movk_i32 s0, 0xff +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_lshr_b32 s3, s1, 24 +; GFX8-NEXT: s_lshr_b32 s4, s2, 24 +; GFX8-NEXT: s_and_b32 s6, s1, s0 +; GFX8-NEXT: s_bfe_u32 s7, s2, 0x80010 +; GFX8-NEXT: s_and_b32 s0, s2, s0 +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_mov_b32_e32 v4, s2 +; GFX8-NEXT: v_mul_u32_u24_sdwa v3, v3, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1 +; GFX8-NEXT: v_mov_b32_e32 v4, s0 +; GFX8-NEXT: s_bfe_u32 s5, s1, 0x80010 +; GFX8-NEXT: v_mov_b32_e32 v5, s7 +; GFX8-NEXT: v_mov_b32_e32 v6, s4 +; GFX8-NEXT: v_mov_b32_e32 v7, s3 +; GFX8-NEXT: v_mul_u32_u24_e32 v4, s6, v4 +; GFX8-NEXT: v_mul_u32_u24_e32 v5, s5, v5 +; GFX8-NEXT: v_mul_u32_u24_sdwa v6, v7, v6 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v3, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_lshrrev_b32_e32 v4, 8, v3 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3 +; GFX8-NEXT: v_add_u32_e32 v2, vcc, v4, v2 +; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD +; GFX8-NEXT: flat_store_byte v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: udot4_acc8_vecMul: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-NODL-NEXT: s_load_dword s3, s[6:7], 0x0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NODL-NEXT: global_load_ubyte v2, v[0:1], off +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: s_lshr_b32 s0, s2, 16 +; GFX9-NODL-NEXT: v_mov_b32_e32 v3, s3 +; GFX9-NODL-NEXT: v_mov_b32_e32 v4, s3 +; GFX9-NODL-NEXT: s_lshr_b32 s1, s3, 16 +; GFX9-NODL-NEXT: s_lshr_b32 s4, s3, 24 +; GFX9-NODL-NEXT: v_mul_lo_u16_e32 v3, s2, v3 +; GFX9-NODL-NEXT: v_mul_lo_u16_sdwa v4, s2, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1 +; GFX9-NODL-NEXT: v_mov_b32_e32 v5, s1 +; GFX9-NODL-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NODL-NEXT: s_lshr_b32 s5, s2, 24 +; GFX9-NODL-NEXT: v_mov_b32_e32 v4, s4 +; GFX9-NODL-NEXT: v_mul_lo_u16_sdwa v4, s5, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9-NODL-NEXT: v_mul_lo_u16_e32 v5, s0, v5 +; GFX9-NODL-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NODL-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v4, 8, v3 +; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) +; GFX9-NODL-NEXT: v_add_u32_e32 v2, v3, v2 +; GFX9-NODL-NEXT: v_add_u32_e32 v2, v2, v4 +; GFX9-NODL-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NODL-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 +; GFX9-NODL-NEXT: global_store_byte v[0:1], v2, off +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: udot4_acc8_vecMul: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s3, s[6:7], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_load_ubyte v2, v[0:1], off +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_lshr_b32 s0, s2, 16 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s3 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s3 +; GFX9-DL-NEXT: s_lshr_b32 s1, s3, 16 +; GFX9-DL-NEXT: s_lshr_b32 s4, s3, 24 +; GFX9-DL-NEXT: v_mul_lo_u16_e32 v3, s2, v3 +; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v4, s2, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1 +; GFX9-DL-NEXT: v_mov_b32_e32 v5, s1 +; GFX9-DL-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-DL-NEXT: s_lshr_b32 s5, s2, 24 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s4 +; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v4, s5, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9-DL-NEXT: v_mul_lo_u16_e32 v5, s0, v5 +; GFX9-DL-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-DL-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-DL-NEXT: v_lshrrev_b32_e32 v4, 8, v3 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_add_u32_e32 v2, v3, v2 +; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v4 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 +; GFX9-DL-NEXT: global_store_byte v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm + <4 x i8> addrspace(1)* %src2, + i8 addrspace(1)* nocapture %dst) { +entry: + %vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %src1 + %vec2 = load <4 x i8>, <4 x i8> addrspace(1)* %src2 + + %mul = mul <4 x i8> %vec1, %vec2 + %mul0 = extractelement <4 x i8> %mul, i64 0 + %mul1 = extractelement <4 x i8> %mul, i64 1 + %mul2 = extractelement <4 x i8> %mul, i64 2 + %mul3 = extractelement <4 x i8> %mul, i64 3 + + %acc = load i8, i8 addrspace(1)* %dst, align 4 + %add1 = add i8 %mul0, %acc + %add2 = add i8 %add1, %mul1 + %add3 = add i8 %add2, %mul2 + %add4 = add i8 %add3, %mul3 + + store i8 %add4, i8 addrspace(1)* %dst, align 4 + ret void +} Index: test/CodeGen/AMDGPU/idot8.ll =================================================================== --- test/CodeGen/AMDGPU/idot8.ll +++ test/CodeGen/AMDGPU/idot8.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX7 %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8 %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN-DL %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9-DL %s define amdgpu_kernel void @udot8_acc32(<8 x i4> addrspace(1)* %src1, ; GFX7-LABEL: udot8_acc32: @@ -146,22 +146,22 @@ ; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: s_endpgm ; -; GCN-DL-LABEL: udot8_acc32: -; GCN-DL: ; %bb.0: ; %entry -; GCN-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GCN-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GCN-DL-NEXT: s_load_dword s4, s[6:7], 0x0 -; GCN-DL-NEXT: s_load_dword s5, s[0:1], 0x0 -; GCN-DL-NEXT: v_mov_b32_e32 v0, s0 -; GCN-DL-NEXT: v_mov_b32_e32 v1, s1 -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: v_mov_b32_e32 v2, s4 -; GCN-DL-NEXT: v_mov_b32_e32 v3, s5 -; GCN-DL-NEXT: v_dot8_u32_u4 v2, s2, v2, v3 -; GCN-DL-NEXT: global_store_dword v[0:1], v2, off -; GCN-DL-NEXT: s_endpgm +; GFX9-DL-LABEL: udot8_acc32: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-DL-NEXT: s_load_dword s5, s[0:1], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-DL-NEXT: v_dot8_u32_u4 v2, s2, v2, v3 +; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm <8 x i4> addrspace(1)* %src2, i32 addrspace(1)* nocapture %dst) { entry: @@ -376,53 +376,53 @@ ; GFX9-NEXT: global_store_short v[0:1], v2, off ; GFX9-NEXT: s_endpgm ; -; GCN-DL-LABEL: udot8_acc16: -; GCN-DL: ; %bb.0: ; %entry -; GCN-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GCN-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GCN-DL-NEXT: s_load_dword s4, s[6:7], 0x0 -; GCN-DL-NEXT: v_mov_b32_e32 v0, s0 -; GCN-DL-NEXT: v_mov_b32_e32 v1, s1 -; GCN-DL-NEXT: global_load_ushort v2, v[0:1], off -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: s_and_b32 s0, s2, 15 -; GCN-DL-NEXT: s_and_b32 s1, s4, 15 -; GCN-DL-NEXT: v_mov_b32_e32 v3, s1 -; GCN-DL-NEXT: s_bfe_u32 s5, s4, 0x40004 -; GCN-DL-NEXT: v_mov_b32_e32 v4, s5 -; GCN-DL-NEXT: s_bfe_u32 s1, s2, 0x40004 -; GCN-DL-NEXT: s_bfe_u32 s5, s4, 0x40008 -; GCN-DL-NEXT: s_bfe_u32 s8, s4, 0x40010 -; GCN-DL-NEXT: s_bfe_u32 s10, s4, 0x40014 -; GCN-DL-NEXT: s_bfe_u32 s12, s4, 0x40018 -; GCN-DL-NEXT: s_lshr_b32 s14, s4, 28 -; GCN-DL-NEXT: s_bfe_u32 s4, s4, 0x4000c -; GCN-DL-NEXT: s_bfe_u32 s6, s2, 0x40008 -; GCN-DL-NEXT: v_mov_b32_e32 v5, s5 -; GCN-DL-NEXT: s_bfe_u32 s7, s2, 0x4000c -; GCN-DL-NEXT: v_mov_b32_e32 v6, s4 -; GCN-DL-NEXT: s_bfe_u32 s9, s2, 0x40010 -; GCN-DL-NEXT: v_mov_b32_e32 v7, s8 -; GCN-DL-NEXT: s_bfe_u32 s11, s2, 0x40014 -; GCN-DL-NEXT: v_mov_b32_e32 v8, s10 -; GCN-DL-NEXT: s_bfe_u32 s13, s2, 0x40018 -; GCN-DL-NEXT: v_mov_b32_e32 v9, s12 -; GCN-DL-NEXT: s_lshr_b32 s2, s2, 28 -; GCN-DL-NEXT: s_waitcnt vmcnt(0) -; GCN-DL-NEXT: v_mad_u32_u24 v2, s0, v3, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s1, v4, v2 -; GCN-DL-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s6, v5, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s7, v6, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s9, v7, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s11, v8, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s13, v9, v2 -; GCN-DL-NEXT: v_mov_b32_e32 v3, s14 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s2, v3, v2 -; GCN-DL-NEXT: global_store_short v[0:1], v2, off -; GCN-DL-NEXT: s_endpgm +; GFX9-DL-LABEL: udot8_acc16: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_load_ushort v2, v[0:1], off +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_and_b32 s0, s2, 15 +; GFX9-DL-NEXT: s_and_b32 s1, s4, 15 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-DL-NEXT: s_bfe_u32 s5, s4, 0x40004 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s5 +; GFX9-DL-NEXT: s_bfe_u32 s1, s2, 0x40004 +; GFX9-DL-NEXT: s_bfe_u32 s5, s4, 0x40008 +; GFX9-DL-NEXT: s_bfe_u32 s8, s4, 0x40010 +; GFX9-DL-NEXT: s_bfe_u32 s10, s4, 0x40014 +; GFX9-DL-NEXT: s_bfe_u32 s12, s4, 0x40018 +; GFX9-DL-NEXT: s_lshr_b32 s14, s4, 28 +; GFX9-DL-NEXT: s_bfe_u32 s4, s4, 0x4000c +; GFX9-DL-NEXT: s_bfe_u32 s6, s2, 0x40008 +; GFX9-DL-NEXT: v_mov_b32_e32 v5, s5 +; GFX9-DL-NEXT: s_bfe_u32 s7, s2, 0x4000c +; GFX9-DL-NEXT: v_mov_b32_e32 v6, s4 +; GFX9-DL-NEXT: s_bfe_u32 s9, s2, 0x40010 +; GFX9-DL-NEXT: v_mov_b32_e32 v7, s8 +; GFX9-DL-NEXT: s_bfe_u32 s11, s2, 0x40014 +; GFX9-DL-NEXT: v_mov_b32_e32 v8, s10 +; GFX9-DL-NEXT: s_bfe_u32 s13, s2, 0x40018 +; GFX9-DL-NEXT: v_mov_b32_e32 v9, s12 +; GFX9-DL-NEXT: s_lshr_b32 s2, s2, 28 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s0, v3, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s1, v4, v2 +; GFX9-DL-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s6, v5, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s7, v6, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s9, v7, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s11, v8, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s13, v9, v2 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s14 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s2, v3, v2 +; GFX9-DL-NEXT: global_store_short v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm <8 x i4> addrspace(1)* %src2, i16 addrspace(1)* nocapture %dst) { entry: @@ -637,53 +637,53 @@ ; GFX9-NEXT: global_store_byte v[0:1], v2, off ; GFX9-NEXT: s_endpgm ; -; GCN-DL-LABEL: udot8_acc8: -; GCN-DL: ; %bb.0: ; %entry -; GCN-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GCN-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GCN-DL-NEXT: s_load_dword s4, s[6:7], 0x0 -; GCN-DL-NEXT: v_mov_b32_e32 v0, s0 -; GCN-DL-NEXT: v_mov_b32_e32 v1, s1 -; GCN-DL-NEXT: global_load_ubyte v2, v[0:1], off -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: s_and_b32 s0, s2, 15 -; GCN-DL-NEXT: s_and_b32 s1, s4, 15 -; GCN-DL-NEXT: v_mov_b32_e32 v3, s1 -; GCN-DL-NEXT: s_bfe_u32 s5, s4, 0x40004 -; GCN-DL-NEXT: v_mov_b32_e32 v4, s5 -; GCN-DL-NEXT: s_bfe_u32 s1, s2, 0x40004 -; GCN-DL-NEXT: s_bfe_u32 s5, s4, 0x40008 -; GCN-DL-NEXT: s_bfe_u32 s8, s4, 0x40010 -; GCN-DL-NEXT: s_bfe_u32 s10, s4, 0x40014 -; GCN-DL-NEXT: s_bfe_u32 s12, s4, 0x40018 -; GCN-DL-NEXT: s_lshr_b32 s14, s4, 28 -; GCN-DL-NEXT: s_bfe_u32 s4, s4, 0x4000c -; GCN-DL-NEXT: s_bfe_u32 s6, s2, 0x40008 -; GCN-DL-NEXT: v_mov_b32_e32 v5, s5 -; GCN-DL-NEXT: s_bfe_u32 s7, s2, 0x4000c -; GCN-DL-NEXT: v_mov_b32_e32 v6, s4 -; GCN-DL-NEXT: s_bfe_u32 s9, s2, 0x40010 -; GCN-DL-NEXT: v_mov_b32_e32 v7, s8 -; GCN-DL-NEXT: s_bfe_u32 s11, s2, 0x40014 -; GCN-DL-NEXT: v_mov_b32_e32 v8, s10 -; GCN-DL-NEXT: s_bfe_u32 s13, s2, 0x40018 -; GCN-DL-NEXT: v_mov_b32_e32 v9, s12 -; GCN-DL-NEXT: s_lshr_b32 s2, s2, 28 -; GCN-DL-NEXT: s_waitcnt vmcnt(0) -; GCN-DL-NEXT: v_mad_u32_u24 v2, s0, v3, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s1, v4, v2 -; GCN-DL-NEXT: v_and_b32_e32 v2, 0xff, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s6, v5, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s7, v6, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s9, v7, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s11, v8, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s13, v9, v2 -; GCN-DL-NEXT: v_mov_b32_e32 v3, s14 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s2, v3, v2 -; GCN-DL-NEXT: global_store_byte v[0:1], v2, off -; GCN-DL-NEXT: s_endpgm +; GFX9-DL-LABEL: udot8_acc8: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_load_ubyte v2, v[0:1], off +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_and_b32 s0, s2, 15 +; GFX9-DL-NEXT: s_and_b32 s1, s4, 15 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-DL-NEXT: s_bfe_u32 s5, s4, 0x40004 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s5 +; GFX9-DL-NEXT: s_bfe_u32 s1, s2, 0x40004 +; GFX9-DL-NEXT: s_bfe_u32 s5, s4, 0x40008 +; GFX9-DL-NEXT: s_bfe_u32 s8, s4, 0x40010 +; GFX9-DL-NEXT: s_bfe_u32 s10, s4, 0x40014 +; GFX9-DL-NEXT: s_bfe_u32 s12, s4, 0x40018 +; GFX9-DL-NEXT: s_lshr_b32 s14, s4, 28 +; GFX9-DL-NEXT: s_bfe_u32 s4, s4, 0x4000c +; GFX9-DL-NEXT: s_bfe_u32 s6, s2, 0x40008 +; GFX9-DL-NEXT: v_mov_b32_e32 v5, s5 +; GFX9-DL-NEXT: s_bfe_u32 s7, s2, 0x4000c +; GFX9-DL-NEXT: v_mov_b32_e32 v6, s4 +; GFX9-DL-NEXT: s_bfe_u32 s9, s2, 0x40010 +; GFX9-DL-NEXT: v_mov_b32_e32 v7, s8 +; GFX9-DL-NEXT: s_bfe_u32 s11, s2, 0x40014 +; GFX9-DL-NEXT: v_mov_b32_e32 v8, s10 +; GFX9-DL-NEXT: s_bfe_u32 s13, s2, 0x40018 +; GFX9-DL-NEXT: v_mov_b32_e32 v9, s12 +; GFX9-DL-NEXT: s_lshr_b32 s2, s2, 28 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s0, v3, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s1, v4, v2 +; GFX9-DL-NEXT: v_and_b32_e32 v2, 0xff, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s6, v5, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s7, v6, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s9, v7, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s11, v8, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s13, v9, v2 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s14 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s2, v3, v2 +; GFX9-DL-NEXT: global_store_byte v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm <8 x i4> addrspace(1)* %src2, i8 addrspace(1)* nocapture %dst) { entry: @@ -905,56 +905,56 @@ ; GFX9-NEXT: global_store_byte v[0:1], v2, off ; GFX9-NEXT: s_endpgm ; -; GCN-DL-LABEL: udot8_acc4: -; GCN-DL: ; %bb.0: ; %entry -; GCN-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GCN-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GCN-DL-NEXT: s_load_dword s4, s[6:7], 0x0 -; GCN-DL-NEXT: v_mov_b32_e32 v0, s0 -; GCN-DL-NEXT: v_mov_b32_e32 v1, s1 -; GCN-DL-NEXT: global_load_ubyte v2, v[0:1], off -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: s_and_b32 s0, s2, 15 -; GCN-DL-NEXT: s_and_b32 s1, s4, 15 -; GCN-DL-NEXT: v_mov_b32_e32 v3, s1 -; GCN-DL-NEXT: s_bfe_u32 s5, s4, 0x40004 -; GCN-DL-NEXT: s_bfe_u32 s6, s4, 0x40008 -; GCN-DL-NEXT: v_mov_b32_e32 v4, s6 -; GCN-DL-NEXT: s_bfe_u32 s7, s2, 0x40008 -; GCN-DL-NEXT: v_mov_b32_e32 v5, s5 -; GCN-DL-NEXT: s_bfe_u32 s1, s2, 0x40004 -; GCN-DL-NEXT: v_mul_u32_u24_e32 v4, s7, v4 -; GCN-DL-NEXT: s_bfe_u32 s5, s4, 0x4000c -; GCN-DL-NEXT: v_and_b32_e32 v4, 15, v4 -; GCN-DL-NEXT: s_bfe_u32 s7, s4, 0x40010 -; GCN-DL-NEXT: v_mov_b32_e32 v6, s5 -; GCN-DL-NEXT: s_bfe_u32 s6, s2, 0x4000c -; GCN-DL-NEXT: s_bfe_u32 s8, s4, 0x40014 -; GCN-DL-NEXT: v_mov_b32_e32 v7, s7 -; GCN-DL-NEXT: s_bfe_u32 s5, s2, 0x40010 -; GCN-DL-NEXT: s_bfe_u32 s9, s4, 0x40018 -; GCN-DL-NEXT: v_mov_b32_e32 v8, s8 -; GCN-DL-NEXT: s_bfe_u32 s7, s2, 0x40014 -; GCN-DL-NEXT: s_bfe_u32 s8, s2, 0x40018 -; GCN-DL-NEXT: s_lshr_b32 s4, s4, 28 -; GCN-DL-NEXT: v_mov_b32_e32 v9, s9 -; GCN-DL-NEXT: s_lshr_b32 s2, s2, 28 -; GCN-DL-NEXT: s_waitcnt vmcnt(0) -; GCN-DL-NEXT: v_mad_u32_u24 v2, s0, v3, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s1, v5, v2 -; GCN-DL-NEXT: v_and_b32_e32 v2, 15, v2 -; GCN-DL-NEXT: v_add_u32_e32 v2, v2, v4 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s6, v6, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s5, v7, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s7, v8, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s8, v9, v2 -; GCN-DL-NEXT: v_mov_b32_e32 v3, s4 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s2, v3, v2 -; GCN-DL-NEXT: v_and_b32_e32 v2, 15, v2 -; GCN-DL-NEXT: global_store_byte v[0:1], v2, off -; GCN-DL-NEXT: s_endpgm +; GFX9-DL-LABEL: udot8_acc4: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_load_ubyte v2, v[0:1], off +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_and_b32 s0, s2, 15 +; GFX9-DL-NEXT: s_and_b32 s1, s4, 15 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-DL-NEXT: s_bfe_u32 s5, s4, 0x40004 +; GFX9-DL-NEXT: s_bfe_u32 s6, s4, 0x40008 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s6 +; GFX9-DL-NEXT: s_bfe_u32 s7, s2, 0x40008 +; GFX9-DL-NEXT: v_mov_b32_e32 v5, s5 +; GFX9-DL-NEXT: s_bfe_u32 s1, s2, 0x40004 +; GFX9-DL-NEXT: v_mul_u32_u24_e32 v4, s7, v4 +; GFX9-DL-NEXT: s_bfe_u32 s5, s4, 0x4000c +; GFX9-DL-NEXT: v_and_b32_e32 v4, 15, v4 +; GFX9-DL-NEXT: s_bfe_u32 s7, s4, 0x40010 +; GFX9-DL-NEXT: v_mov_b32_e32 v6, s5 +; GFX9-DL-NEXT: s_bfe_u32 s6, s2, 0x4000c +; GFX9-DL-NEXT: s_bfe_u32 s8, s4, 0x40014 +; GFX9-DL-NEXT: v_mov_b32_e32 v7, s7 +; GFX9-DL-NEXT: s_bfe_u32 s5, s2, 0x40010 +; GFX9-DL-NEXT: s_bfe_u32 s9, s4, 0x40018 +; GFX9-DL-NEXT: v_mov_b32_e32 v8, s8 +; GFX9-DL-NEXT: s_bfe_u32 s7, s2, 0x40014 +; GFX9-DL-NEXT: s_bfe_u32 s8, s2, 0x40018 +; GFX9-DL-NEXT: s_lshr_b32 s4, s4, 28 +; GFX9-DL-NEXT: v_mov_b32_e32 v9, s9 +; GFX9-DL-NEXT: s_lshr_b32 s2, s2, 28 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s0, v3, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s1, v5, v2 +; GFX9-DL-NEXT: v_and_b32_e32 v2, 15, v2 +; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v4 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s6, v6, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s5, v7, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s7, v8, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s8, v9, v2 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s4 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s2, v3, v2 +; GFX9-DL-NEXT: v_and_b32_e32 v2, 15, v2 +; GFX9-DL-NEXT: global_store_byte v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm <8 x i4> addrspace(1)* %src2, i4 addrspace(1)* nocapture %dst) { entry: @@ -1154,53 +1154,53 @@ ; GFX9-NEXT: global_store_byte v[0:1], v2, off ; GFX9-NEXT: s_endpgm ; -; GCN-DL-LABEL: udot8_CommutationInsideMAD: -; GCN-DL: ; %bb.0: ; %entry -; GCN-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GCN-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GCN-DL-NEXT: s_load_dword s4, s[6:7], 0x0 -; GCN-DL-NEXT: v_mov_b32_e32 v0, s0 -; GCN-DL-NEXT: v_mov_b32_e32 v1, s1 -; GCN-DL-NEXT: global_load_ubyte v2, v[0:1], off -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: s_and_b32 s0, s2, 15 -; GCN-DL-NEXT: s_and_b32 s1, s4, 15 -; GCN-DL-NEXT: v_mov_b32_e32 v3, s1 -; GCN-DL-NEXT: s_bfe_u32 s5, s4, 0x40004 -; GCN-DL-NEXT: s_bfe_u32 s6, s4, 0x40008 -; GCN-DL-NEXT: v_mov_b32_e32 v4, s5 -; GCN-DL-NEXT: s_bfe_u32 s1, s2, 0x40004 -; GCN-DL-NEXT: s_bfe_u32 s7, s4, 0x4000c -; GCN-DL-NEXT: v_mov_b32_e32 v5, s6 -; GCN-DL-NEXT: s_bfe_u32 s5, s2, 0x40008 -; GCN-DL-NEXT: s_bfe_u32 s8, s4, 0x40010 -; GCN-DL-NEXT: v_mov_b32_e32 v6, s7 -; GCN-DL-NEXT: s_bfe_u32 s6, s2, 0x4000c -; GCN-DL-NEXT: s_bfe_u32 s9, s4, 0x40014 -; GCN-DL-NEXT: v_mov_b32_e32 v7, s8 -; GCN-DL-NEXT: s_bfe_u32 s7, s2, 0x40010 -; GCN-DL-NEXT: s_bfe_u32 s10, s4, 0x40018 -; GCN-DL-NEXT: v_mov_b32_e32 v8, s9 -; GCN-DL-NEXT: s_bfe_u32 s8, s2, 0x40014 -; GCN-DL-NEXT: s_bfe_u32 s9, s2, 0x40018 -; GCN-DL-NEXT: s_lshr_b32 s4, s4, 28 -; GCN-DL-NEXT: v_mov_b32_e32 v9, s10 -; GCN-DL-NEXT: s_lshr_b32 s2, s2, 28 -; GCN-DL-NEXT: s_waitcnt vmcnt(0) -; GCN-DL-NEXT: v_mad_u32_u24 v2, s0, v3, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s1, v4, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s5, v5, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s6, v6, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s7, v7, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s8, v8, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s9, v9, v2 -; GCN-DL-NEXT: v_mov_b32_e32 v3, s4 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s2, v3, v2 -; GCN-DL-NEXT: v_and_b32_e32 v2, 15, v2 -; GCN-DL-NEXT: global_store_byte v[0:1], v2, off -; GCN-DL-NEXT: s_endpgm +; GFX9-DL-LABEL: udot8_CommutationInsideMAD: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_load_ubyte v2, v[0:1], off +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_and_b32 s0, s2, 15 +; GFX9-DL-NEXT: s_and_b32 s1, s4, 15 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-DL-NEXT: s_bfe_u32 s5, s4, 0x40004 +; GFX9-DL-NEXT: s_bfe_u32 s6, s4, 0x40008 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s5 +; GFX9-DL-NEXT: s_bfe_u32 s1, s2, 0x40004 +; GFX9-DL-NEXT: s_bfe_u32 s7, s4, 0x4000c +; GFX9-DL-NEXT: v_mov_b32_e32 v5, s6 +; GFX9-DL-NEXT: s_bfe_u32 s5, s2, 0x40008 +; GFX9-DL-NEXT: s_bfe_u32 s8, s4, 0x40010 +; GFX9-DL-NEXT: v_mov_b32_e32 v6, s7 +; GFX9-DL-NEXT: s_bfe_u32 s6, s2, 0x4000c +; GFX9-DL-NEXT: s_bfe_u32 s9, s4, 0x40014 +; GFX9-DL-NEXT: v_mov_b32_e32 v7, s8 +; GFX9-DL-NEXT: s_bfe_u32 s7, s2, 0x40010 +; GFX9-DL-NEXT: s_bfe_u32 s10, s4, 0x40018 +; GFX9-DL-NEXT: v_mov_b32_e32 v8, s9 +; GFX9-DL-NEXT: s_bfe_u32 s8, s2, 0x40014 +; GFX9-DL-NEXT: s_bfe_u32 s9, s2, 0x40018 +; GFX9-DL-NEXT: s_lshr_b32 s4, s4, 28 +; GFX9-DL-NEXT: v_mov_b32_e32 v9, s10 +; GFX9-DL-NEXT: s_lshr_b32 s2, s2, 28 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s0, v3, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s1, v4, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s5, v5, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s6, v6, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s7, v7, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s8, v8, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s9, v9, v2 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s4 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s2, v3, v2 +; GFX9-DL-NEXT: v_and_b32_e32 v2, 15, v2 +; GFX9-DL-NEXT: global_store_byte v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm <8 x i4> addrspace(1)* %src2, i4 addrspace(1)* nocapture %dst) { entry: @@ -1401,54 +1401,54 @@ ; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: s_endpgm ; -; GCN-DL-LABEL: udot8_multiuses_mul1: -; GCN-DL: ; %bb.0: ; %entry -; GCN-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GCN-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GCN-DL-NEXT: s_load_dword s4, s[6:7], 0x0 -; GCN-DL-NEXT: s_load_dword s5, s[0:1], 0x0 -; GCN-DL-NEXT: v_mov_b32_e32 v0, s0 -; GCN-DL-NEXT: v_mov_b32_e32 v1, s1 -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: s_lshr_b32 s0, s2, 28 -; GCN-DL-NEXT: s_bfe_u32 s17, s4, 0x40004 -; GCN-DL-NEXT: s_lshr_b32 s11, s4, 28 -; GCN-DL-NEXT: s_bfe_u32 s12, s4, 0x40018 -; GCN-DL-NEXT: s_bfe_u32 s13, s4, 0x40014 -; GCN-DL-NEXT: s_bfe_u32 s14, s4, 0x40010 -; GCN-DL-NEXT: s_bfe_u32 s15, s4, 0x4000c -; GCN-DL-NEXT: s_bfe_u32 s16, s4, 0x40008 -; GCN-DL-NEXT: s_and_b32 s4, s4, 15 -; GCN-DL-NEXT: s_bfe_u32 s1, s2, 0x40018 -; GCN-DL-NEXT: s_bfe_u32 s6, s2, 0x40014 -; GCN-DL-NEXT: s_bfe_u32 s7, s2, 0x40010 -; GCN-DL-NEXT: s_bfe_u32 s8, s2, 0x4000c -; GCN-DL-NEXT: s_bfe_u32 s9, s2, 0x40008 -; GCN-DL-NEXT: s_bfe_u32 s10, s2, 0x40004 -; GCN-DL-NEXT: s_and_b32 s2, s2, 15 -; GCN-DL-NEXT: v_mov_b32_e32 v2, s4 -; GCN-DL-NEXT: v_mov_b32_e32 v3, s5 -; GCN-DL-NEXT: v_mad_u32_u24 v3, s2, v2, v3 -; GCN-DL-NEXT: v_mov_b32_e32 v4, s17 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s2, v2, v3 -; GCN-DL-NEXT: v_mad_u32_u24 v3, s10, v4, v3 -; GCN-DL-NEXT: v_mov_b32_e32 v4, s16 -; GCN-DL-NEXT: v_mad_u32_u24 v3, s9, v4, v3 -; GCN-DL-NEXT: v_mov_b32_e32 v4, s15 -; GCN-DL-NEXT: v_mad_u32_u24 v3, s8, v4, v3 -; GCN-DL-NEXT: v_mov_b32_e32 v4, s14 -; GCN-DL-NEXT: v_mad_u32_u24 v3, s7, v4, v3 -; GCN-DL-NEXT: v_mov_b32_e32 v4, s13 -; GCN-DL-NEXT: v_mad_u32_u24 v3, s6, v4, v3 -; GCN-DL-NEXT: v_mov_b32_e32 v4, s12 -; GCN-DL-NEXT: v_mad_u32_u24 v3, s1, v4, v3 -; GCN-DL-NEXT: v_mov_b32_e32 v4, s11 -; GCN-DL-NEXT: v_mad_u32_u24 v3, s0, v4, v3 -; GCN-DL-NEXT: v_add_u32_e32 v2, v2, v3 -; GCN-DL-NEXT: global_store_dword v[0:1], v2, off -; GCN-DL-NEXT: s_endpgm +; GFX9-DL-LABEL: udot8_multiuses_mul1: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-DL-NEXT: s_load_dword s5, s[0:1], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_lshr_b32 s0, s2, 28 +; GFX9-DL-NEXT: s_bfe_u32 s17, s4, 0x40004 +; GFX9-DL-NEXT: s_lshr_b32 s11, s4, 28 +; GFX9-DL-NEXT: s_bfe_u32 s12, s4, 0x40018 +; GFX9-DL-NEXT: s_bfe_u32 s13, s4, 0x40014 +; GFX9-DL-NEXT: s_bfe_u32 s14, s4, 0x40010 +; GFX9-DL-NEXT: s_bfe_u32 s15, s4, 0x4000c +; GFX9-DL-NEXT: s_bfe_u32 s16, s4, 0x40008 +; GFX9-DL-NEXT: s_and_b32 s4, s4, 15 +; GFX9-DL-NEXT: s_bfe_u32 s1, s2, 0x40018 +; GFX9-DL-NEXT: s_bfe_u32 s6, s2, 0x40014 +; GFX9-DL-NEXT: s_bfe_u32 s7, s2, 0x40010 +; GFX9-DL-NEXT: s_bfe_u32 s8, s2, 0x4000c +; GFX9-DL-NEXT: s_bfe_u32 s9, s2, 0x40008 +; GFX9-DL-NEXT: s_bfe_u32 s10, s2, 0x40004 +; GFX9-DL-NEXT: s_and_b32 s2, s2, 15 +; GFX9-DL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-DL-NEXT: v_mad_u32_u24 v3, s2, v2, v3 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s17 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s2, v2, v3 +; GFX9-DL-NEXT: v_mad_u32_u24 v3, s10, v4, v3 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s16 +; GFX9-DL-NEXT: v_mad_u32_u24 v3, s9, v4, v3 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s15 +; GFX9-DL-NEXT: v_mad_u32_u24 v3, s8, v4, v3 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s14 +; GFX9-DL-NEXT: v_mad_u32_u24 v3, s7, v4, v3 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s13 +; GFX9-DL-NEXT: v_mad_u32_u24 v3, s6, v4, v3 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s12 +; GFX9-DL-NEXT: v_mad_u32_u24 v3, s1, v4, v3 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s11 +; GFX9-DL-NEXT: v_mad_u32_u24 v3, s0, v4, v3 +; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v3 +; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm <8 x i4> addrspace(1)* %src2, i32 addrspace(1)* nocapture %dst) { entry: @@ -1661,22 +1661,22 @@ ; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: s_endpgm ; -; GCN-DL-LABEL: udot8_acc32_vecMul: -; GCN-DL: ; %bb.0: ; %entry -; GCN-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GCN-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GCN-DL-NEXT: s_load_dword s4, s[6:7], 0x0 -; GCN-DL-NEXT: s_load_dword s5, s[0:1], 0x0 -; GCN-DL-NEXT: v_mov_b32_e32 v0, s0 -; GCN-DL-NEXT: v_mov_b32_e32 v1, s1 -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: v_mov_b32_e32 v2, s4 -; GCN-DL-NEXT: v_mov_b32_e32 v3, s5 -; GCN-DL-NEXT: v_dot8_u32_u4 v2, s2, v2, v3 -; GCN-DL-NEXT: global_store_dword v[0:1], v2, off -; GCN-DL-NEXT: s_endpgm +; GFX9-DL-LABEL: udot8_acc32_vecMul: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-DL-NEXT: s_load_dword s5, s[0:1], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-DL-NEXT: v_dot8_u32_u4 v2, s2, v2, v3 +; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm <8 x i4> addrspace(1)* %src2, i32 addrspace(1)* nocapture %dst) { entry: @@ -1883,60 +1883,60 @@ ; GFX9-NEXT: global_store_short v[0:1], v2, off ; GFX9-NEXT: s_endpgm ; -; GCN-DL-LABEL: udot8_acc16_vecMul: -; GCN-DL: ; %bb.0: ; %entry -; GCN-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GCN-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GCN-DL-NEXT: s_load_dword s4, s[6:7], 0x0 -; GCN-DL-NEXT: v_mov_b32_e32 v0, s0 -; GCN-DL-NEXT: v_mov_b32_e32 v1, s1 -; GCN-DL-NEXT: global_load_ushort v2, v[0:1], off -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: s_and_b32 s0, s2, 15 -; GCN-DL-NEXT: s_and_b32 s1, s4, 15 -; GCN-DL-NEXT: s_bfe_u32 s5, s4, 0x40004 -; GCN-DL-NEXT: s_pack_ll_b32_b16 s1, s1, s5 -; GCN-DL-NEXT: s_bfe_u32 s6, s2, 0x40004 -; GCN-DL-NEXT: s_pack_ll_b32_b16 s0, s0, s6 -; GCN-DL-NEXT: v_mov_b32_e32 v3, s1 -; GCN-DL-NEXT: s_bfe_u32 s5, s4, 0x40008 -; GCN-DL-NEXT: s_bfe_u32 s7, s4, 0x4000c -; GCN-DL-NEXT: s_pack_ll_b32_b16 s5, s5, s7 -; GCN-DL-NEXT: v_pk_mul_lo_u16 v3, s0, v3 -; GCN-DL-NEXT: s_bfe_u32 s1, s2, 0x40008 -; GCN-DL-NEXT: s_bfe_u32 s6, s2, 0x4000c -; GCN-DL-NEXT: s_pack_ll_b32_b16 s1, s1, s6 -; GCN-DL-NEXT: v_mov_b32_e32 v4, s5 -; GCN-DL-NEXT: s_bfe_u32 s0, s4, 0x40010 -; GCN-DL-NEXT: s_bfe_u32 s7, s4, 0x40014 -; GCN-DL-NEXT: s_pack_ll_b32_b16 s0, s0, s7 -; GCN-DL-NEXT: v_pk_mul_lo_u16 v4, s1, v4 -; GCN-DL-NEXT: s_bfe_u32 s5, s2, 0x40010 -; GCN-DL-NEXT: s_bfe_u32 s6, s2, 0x40014 -; GCN-DL-NEXT: s_bfe_u32 s1, s4, 0x40018 -; GCN-DL-NEXT: s_lshr_b32 s4, s4, 28 -; GCN-DL-NEXT: v_mov_b32_e32 v5, s0 -; GCN-DL-NEXT: s_pack_ll_b32_b16 s5, s5, s6 -; GCN-DL-NEXT: s_bfe_u32 s0, s2, 0x40018 -; GCN-DL-NEXT: s_lshr_b32 s2, s2, 28 -; GCN-DL-NEXT: s_pack_ll_b32_b16 s1, s1, s4 -; GCN-DL-NEXT: v_pk_mul_lo_u16 v5, s5, v5 -; GCN-DL-NEXT: s_pack_ll_b32_b16 s0, s0, s2 -; GCN-DL-NEXT: v_mov_b32_e32 v6, s1 -; GCN-DL-NEXT: v_pk_mul_lo_u16 v6, s0, v6 -; GCN-DL-NEXT: s_waitcnt vmcnt(0) -; GCN-DL-NEXT: v_add_u32_e32 v2, v3, v2 -; GCN-DL-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GCN-DL-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:BYTE_0 -; GCN-DL-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GCN-DL-NEXT: v_add_u32_e32 v2, v2, v5 -; GCN-DL-NEXT: v_add_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GCN-DL-NEXT: v_add_u32_e32 v2, v2, v6 -; GCN-DL-NEXT: v_add_u32_sdwa v2, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GCN-DL-NEXT: global_store_short v[0:1], v2, off -; GCN-DL-NEXT: s_endpgm +; GFX9-DL-LABEL: udot8_acc16_vecMul: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_load_ushort v2, v[0:1], off +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_and_b32 s0, s2, 15 +; GFX9-DL-NEXT: s_and_b32 s1, s4, 15 +; GFX9-DL-NEXT: s_bfe_u32 s5, s4, 0x40004 +; GFX9-DL-NEXT: s_pack_ll_b32_b16 s1, s1, s5 +; GFX9-DL-NEXT: s_bfe_u32 s6, s2, 0x40004 +; GFX9-DL-NEXT: s_pack_ll_b32_b16 s0, s0, s6 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-DL-NEXT: s_bfe_u32 s5, s4, 0x40008 +; GFX9-DL-NEXT: s_bfe_u32 s7, s4, 0x4000c +; GFX9-DL-NEXT: s_pack_ll_b32_b16 s5, s5, s7 +; GFX9-DL-NEXT: v_pk_mul_lo_u16 v3, s0, v3 +; GFX9-DL-NEXT: s_bfe_u32 s1, s2, 0x40008 +; GFX9-DL-NEXT: s_bfe_u32 s6, s2, 0x4000c +; GFX9-DL-NEXT: s_pack_ll_b32_b16 s1, s1, s6 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s5 +; GFX9-DL-NEXT: s_bfe_u32 s0, s4, 0x40010 +; GFX9-DL-NEXT: s_bfe_u32 s7, s4, 0x40014 +; GFX9-DL-NEXT: s_pack_ll_b32_b16 s0, s0, s7 +; GFX9-DL-NEXT: v_pk_mul_lo_u16 v4, s1, v4 +; GFX9-DL-NEXT: s_bfe_u32 s5, s2, 0x40010 +; GFX9-DL-NEXT: s_bfe_u32 s6, s2, 0x40014 +; GFX9-DL-NEXT: s_bfe_u32 s1, s4, 0x40018 +; GFX9-DL-NEXT: s_lshr_b32 s4, s4, 28 +; GFX9-DL-NEXT: v_mov_b32_e32 v5, s0 +; GFX9-DL-NEXT: s_pack_ll_b32_b16 s5, s5, s6 +; GFX9-DL-NEXT: s_bfe_u32 s0, s2, 0x40018 +; GFX9-DL-NEXT: s_lshr_b32 s2, s2, 28 +; GFX9-DL-NEXT: s_pack_ll_b32_b16 s1, s1, s4 +; GFX9-DL-NEXT: v_pk_mul_lo_u16 v5, s5, v5 +; GFX9-DL-NEXT: s_pack_ll_b32_b16 s0, s0, s2 +; GFX9-DL-NEXT: v_mov_b32_e32 v6, s1 +; GFX9-DL-NEXT: v_pk_mul_lo_u16 v6, s0, v6 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_add_u32_e32 v2, v3, v2 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:BYTE_0 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v5 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v6 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-DL-NEXT: global_store_short v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm <8 x i4> addrspace(1)* %src2, i16 addrspace(1)* nocapture %dst) { entry: @@ -2175,68 +2175,68 @@ ; GFX9-NEXT: global_store_byte v[0:1], v2, off ; GFX9-NEXT: s_endpgm ; -; GCN-DL-LABEL: udot8_acc8_vecMul: -; GCN-DL: ; %bb.0: ; %entry -; GCN-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GCN-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GCN-DL-NEXT: s_load_dword s4, s[6:7], 0x0 -; GCN-DL-NEXT: v_mov_b32_e32 v0, s0 -; GCN-DL-NEXT: v_mov_b32_e32 v1, s1 -; GCN-DL-NEXT: global_load_ubyte v2, v[0:1], off -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: s_and_b32 s0, s2, 15 -; GCN-DL-NEXT: s_and_b32 s1, s4, 15 -; GCN-DL-NEXT: s_bfe_u32 s5, s4, 0x40004 -; GCN-DL-NEXT: s_bfe_u32 s6, s4, 0x40008 -; GCN-DL-NEXT: s_bfe_u32 s7, s4, 0x4000c -; GCN-DL-NEXT: v_mov_b32_e32 v3, s1 -; GCN-DL-NEXT: v_mov_b32_e32 v4, s5 -; GCN-DL-NEXT: s_bfe_u32 s8, s2, 0x40004 -; GCN-DL-NEXT: v_mov_b32_e32 v5, s6 -; GCN-DL-NEXT: s_bfe_u32 s9, s2, 0x40008 -; GCN-DL-NEXT: v_mov_b32_e32 v6, s7 -; GCN-DL-NEXT: s_bfe_u32 s10, s2, 0x4000c -; GCN-DL-NEXT: v_mul_lo_u16_e32 v3, s0, v3 -; GCN-DL-NEXT: v_mul_lo_u16_sdwa v4, s8, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GCN-DL-NEXT: v_mul_lo_u16_e32 v5, s9, v5 -; GCN-DL-NEXT: v_mul_lo_u16_sdwa v6, s10, v6 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GCN-DL-NEXT: v_or_b32_e32 v3, v3, v4 -; GCN-DL-NEXT: v_or_b32_sdwa v4, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GCN-DL-NEXT: s_bfe_u32 s1, s4, 0x40014 -; GCN-DL-NEXT: s_bfe_u32 s5, s4, 0x40018 -; GCN-DL-NEXT: s_bfe_u32 s0, s4, 0x40010 -; GCN-DL-NEXT: s_lshr_b32 s4, s4, 28 -; GCN-DL-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GCN-DL-NEXT: s_bfe_u32 s6, s2, 0x40010 -; GCN-DL-NEXT: v_mov_b32_e32 v4, s0 -; GCN-DL-NEXT: s_bfe_u32 s7, s2, 0x40014 -; GCN-DL-NEXT: v_mov_b32_e32 v5, s1 -; GCN-DL-NEXT: s_bfe_u32 s8, s2, 0x40018 -; GCN-DL-NEXT: v_mov_b32_e32 v6, s5 -; GCN-DL-NEXT: s_lshr_b32 s2, s2, 28 -; GCN-DL-NEXT: v_mov_b32_e32 v7, s4 -; GCN-DL-NEXT: v_mul_lo_u16_e32 v4, s6, v4 -; GCN-DL-NEXT: v_mul_lo_u16_sdwa v5, s7, v5 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GCN-DL-NEXT: v_mul_lo_u16_e32 v6, s8, v6 -; GCN-DL-NEXT: v_mul_lo_u16_sdwa v7, s2, v7 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GCN-DL-NEXT: v_or_b32_e32 v4, v4, v5 -; GCN-DL-NEXT: v_or_b32_sdwa v5, v6, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -; GCN-DL-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD -; GCN-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v3 -; GCN-DL-NEXT: s_waitcnt vmcnt(0) -; GCN-DL-NEXT: v_add_u32_e32 v2, v3, v2 -; GCN-DL-NEXT: v_add_u32_e32 v2, v2, v5 -; GCN-DL-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_2 -; GCN-DL-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 -; GCN-DL-NEXT: v_add_u32_e32 v2, v2, v4 -; GCN-DL-NEXT: v_lshrrev_b32_e32 v3, 8, v4 -; GCN-DL-NEXT: v_add_u32_e32 v2, v2, v3 -; GCN-DL-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 -; GCN-DL-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 -; GCN-DL-NEXT: global_store_byte v[0:1], v2, off -; GCN-DL-NEXT: s_endpgm +; GFX9-DL-LABEL: udot8_acc8_vecMul: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_load_ubyte v2, v[0:1], off +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_and_b32 s0, s2, 15 +; GFX9-DL-NEXT: s_and_b32 s1, s4, 15 +; GFX9-DL-NEXT: s_bfe_u32 s5, s4, 0x40004 +; GFX9-DL-NEXT: s_bfe_u32 s6, s4, 0x40008 +; GFX9-DL-NEXT: s_bfe_u32 s7, s4, 0x4000c +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s5 +; GFX9-DL-NEXT: s_bfe_u32 s8, s2, 0x40004 +; GFX9-DL-NEXT: v_mov_b32_e32 v5, s6 +; GFX9-DL-NEXT: s_bfe_u32 s9, s2, 0x40008 +; GFX9-DL-NEXT: v_mov_b32_e32 v6, s7 +; GFX9-DL-NEXT: s_bfe_u32 s10, s2, 0x4000c +; GFX9-DL-NEXT: v_mul_lo_u16_e32 v3, s0, v3 +; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v4, s8, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9-DL-NEXT: v_mul_lo_u16_e32 v5, s9, v5 +; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v6, s10, v6 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9-DL-NEXT: v_or_b32_e32 v3, v3, v4 +; GFX9-DL-NEXT: v_or_b32_sdwa v4, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9-DL-NEXT: s_bfe_u32 s1, s4, 0x40014 +; GFX9-DL-NEXT: s_bfe_u32 s5, s4, 0x40018 +; GFX9-DL-NEXT: s_bfe_u32 s0, s4, 0x40010 +; GFX9-DL-NEXT: s_lshr_b32 s4, s4, 28 +; GFX9-DL-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-DL-NEXT: s_bfe_u32 s6, s2, 0x40010 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s0 +; GFX9-DL-NEXT: s_bfe_u32 s7, s2, 0x40014 +; GFX9-DL-NEXT: v_mov_b32_e32 v5, s1 +; GFX9-DL-NEXT: s_bfe_u32 s8, s2, 0x40018 +; GFX9-DL-NEXT: v_mov_b32_e32 v6, s5 +; GFX9-DL-NEXT: s_lshr_b32 s2, s2, 28 +; GFX9-DL-NEXT: v_mov_b32_e32 v7, s4 +; GFX9-DL-NEXT: v_mul_lo_u16_e32 v4, s6, v4 +; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v5, s7, v5 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9-DL-NEXT: v_mul_lo_u16_e32 v6, s8, v6 +; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v7, s2, v7 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9-DL-NEXT: v_or_b32_e32 v4, v4, v5 +; GFX9-DL-NEXT: v_or_b32_sdwa v5, v6, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9-DL-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v3 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_add_u32_e32 v2, v3, v2 +; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v5 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_2 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 +; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v4 +; GFX9-DL-NEXT: v_lshrrev_b32_e32 v3, 8, v4 +; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v3 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 +; GFX9-DL-NEXT: global_store_byte v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm <8 x i4> addrspace(1)* %src2, i8 addrspace(1)* nocapture %dst) { entry: @@ -2422,56 +2422,56 @@ ; GFX9-NEXT: global_store_byte v[0:1], v2, off ; GFX9-NEXT: s_endpgm ; -; GCN-DL-LABEL: udot8_acc4_vecMul: -; GCN-DL: ; %bb.0: ; %entry -; GCN-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GCN-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: s_load_dword s2, s[4:5], 0x0 -; GCN-DL-NEXT: s_load_dword s4, s[6:7], 0x0 -; GCN-DL-NEXT: v_mov_b32_e32 v0, s0 -; GCN-DL-NEXT: v_mov_b32_e32 v1, s1 -; GCN-DL-NEXT: global_load_ubyte v2, v[0:1], off -; GCN-DL-NEXT: s_waitcnt lgkmcnt(0) -; GCN-DL-NEXT: s_and_b32 s0, s2, 15 -; GCN-DL-NEXT: s_and_b32 s1, s4, 15 -; GCN-DL-NEXT: v_mov_b32_e32 v3, s1 -; GCN-DL-NEXT: s_bfe_u32 s5, s4, 0x40004 -; GCN-DL-NEXT: s_bfe_u32 s6, s4, 0x40008 -; GCN-DL-NEXT: v_mov_b32_e32 v4, s6 -; GCN-DL-NEXT: s_bfe_u32 s7, s2, 0x40008 -; GCN-DL-NEXT: v_mov_b32_e32 v5, s5 -; GCN-DL-NEXT: s_bfe_u32 s1, s2, 0x40004 -; GCN-DL-NEXT: v_mul_u32_u24_e32 v4, s7, v4 -; GCN-DL-NEXT: s_bfe_u32 s5, s4, 0x4000c -; GCN-DL-NEXT: v_and_b32_e32 v4, 15, v4 -; GCN-DL-NEXT: s_bfe_u32 s7, s4, 0x40010 -; GCN-DL-NEXT: v_mov_b32_e32 v6, s5 -; GCN-DL-NEXT: s_bfe_u32 s6, s2, 0x4000c -; GCN-DL-NEXT: s_bfe_u32 s8, s4, 0x40014 -; GCN-DL-NEXT: v_mov_b32_e32 v7, s7 -; GCN-DL-NEXT: s_bfe_u32 s5, s2, 0x40010 -; GCN-DL-NEXT: s_bfe_u32 s9, s4, 0x40018 -; GCN-DL-NEXT: v_mov_b32_e32 v8, s8 -; GCN-DL-NEXT: s_bfe_u32 s7, s2, 0x40014 -; GCN-DL-NEXT: s_bfe_u32 s8, s2, 0x40018 -; GCN-DL-NEXT: s_lshr_b32 s4, s4, 28 -; GCN-DL-NEXT: v_mov_b32_e32 v9, s9 -; GCN-DL-NEXT: s_lshr_b32 s2, s2, 28 -; GCN-DL-NEXT: s_waitcnt vmcnt(0) -; GCN-DL-NEXT: v_mad_u32_u24 v2, s0, v3, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s1, v5, v2 -; GCN-DL-NEXT: v_and_b32_e32 v2, 15, v2 -; GCN-DL-NEXT: v_add_u32_e32 v2, v2, v4 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s6, v6, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s5, v7, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s7, v8, v2 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s8, v9, v2 -; GCN-DL-NEXT: v_mov_b32_e32 v3, s4 -; GCN-DL-NEXT: v_mad_u32_u24 v2, s2, v3, v2 -; GCN-DL-NEXT: v_and_b32_e32 v2, 15, v2 -; GCN-DL-NEXT: global_store_byte v[0:1], v2, off -; GCN-DL-NEXT: s_endpgm +; GFX9-DL-LABEL: udot8_acc4_vecMul: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_load_ubyte v2, v[0:1], off +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_and_b32 s0, s2, 15 +; GFX9-DL-NEXT: s_and_b32 s1, s4, 15 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-DL-NEXT: s_bfe_u32 s5, s4, 0x40004 +; GFX9-DL-NEXT: s_bfe_u32 s6, s4, 0x40008 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s6 +; GFX9-DL-NEXT: s_bfe_u32 s7, s2, 0x40008 +; GFX9-DL-NEXT: v_mov_b32_e32 v5, s5 +; GFX9-DL-NEXT: s_bfe_u32 s1, s2, 0x40004 +; GFX9-DL-NEXT: v_mul_u32_u24_e32 v4, s7, v4 +; GFX9-DL-NEXT: s_bfe_u32 s5, s4, 0x4000c +; GFX9-DL-NEXT: v_and_b32_e32 v4, 15, v4 +; GFX9-DL-NEXT: s_bfe_u32 s7, s4, 0x40010 +; GFX9-DL-NEXT: v_mov_b32_e32 v6, s5 +; GFX9-DL-NEXT: s_bfe_u32 s6, s2, 0x4000c +; GFX9-DL-NEXT: s_bfe_u32 s8, s4, 0x40014 +; GFX9-DL-NEXT: v_mov_b32_e32 v7, s7 +; GFX9-DL-NEXT: s_bfe_u32 s5, s2, 0x40010 +; GFX9-DL-NEXT: s_bfe_u32 s9, s4, 0x40018 +; GFX9-DL-NEXT: v_mov_b32_e32 v8, s8 +; GFX9-DL-NEXT: s_bfe_u32 s7, s2, 0x40014 +; GFX9-DL-NEXT: s_bfe_u32 s8, s2, 0x40018 +; GFX9-DL-NEXT: s_lshr_b32 s4, s4, 28 +; GFX9-DL-NEXT: v_mov_b32_e32 v9, s9 +; GFX9-DL-NEXT: s_lshr_b32 s2, s2, 28 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s0, v3, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s1, v5, v2 +; GFX9-DL-NEXT: v_and_b32_e32 v2, 15, v2 +; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v4 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s6, v6, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s5, v7, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s7, v8, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s8, v9, v2 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s4 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, s2, v3, v2 +; GFX9-DL-NEXT: v_and_b32_e32 v2, 15, v2 +; GFX9-DL-NEXT: global_store_byte v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm <8 x i4> addrspace(1)* %src2, i4 addrspace(1)* nocapture %dst) { entry: @@ -2501,3 +2501,2137 @@ store i4 %add8, i4 addrspace(1)* %dst, align 4 ret void } + +define amdgpu_kernel void @idot8_acc32(<8 x i4> addrspace(1)* %src1, +; GFX7-LABEL: idot8_acc32: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s7, 0xf000 +; GFX7-NEXT: s_mov_b32 s6, -1 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s0, s[8:9], 0x0 +; GFX7-NEXT: s_load_dword s1, s[10:11], 0x0 +; GFX7-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_bfe_i32 s8, s0, 0x40000 +; GFX7-NEXT: s_bfe_i32 s9, s1, 0x40000 +; GFX7-NEXT: s_bfe_i32 s11, s1, 0x40004 +; GFX7-NEXT: v_mov_b32_e32 v0, s9 +; GFX7-NEXT: v_mov_b32_e32 v1, s2 +; GFX7-NEXT: v_mad_i32_i24 v0, s8, v0, v1 +; GFX7-NEXT: s_bfe_i32 s10, s0, 0x40004 +; GFX7-NEXT: v_mov_b32_e32 v1, s11 +; GFX7-NEXT: s_bfe_i32 s13, s1, 0x40008 +; GFX7-NEXT: v_mad_i32_i24 v0, s10, v1, v0 +; GFX7-NEXT: s_bfe_i32 s12, s0, 0x40008 +; GFX7-NEXT: v_mov_b32_e32 v1, s13 +; GFX7-NEXT: s_bfe_i32 s15, s1, 0x4000c +; GFX7-NEXT: v_mad_i32_i24 v0, s12, v1, v0 +; GFX7-NEXT: s_bfe_i32 s14, s0, 0x4000c +; GFX7-NEXT: v_mov_b32_e32 v1, s15 +; GFX7-NEXT: s_bfe_i32 s17, s1, 0x40010 +; GFX7-NEXT: v_mad_i32_i24 v0, s14, v1, v0 +; GFX7-NEXT: s_bfe_i32 s16, s0, 0x40010 +; GFX7-NEXT: v_mov_b32_e32 v1, s17 +; GFX7-NEXT: s_bfe_i32 s19, s1, 0x40014 +; GFX7-NEXT: s_bfe_i32 s21, s1, 0x40018 +; GFX7-NEXT: v_mad_i32_i24 v0, s16, v1, v0 +; GFX7-NEXT: s_bfe_i32 s18, s0, 0x40014 +; GFX7-NEXT: v_mov_b32_e32 v1, s19 +; GFX7-NEXT: s_bfe_i32 s20, s0, 0x40018 +; GFX7-NEXT: v_mad_i32_i24 v0, s18, v1, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, s21 +; GFX7-NEXT: s_ashr_i32 s1, s1, 28 +; GFX7-NEXT: v_mad_i32_i24 v0, s20, v1, v0 +; GFX7-NEXT: s_ashr_i32 s0, s0, 28 +; GFX7-NEXT: v_mov_b32_e32 v1, s1 +; GFX7-NEXT: v_mad_i32_i24 v0, s0, v1, v0 +; GFX7-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: idot8_acc32: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX8-NEXT: s_load_dword s5, s[0:1], 0x0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_bfe_i32 s0, s2, 0x40000 +; GFX8-NEXT: s_bfe_i32 s1, s4, 0x40000 +; GFX8-NEXT: s_bfe_i32 s7, s4, 0x40004 +; GFX8-NEXT: v_mov_b32_e32 v2, s1 +; GFX8-NEXT: v_mov_b32_e32 v3, s5 +; GFX8-NEXT: v_mad_i32_i24 v2, s0, v2, v3 +; GFX8-NEXT: s_bfe_i32 s6, s2, 0x40004 +; GFX8-NEXT: v_mov_b32_e32 v3, s7 +; GFX8-NEXT: s_bfe_i32 s9, s4, 0x40008 +; GFX8-NEXT: v_mad_i32_i24 v2, s6, v3, v2 +; GFX8-NEXT: s_bfe_i32 s8, s2, 0x40008 +; GFX8-NEXT: v_mov_b32_e32 v3, s9 +; GFX8-NEXT: s_bfe_i32 s11, s4, 0x4000c +; GFX8-NEXT: v_mad_i32_i24 v2, s8, v3, v2 +; GFX8-NEXT: s_bfe_i32 s10, s2, 0x4000c +; GFX8-NEXT: v_mov_b32_e32 v3, s11 +; GFX8-NEXT: s_bfe_i32 s13, s4, 0x40010 +; GFX8-NEXT: v_mad_i32_i24 v2, s10, v3, v2 +; GFX8-NEXT: s_bfe_i32 s12, s2, 0x40010 +; GFX8-NEXT: v_mov_b32_e32 v3, s13 +; GFX8-NEXT: s_bfe_i32 s15, s4, 0x40014 +; GFX8-NEXT: s_bfe_i32 s17, s4, 0x40018 +; GFX8-NEXT: v_mad_i32_i24 v2, s12, v3, v2 +; GFX8-NEXT: s_bfe_i32 s14, s2, 0x40014 +; GFX8-NEXT: v_mov_b32_e32 v3, s15 +; GFX8-NEXT: s_bfe_i32 s16, s2, 0x40018 +; GFX8-NEXT: v_mad_i32_i24 v2, s14, v3, v2 +; GFX8-NEXT: v_mov_b32_e32 v3, s17 +; GFX8-NEXT: s_ashr_i32 s4, s4, 28 +; GFX8-NEXT: v_mad_i32_i24 v2, s16, v3, v2 +; GFX8-NEXT: s_ashr_i32 s2, s2, 28 +; GFX8-NEXT: v_mov_b32_e32 v3, s4 +; GFX8-NEXT: v_mad_i32_i24 v2, s2, v3, v2 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: idot8_acc32: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-NEXT: s_load_dword s5, s[0:1], 0x0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_bfe_i32 s0, s2, 0x40000 +; GFX9-NEXT: s_bfe_i32 s1, s4, 0x40000 +; GFX9-NEXT: s_bfe_i32 s7, s4, 0x40004 +; GFX9-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-NEXT: v_mad_i32_i24 v2, s0, v2, v3 +; GFX9-NEXT: s_bfe_i32 s6, s2, 0x40004 +; GFX9-NEXT: v_mov_b32_e32 v3, s7 +; GFX9-NEXT: s_bfe_i32 s9, s4, 0x40008 +; GFX9-NEXT: v_mad_i32_i24 v2, s6, v3, v2 +; GFX9-NEXT: s_bfe_i32 s8, s2, 0x40008 +; GFX9-NEXT: v_mov_b32_e32 v3, s9 +; GFX9-NEXT: s_bfe_i32 s11, s4, 0x4000c +; GFX9-NEXT: v_mad_i32_i24 v2, s8, v3, v2 +; GFX9-NEXT: s_bfe_i32 s10, s2, 0x4000c +; GFX9-NEXT: v_mov_b32_e32 v3, s11 +; GFX9-NEXT: s_bfe_i32 s13, s4, 0x40010 +; GFX9-NEXT: v_mad_i32_i24 v2, s10, v3, v2 +; GFX9-NEXT: s_bfe_i32 s12, s2, 0x40010 +; GFX9-NEXT: v_mov_b32_e32 v3, s13 +; GFX9-NEXT: s_bfe_i32 s15, s4, 0x40014 +; GFX9-NEXT: s_bfe_i32 s17, s4, 0x40018 +; GFX9-NEXT: v_mad_i32_i24 v2, s12, v3, v2 +; GFX9-NEXT: s_bfe_i32 s14, s2, 0x40014 +; GFX9-NEXT: v_mov_b32_e32 v3, s15 +; GFX9-NEXT: s_bfe_i32 s16, s2, 0x40018 +; GFX9-NEXT: v_mad_i32_i24 v2, s14, v3, v2 +; GFX9-NEXT: v_mov_b32_e32 v3, s17 +; GFX9-NEXT: s_ashr_i32 s4, s4, 28 +; GFX9-NEXT: v_mad_i32_i24 v2, s16, v3, v2 +; GFX9-NEXT: s_ashr_i32 s2, s2, 28 +; GFX9-NEXT: v_mov_b32_e32 v3, s4 +; GFX9-NEXT: v_mad_i32_i24 v2, s2, v3, v2 +; GFX9-NEXT: global_store_dword v[0:1], v2, off +; GFX9-NEXT: s_endpgm +; +; GFX9-DL-LABEL: idot8_acc32: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-DL-NEXT: s_load_dword s5, s[0:1], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-DL-NEXT: v_dot8_i32_i4 v2, s2, v2, v3 +; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm + <8 x i4> addrspace(1)* %src2, + i32 addrspace(1)* nocapture %dst) { +entry: + %vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %src1 + %vec2 = load <8 x i4>, <8 x i4> addrspace(1)* %src2 + + %v1e0 = extractelement <8 x i4> %vec1, i64 0 + %cv1e0 = sext i4 %v1e0 to i32 + %v2e0 = extractelement <8 x i4> %vec2, i64 0 + %cv2e0 = sext i4 %v2e0 to i32 + %mul0 = mul nuw nsw i32 %cv1e0, %cv2e0 + + %v1e1 = extractelement <8 x i4> %vec1, i64 1 + %cv1e1 = sext i4 %v1e1 to i32 + %v2e1 = extractelement <8 x i4> %vec2, i64 1 + %cv2e1 = sext i4 %v2e1 to i32 + %mul1 = mul nuw nsw i32 %cv1e1, %cv2e1 + + %v1e2 = extractelement <8 x i4> %vec1, i64 2 + %cv1e2 = sext i4 %v1e2 to i32 + %v2e2 = extractelement <8 x i4> %vec2, i64 2 + %cv2e2 = sext i4 %v2e2 to i32 + %mul2 = mul nuw nsw i32 %cv1e2, %cv2e2 + + %v1e3 = extractelement <8 x i4> %vec1, i64 3 + %cv1e3 = sext i4 %v1e3 to i32 + %v2e3 = extractelement <8 x i4> %vec2, i64 3 + %cv2e3 = sext i4 %v2e3 to i32 + %mul3 = mul nuw nsw i32 %cv1e3, %cv2e3 + + %v1e4 = extractelement <8 x i4> %vec1, i64 4 + %cv1e4 = sext i4 %v1e4 to i32 + %v2e4 = extractelement <8 x i4> %vec2, i64 4 + %cv2e4 = sext i4 %v2e4 to i32 + %mul4 = mul nuw nsw i32 %cv1e4, %cv2e4 + + %v1e5 = extractelement <8 x i4> %vec1, i64 5 + %cv1e5 = sext i4 %v1e5 to i32 + %v2e5 = extractelement <8 x i4> %vec2, i64 5 + %cv2e5 = sext i4 %v2e5 to i32 + %mul5 = mul nuw nsw i32 %cv1e5, %cv2e5 + + %v1e6 = extractelement <8 x i4> %vec1, i64 6 + %cv1e6 = sext i4 %v1e6 to i32 + %v2e6 = extractelement <8 x i4> %vec2, i64 6 + %cv2e6 = sext i4 %v2e6 to i32 + %mul6 = mul nuw nsw i32 %cv1e6, %cv2e6 + + %v1e7 = extractelement <8 x i4> %vec1, i64 7 + %cv1e7 = sext i4 %v1e7 to i32 + %v2e7 = extractelement <8 x i4> %vec2, i64 7 + %cv2e7 = sext i4 %v2e7 to i32 + %mul7 = mul nuw nsw i32 %cv1e7, %cv2e7 + + %acc = load i32, i32 addrspace(1)* %dst, align 4 + %add1 = add i32 %mul0, %acc + %add2 = add i32 %add1, %mul1 + %add3 = add i32 %add2, %mul2 + %add4 = add i32 %add3, %mul3 + %add5 = add i32 %add4, %mul4 + %add6 = add i32 %add5, %mul5 + %add7 = add i32 %add6, %mul6 + %add8 = add i32 %add7, %mul7 + + store i32 %add8, i32 addrspace(1)* %dst, align 4 + ret void +} + +; TODO: Once the unnecessary zero extentions of the elements are removed; +; pattern recognizer will kick in. +define amdgpu_kernel void @idot8_acc16(<8 x i4> addrspace(1)* %src1, +; GFX7-LABEL: idot8_acc16: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s7, 0xf000 +; GFX7-NEXT: s_mov_b32 s6, -1 +; GFX7-NEXT: s_mov_b32 s0, 0xffff +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s1, s[8:9], 0x0 +; GFX7-NEXT: buffer_load_ushort v0, off, s[4:7], 0 +; GFX7-NEXT: s_load_dword s2, s[10:11], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_bfe_i32 s8, s1, 0x40000 +; GFX7-NEXT: s_bfe_i32 s10, s1, 0x40004 +; GFX7-NEXT: s_bfe_i32 s9, s2, 0x40000 +; GFX7-NEXT: s_bfe_i32 s11, s2, 0x40004 +; GFX7-NEXT: s_and_b32 s9, s9, s0 +; GFX7-NEXT: s_bfe_i32 s13, s2, 0x40008 +; GFX7-NEXT: s_and_b32 s11, s11, s0 +; GFX7-NEXT: s_and_b32 s8, s8, s0 +; GFX7-NEXT: v_mov_b32_e32 v1, s9 +; GFX7-NEXT: s_bfe_i32 s12, s1, 0x40008 +; GFX7-NEXT: s_bfe_i32 s15, s2, 0x4000c +; GFX7-NEXT: s_and_b32 s13, s13, s0 +; GFX7-NEXT: s_and_b32 s10, s10, s0 +; GFX7-NEXT: v_mov_b32_e32 v2, s11 +; GFX7-NEXT: s_bfe_i32 s14, s1, 0x4000c +; GFX7-NEXT: s_bfe_i32 s17, s2, 0x40010 +; GFX7-NEXT: s_and_b32 s15, s15, s0 +; GFX7-NEXT: s_and_b32 s12, s12, s0 +; GFX7-NEXT: v_mov_b32_e32 v3, s13 +; GFX7-NEXT: s_bfe_i32 s16, s1, 0x40010 +; GFX7-NEXT: s_bfe_i32 s19, s2, 0x40014 +; GFX7-NEXT: s_and_b32 s17, s17, s0 +; GFX7-NEXT: s_and_b32 s14, s14, s0 +; GFX7-NEXT: v_mov_b32_e32 v4, s15 +; GFX7-NEXT: s_bfe_i32 s21, s2, 0x40018 +; GFX7-NEXT: s_bfe_i32 s18, s1, 0x40014 +; GFX7-NEXT: s_and_b32 s19, s19, s0 +; GFX7-NEXT: s_and_b32 s16, s16, s0 +; GFX7-NEXT: v_mov_b32_e32 v5, s17 +; GFX7-NEXT: s_bfe_i32 s20, s1, 0x40018 +; GFX7-NEXT: s_ashr_i32 s2, s2, 28 +; GFX7-NEXT: s_and_b32 s21, s21, s0 +; GFX7-NEXT: s_and_b32 s18, s18, s0 +; GFX7-NEXT: v_mov_b32_e32 v6, s19 +; GFX7-NEXT: s_ashr_i32 s1, s1, 28 +; GFX7-NEXT: s_and_b32 s20, s20, s0 +; GFX7-NEXT: s_and_b32 s2, s2, s0 +; GFX7-NEXT: v_mov_b32_e32 v7, s21 +; GFX7-NEXT: s_and_b32 s0, s1, s0 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_mad_u32_u24 v0, s8, v1, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s10, v2, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s12, v3, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s14, v4, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s16, v5, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s18, v6, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s20, v7, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, s2 +; GFX7-NEXT: v_mad_u32_u24 v0, s0, v1, v0 +; GFX7-NEXT: buffer_store_short v0, off, s[4:7], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: idot8_acc16: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ushort v2, v[0:1] +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_lshr_b32 s0, s2, 4 +; GFX8-NEXT: s_lshr_b32 s1, s4, 4 +; GFX8-NEXT: s_bfe_i32 s5, s4, 0x40000 +; GFX8-NEXT: v_lshlrev_b16_e64 v3, 12, s0 +; GFX8-NEXT: v_lshlrev_b16_e64 v4, 12, s1 +; GFX8-NEXT: s_bfe_i32 s0, s4, 0x40008 +; GFX8-NEXT: v_mov_b32_e32 v5, s5 +; GFX8-NEXT: s_bfe_i32 s6, s2, 0x40000 +; GFX8-NEXT: s_lshr_b32 s1, s2, 12 +; GFX8-NEXT: s_lshr_b32 s5, s4, 12 +; GFX8-NEXT: v_mov_b32_e32 v6, s0 +; GFX8-NEXT: s_bfe_i32 s7, s2, 0x40008 +; GFX8-NEXT: v_ashrrev_i16_e32 v3, 12, v3 +; GFX8-NEXT: v_ashrrev_i16_e32 v4, 12, v4 +; GFX8-NEXT: v_lshlrev_b16_e64 v7, 12, s1 +; GFX8-NEXT: v_lshlrev_b16_e64 v8, 12, s5 +; GFX8-NEXT: v_mul_i32_i24_e32 v6, s7, v6 +; GFX8-NEXT: s_lshr_b32 s0, s2, 20 +; GFX8-NEXT: s_lshr_b32 s1, s4, 20 +; GFX8-NEXT: s_bfe_i32 s5, s4, 0x40010 +; GFX8-NEXT: v_ashrrev_i16_e32 v7, 12, v7 +; GFX8-NEXT: v_ashrrev_i16_e32 v8, 12, v8 +; GFX8-NEXT: v_lshlrev_b16_e64 v9, 12, s0 +; GFX8-NEXT: v_lshlrev_b16_e64 v10, 12, s1 +; GFX8-NEXT: s_bfe_i32 s8, s2, 0x40010 +; GFX8-NEXT: v_mov_b32_e32 v13, s5 +; GFX8-NEXT: s_lshr_b32 s0, s2, 28 +; GFX8-NEXT: s_lshr_b32 s9, s4, 28 +; GFX8-NEXT: s_bfe_i32 s4, s4, 0x40018 +; GFX8-NEXT: v_ashrrev_i16_e32 v9, 12, v9 +; GFX8-NEXT: v_ashrrev_i16_e32 v10, 12, v10 +; GFX8-NEXT: v_lshlrev_b16_e64 v11, 12, s0 +; GFX8-NEXT: v_lshlrev_b16_e64 v12, 12, s9 +; GFX8-NEXT: s_bfe_i32 s2, s2, 0x40018 +; GFX8-NEXT: v_ashrrev_i16_e32 v11, 12, v11 +; GFX8-NEXT: v_ashrrev_i16_e32 v12, 12, v12 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_mad_i32_i24 v2, s6, v5, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, v3, v4, v2 +; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v6, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0 +; GFX8-NEXT: v_mad_u32_u24 v2, v7, v8, v2 +; GFX8-NEXT: v_mad_i32_i24 v2, s8, v13, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, v9, v10, v2 +; GFX8-NEXT: v_mov_b32_e32 v3, s4 +; GFX8-NEXT: v_mad_i32_i24 v2, s2, v3, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, v11, v12, v2 +; GFX8-NEXT: flat_store_short v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: idot8_acc16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_load_ushort v2, v[0:1], off +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_lshr_b32 s0, s2, 4 +; GFX9-NEXT: s_lshr_b32 s1, s4, 4 +; GFX9-NEXT: s_bfe_i32 s5, s4, 0x40000 +; GFX9-NEXT: v_lshlrev_b16_e64 v3, 12, s0 +; GFX9-NEXT: v_lshlrev_b16_e64 v4, 12, s1 +; GFX9-NEXT: s_bfe_i32 s0, s4, 0x40008 +; GFX9-NEXT: v_mov_b32_e32 v5, s5 +; GFX9-NEXT: s_bfe_i32 s6, s2, 0x40000 +; GFX9-NEXT: s_lshr_b32 s1, s2, 12 +; GFX9-NEXT: s_lshr_b32 s5, s4, 12 +; GFX9-NEXT: v_mov_b32_e32 v6, s0 +; GFX9-NEXT: s_bfe_i32 s7, s2, 0x40008 +; GFX9-NEXT: v_ashrrev_i16_e32 v3, 12, v3 +; GFX9-NEXT: v_ashrrev_i16_e32 v4, 12, v4 +; GFX9-NEXT: v_lshlrev_b16_e64 v7, 12, s1 +; GFX9-NEXT: v_lshlrev_b16_e64 v8, 12, s5 +; GFX9-NEXT: v_mul_i32_i24_e32 v6, s7, v6 +; GFX9-NEXT: s_lshr_b32 s0, s2, 20 +; GFX9-NEXT: s_lshr_b32 s1, s4, 20 +; GFX9-NEXT: s_bfe_i32 s5, s4, 0x40010 +; GFX9-NEXT: v_ashrrev_i16_e32 v7, 12, v7 +; GFX9-NEXT: v_ashrrev_i16_e32 v8, 12, v8 +; GFX9-NEXT: v_lshlrev_b16_e64 v9, 12, s0 +; GFX9-NEXT: v_lshlrev_b16_e64 v10, 12, s1 +; GFX9-NEXT: s_bfe_i32 s8, s2, 0x40010 +; GFX9-NEXT: v_mov_b32_e32 v13, s5 +; GFX9-NEXT: s_lshr_b32 s0, s2, 28 +; GFX9-NEXT: s_lshr_b32 s9, s4, 28 +; GFX9-NEXT: s_bfe_i32 s4, s4, 0x40018 +; GFX9-NEXT: v_ashrrev_i16_e32 v9, 12, v9 +; GFX9-NEXT: v_ashrrev_i16_e32 v10, 12, v10 +; GFX9-NEXT: v_lshlrev_b16_e64 v11, 12, s0 +; GFX9-NEXT: v_lshlrev_b16_e64 v12, 12, s9 +; GFX9-NEXT: s_bfe_i32 s2, s2, 0x40018 +; GFX9-NEXT: v_ashrrev_i16_e32 v11, 12, v11 +; GFX9-NEXT: v_ashrrev_i16_e32 v12, 12, v12 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_mad_i32_i24 v2, s6, v5, v2 +; GFX9-NEXT: v_mad_u32_u24 v2, v3, v4, v2 +; GFX9-NEXT: v_add_u32_sdwa v2, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0 +; GFX9-NEXT: v_mad_u32_u24 v2, v7, v8, v2 +; GFX9-NEXT: v_mad_i32_i24 v2, s8, v13, v2 +; GFX9-NEXT: v_mad_u32_u24 v2, v9, v10, v2 +; GFX9-NEXT: v_mov_b32_e32 v3, s4 +; GFX9-NEXT: v_mad_i32_i24 v2, s2, v3, v2 +; GFX9-NEXT: v_mad_u32_u24 v2, v11, v12, v2 +; GFX9-NEXT: global_store_short v[0:1], v2, off +; GFX9-NEXT: s_endpgm +; +; GFX9-DL-LABEL: idot8_acc16: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_load_ushort v2, v[0:1], off +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_lshr_b32 s0, s2, 4 +; GFX9-DL-NEXT: s_lshr_b32 s1, s4, 4 +; GFX9-DL-NEXT: s_bfe_i32 s5, s4, 0x40000 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v3, 12, s0 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v4, 12, s1 +; GFX9-DL-NEXT: s_bfe_i32 s0, s4, 0x40008 +; GFX9-DL-NEXT: v_mov_b32_e32 v5, s5 +; GFX9-DL-NEXT: s_bfe_i32 s6, s2, 0x40000 +; GFX9-DL-NEXT: s_lshr_b32 s1, s2, 12 +; GFX9-DL-NEXT: s_lshr_b32 s5, s4, 12 +; GFX9-DL-NEXT: v_mov_b32_e32 v6, s0 +; GFX9-DL-NEXT: s_bfe_i32 s7, s2, 0x40008 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v3, 12, v3 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v4, 12, v4 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v7, 12, s1 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v8, 12, s5 +; GFX9-DL-NEXT: v_mul_i32_i24_e32 v6, s7, v6 +; GFX9-DL-NEXT: s_lshr_b32 s0, s2, 20 +; GFX9-DL-NEXT: s_lshr_b32 s1, s4, 20 +; GFX9-DL-NEXT: s_bfe_i32 s5, s4, 0x40010 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v7, 12, v7 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v8, 12, v8 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v9, 12, s0 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v10, 12, s1 +; GFX9-DL-NEXT: s_bfe_i32 s8, s2, 0x40010 +; GFX9-DL-NEXT: v_mov_b32_e32 v13, s5 +; GFX9-DL-NEXT: s_lshr_b32 s0, s2, 28 +; GFX9-DL-NEXT: s_lshr_b32 s9, s4, 28 +; GFX9-DL-NEXT: s_bfe_i32 s4, s4, 0x40018 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v9, 12, v9 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v10, 12, v10 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v11, 12, s0 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v12, 12, s9 +; GFX9-DL-NEXT: s_bfe_i32 s2, s2, 0x40018 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v11, 12, v11 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v12, 12, v12 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s6, v5, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, v3, v4, v2 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, v7, v8, v2 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s8, v13, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, v9, v10, v2 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s4 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s2, v3, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, v11, v12, v2 +; GFX9-DL-NEXT: global_store_short v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm + <8 x i4> addrspace(1)* %src2, + i16 addrspace(1)* nocapture %dst) { +entry: + %vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %src1 + %vec2 = load <8 x i4>, <8 x i4> addrspace(1)* %src2 + + %v1e0 = extractelement <8 x i4> %vec1, i64 0 + %cv1e0 = sext i4 %v1e0 to i16 + %v2e0 = extractelement <8 x i4> %vec2, i64 0 + %cv2e0 = sext i4 %v2e0 to i16 + %mul0 = mul nuw nsw i16 %cv1e0, %cv2e0 + + %v1e1 = extractelement <8 x i4> %vec1, i64 1 + %cv1e1 = sext i4 %v1e1 to i16 + %v2e1 = extractelement <8 x i4> %vec2, i64 1 + %cv2e1 = sext i4 %v2e1 to i16 + %mul1 = mul nuw nsw i16 %cv1e1, %cv2e1 + + %v1e2 = extractelement <8 x i4> %vec1, i64 2 + %cv1e2 = sext i4 %v1e2 to i16 + %v2e2 = extractelement <8 x i4> %vec2, i64 2 + %cv2e2 = sext i4 %v2e2 to i16 + %mul2 = mul nuw nsw i16 %cv1e2, %cv2e2 + + %v1e3 = extractelement <8 x i4> %vec1, i64 3 + %cv1e3 = sext i4 %v1e3 to i16 + %v2e3 = extractelement <8 x i4> %vec2, i64 3 + %cv2e3 = sext i4 %v2e3 to i16 + %mul3 = mul nuw nsw i16 %cv1e3, %cv2e3 + + %v1e4 = extractelement <8 x i4> %vec1, i64 4 + %cv1e4 = sext i4 %v1e4 to i16 + %v2e4 = extractelement <8 x i4> %vec2, i64 4 + %cv2e4 = sext i4 %v2e4 to i16 + %mul4 = mul nuw nsw i16 %cv1e4, %cv2e4 + + %v1e5 = extractelement <8 x i4> %vec1, i64 5 + %cv1e5 = sext i4 %v1e5 to i16 + %v2e5 = extractelement <8 x i4> %vec2, i64 5 + %cv2e5 = sext i4 %v2e5 to i16 + %mul5 = mul nuw nsw i16 %cv1e5, %cv2e5 + + %v1e6 = extractelement <8 x i4> %vec1, i64 6 + %cv1e6 = sext i4 %v1e6 to i16 + %v2e6 = extractelement <8 x i4> %vec2, i64 6 + %cv2e6 = sext i4 %v2e6 to i16 + %mul6 = mul nuw nsw i16 %cv1e6, %cv2e6 + + %v1e7 = extractelement <8 x i4> %vec1, i64 7 + %cv1e7 = sext i4 %v1e7 to i16 + %v2e7 = extractelement <8 x i4> %vec2, i64 7 + %cv2e7 = sext i4 %v2e7 to i16 + %mul7 = mul nuw nsw i16 %cv1e7, %cv2e7 + + %acc = load i16, i16 addrspace(1)* %dst, align 4 + %add1 = add i16 %mul0, %acc + %add2 = add i16 %add1, %mul1 + %add3 = add i16 %add2, %mul2 + %add4 = add i16 %add3, %mul3 + %add5 = add i16 %add4, %mul4 + %add6 = add i16 %add5, %mul5 + %add7 = add i16 %add6, %mul6 + %add8 = add i16 %add7, %mul7 + + store i16 %add8, i16 addrspace(1)* %dst, align 4 + ret void +} + +; TODO: Support this pattern. +define amdgpu_kernel void @idot8_acc8(<8 x i4> addrspace(1)* %src1, +; GFX7-LABEL: idot8_acc8: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s7, 0xf000 +; GFX7-NEXT: s_mov_b32 s6, -1 +; GFX7-NEXT: s_movk_i32 s0, 0xff +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s1, s[8:9], 0x0 +; GFX7-NEXT: buffer_load_ubyte v0, off, s[4:7], 0 +; GFX7-NEXT: s_load_dword s2, s[10:11], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_bfe_i32 s8, s1, 0x40000 +; GFX7-NEXT: s_bfe_i32 s10, s1, 0x40004 +; GFX7-NEXT: s_bfe_i32 s9, s2, 0x40000 +; GFX7-NEXT: s_bfe_i32 s11, s2, 0x40004 +; GFX7-NEXT: s_and_b32 s9, s9, s0 +; GFX7-NEXT: s_bfe_i32 s13, s2, 0x40008 +; GFX7-NEXT: s_and_b32 s11, s11, s0 +; GFX7-NEXT: s_and_b32 s8, s8, s0 +; GFX7-NEXT: v_mov_b32_e32 v1, s9 +; GFX7-NEXT: s_bfe_i32 s12, s1, 0x40008 +; GFX7-NEXT: s_bfe_i32 s15, s2, 0x4000c +; GFX7-NEXT: s_and_b32 s13, s13, s0 +; GFX7-NEXT: s_and_b32 s10, s10, s0 +; GFX7-NEXT: v_mov_b32_e32 v2, s11 +; GFX7-NEXT: s_bfe_i32 s14, s1, 0x4000c +; GFX7-NEXT: s_bfe_i32 s17, s2, 0x40010 +; GFX7-NEXT: s_and_b32 s15, s15, s0 +; GFX7-NEXT: s_and_b32 s12, s12, s0 +; GFX7-NEXT: v_mov_b32_e32 v3, s13 +; GFX7-NEXT: s_bfe_i32 s16, s1, 0x40010 +; GFX7-NEXT: s_bfe_i32 s19, s2, 0x40014 +; GFX7-NEXT: s_and_b32 s17, s17, s0 +; GFX7-NEXT: s_and_b32 s14, s14, s0 +; GFX7-NEXT: v_mov_b32_e32 v4, s15 +; GFX7-NEXT: s_bfe_i32 s21, s2, 0x40018 +; GFX7-NEXT: s_bfe_i32 s18, s1, 0x40014 +; GFX7-NEXT: s_and_b32 s19, s19, s0 +; GFX7-NEXT: s_and_b32 s16, s16, s0 +; GFX7-NEXT: v_mov_b32_e32 v5, s17 +; GFX7-NEXT: s_bfe_i32 s20, s1, 0x40018 +; GFX7-NEXT: s_ashr_i32 s2, s2, 28 +; GFX7-NEXT: s_and_b32 s21, s21, s0 +; GFX7-NEXT: s_and_b32 s18, s18, s0 +; GFX7-NEXT: v_mov_b32_e32 v6, s19 +; GFX7-NEXT: s_ashr_i32 s1, s1, 28 +; GFX7-NEXT: s_and_b32 s20, s20, s0 +; GFX7-NEXT: s_and_b32 s2, s2, s0 +; GFX7-NEXT: v_mov_b32_e32 v7, s21 +; GFX7-NEXT: s_and_b32 s0, s1, s0 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_mad_u32_u24 v0, s8, v1, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s10, v2, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s12, v3, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s14, v4, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s16, v5, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s18, v6, v0 +; GFX7-NEXT: v_mad_u32_u24 v0, s20, v7, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, s2 +; GFX7-NEXT: v_mad_u32_u24 v0, s0, v1, v0 +; GFX7-NEXT: buffer_store_byte v0, off, s[4:7], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: idot8_acc8: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_movk_i32 s2, 0xff +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ubyte v2, v[0:1] +; GFX8-NEXT: s_load_dword s0, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s1, s[6:7], 0x0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_lshr_b32 s7, s0, 4 +; GFX8-NEXT: s_lshr_b32 s11, s1, 4 +; GFX8-NEXT: v_lshlrev_b16_e64 v3, 12, s7 +; GFX8-NEXT: v_lshlrev_b16_e64 v4, 12, s11 +; GFX8-NEXT: s_bfe_i32 s13, s1, 0x40000 +; GFX8-NEXT: v_ashrrev_i16_e32 v3, 12, v3 +; GFX8-NEXT: v_ashrrev_i16_e32 v4, 12, v4 +; GFX8-NEXT: s_lshr_b32 s6, s0, 12 +; GFX8-NEXT: s_lshr_b32 s10, s1, 12 +; GFX8-NEXT: s_bfe_i32 s15, s1, 0x40008 +; GFX8-NEXT: s_bfe_i32 s12, s0, 0x40000 +; GFX8-NEXT: v_mov_b32_e32 v12, s13 +; GFX8-NEXT: v_lshlrev_b16_e64 v6, 12, s6 +; GFX8-NEXT: v_lshlrev_b16_e64 v7, 12, s10 +; GFX8-NEXT: s_bfe_i32 s14, s0, 0x40008 +; GFX8-NEXT: v_mov_b32_e32 v5, s15 +; GFX8-NEXT: v_and_b32_e32 v3, s2, v3 +; GFX8-NEXT: v_and_b32_e32 v4, s2, v4 +; GFX8-NEXT: v_ashrrev_i16_e32 v6, 12, v6 +; GFX8-NEXT: v_ashrrev_i16_e32 v7, 12, v7 +; GFX8-NEXT: s_lshr_b32 s5, s0, 20 +; GFX8-NEXT: s_lshr_b32 s9, s1, 20 +; GFX8-NEXT: v_mul_i32_i24_e32 v5, s14, v5 +; GFX8-NEXT: v_lshlrev_b16_e64 v8, 12, s5 +; GFX8-NEXT: v_lshlrev_b16_e64 v9, 12, s9 +; GFX8-NEXT: s_bfe_i32 s17, s1, 0x40010 +; GFX8-NEXT: v_and_b32_e32 v6, s2, v6 +; GFX8-NEXT: v_and_b32_e32 v7, s2, v7 +; GFX8-NEXT: s_lshr_b32 s8, s1, 28 +; GFX8-NEXT: v_ashrrev_i16_e32 v8, 12, v8 +; GFX8-NEXT: v_ashrrev_i16_e32 v9, 12, v9 +; GFX8-NEXT: s_lshr_b32 s4, s0, 28 +; GFX8-NEXT: s_bfe_i32 s16, s0, 0x40010 +; GFX8-NEXT: v_mov_b32_e32 v13, s17 +; GFX8-NEXT: v_lshlrev_b16_e64 v10, 12, s4 +; GFX8-NEXT: v_lshlrev_b16_e64 v11, 12, s8 +; GFX8-NEXT: s_bfe_i32 s1, s1, 0x40018 +; GFX8-NEXT: v_and_b32_e32 v8, s2, v8 +; GFX8-NEXT: v_and_b32_e32 v9, s2, v9 +; GFX8-NEXT: v_ashrrev_i16_e32 v10, 12, v10 +; GFX8-NEXT: v_ashrrev_i16_e32 v11, 12, v11 +; GFX8-NEXT: s_bfe_i32 s0, s0, 0x40018 +; GFX8-NEXT: v_and_b32_e32 v10, s2, v10 +; GFX8-NEXT: v_and_b32_e32 v11, s2, v11 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_mad_i32_i24 v2, s12, v12, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, v3, v4, v2 +; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX8-NEXT: v_mad_u32_u24 v2, v6, v7, v2 +; GFX8-NEXT: v_mad_i32_i24 v2, s16, v13, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, v8, v9, v2 +; GFX8-NEXT: v_mov_b32_e32 v3, s1 +; GFX8-NEXT: v_mad_i32_i24 v2, s0, v3, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, v10, v11, v2 +; GFX8-NEXT: flat_store_byte v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: idot8_acc8: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NEXT: s_movk_i32 s2, 0xff +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_load_ubyte v2, v[0:1], off +; GFX9-NEXT: s_load_dword s0, s[4:5], 0x0 +; GFX9-NEXT: s_load_dword s1, s[6:7], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_lshr_b32 s7, s0, 4 +; GFX9-NEXT: s_lshr_b32 s11, s1, 4 +; GFX9-NEXT: v_lshlrev_b16_e64 v3, 12, s7 +; GFX9-NEXT: v_lshlrev_b16_e64 v4, 12, s11 +; GFX9-NEXT: s_bfe_i32 s13, s1, 0x40000 +; GFX9-NEXT: v_ashrrev_i16_e32 v3, 12, v3 +; GFX9-NEXT: v_ashrrev_i16_e32 v4, 12, v4 +; GFX9-NEXT: s_lshr_b32 s6, s0, 12 +; GFX9-NEXT: s_lshr_b32 s10, s1, 12 +; GFX9-NEXT: s_bfe_i32 s15, s1, 0x40008 +; GFX9-NEXT: s_bfe_i32 s12, s0, 0x40000 +; GFX9-NEXT: v_mov_b32_e32 v12, s13 +; GFX9-NEXT: v_lshlrev_b16_e64 v6, 12, s6 +; GFX9-NEXT: v_lshlrev_b16_e64 v7, 12, s10 +; GFX9-NEXT: s_bfe_i32 s14, s0, 0x40008 +; GFX9-NEXT: v_mov_b32_e32 v5, s15 +; GFX9-NEXT: v_and_b32_e32 v3, s2, v3 +; GFX9-NEXT: v_and_b32_e32 v4, s2, v4 +; GFX9-NEXT: v_ashrrev_i16_e32 v6, 12, v6 +; GFX9-NEXT: v_ashrrev_i16_e32 v7, 12, v7 +; GFX9-NEXT: s_lshr_b32 s5, s0, 20 +; GFX9-NEXT: s_lshr_b32 s9, s1, 20 +; GFX9-NEXT: v_mul_i32_i24_e32 v5, s14, v5 +; GFX9-NEXT: v_lshlrev_b16_e64 v8, 12, s5 +; GFX9-NEXT: v_lshlrev_b16_e64 v9, 12, s9 +; GFX9-NEXT: s_bfe_i32 s17, s1, 0x40010 +; GFX9-NEXT: v_and_b32_e32 v6, s2, v6 +; GFX9-NEXT: v_and_b32_e32 v7, s2, v7 +; GFX9-NEXT: s_lshr_b32 s8, s1, 28 +; GFX9-NEXT: v_ashrrev_i16_e32 v8, 12, v8 +; GFX9-NEXT: v_ashrrev_i16_e32 v9, 12, v9 +; GFX9-NEXT: s_lshr_b32 s4, s0, 28 +; GFX9-NEXT: s_bfe_i32 s16, s0, 0x40010 +; GFX9-NEXT: v_mov_b32_e32 v13, s17 +; GFX9-NEXT: v_lshlrev_b16_e64 v10, 12, s4 +; GFX9-NEXT: v_lshlrev_b16_e64 v11, 12, s8 +; GFX9-NEXT: s_bfe_i32 s1, s1, 0x40018 +; GFX9-NEXT: v_and_b32_e32 v8, s2, v8 +; GFX9-NEXT: v_and_b32_e32 v9, s2, v9 +; GFX9-NEXT: v_ashrrev_i16_e32 v10, 12, v10 +; GFX9-NEXT: v_ashrrev_i16_e32 v11, 12, v11 +; GFX9-NEXT: s_bfe_i32 s0, s0, 0x40018 +; GFX9-NEXT: v_and_b32_e32 v10, s2, v10 +; GFX9-NEXT: v_and_b32_e32 v11, s2, v11 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_mad_i32_i24 v2, s12, v12, v2 +; GFX9-NEXT: v_mad_u32_u24 v2, v3, v4, v2 +; GFX9-NEXT: v_add_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX9-NEXT: v_mad_u32_u24 v2, v6, v7, v2 +; GFX9-NEXT: v_mad_i32_i24 v2, s16, v13, v2 +; GFX9-NEXT: v_mad_u32_u24 v2, v8, v9, v2 +; GFX9-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-NEXT: v_mad_i32_i24 v2, s0, v3, v2 +; GFX9-NEXT: v_mad_u32_u24 v2, v10, v11, v2 +; GFX9-NEXT: global_store_byte v[0:1], v2, off +; GFX9-NEXT: s_endpgm +; +; GFX9-DL-LABEL: idot8_acc8: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_movk_i32 s2, 0xff +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_load_ubyte v2, v[0:1], off +; GFX9-DL-NEXT: s_load_dword s0, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s1, s[6:7], 0x0 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_lshr_b32 s7, s0, 4 +; GFX9-DL-NEXT: s_lshr_b32 s11, s1, 4 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v3, 12, s7 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v4, 12, s11 +; GFX9-DL-NEXT: s_bfe_i32 s13, s1, 0x40000 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v3, 12, v3 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v4, 12, v4 +; GFX9-DL-NEXT: s_lshr_b32 s6, s0, 12 +; GFX9-DL-NEXT: s_lshr_b32 s10, s1, 12 +; GFX9-DL-NEXT: s_bfe_i32 s15, s1, 0x40008 +; GFX9-DL-NEXT: s_bfe_i32 s12, s0, 0x40000 +; GFX9-DL-NEXT: v_mov_b32_e32 v12, s13 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v6, 12, s6 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v7, 12, s10 +; GFX9-DL-NEXT: s_bfe_i32 s14, s0, 0x40008 +; GFX9-DL-NEXT: v_mov_b32_e32 v5, s15 +; GFX9-DL-NEXT: v_and_b32_e32 v3, s2, v3 +; GFX9-DL-NEXT: v_and_b32_e32 v4, s2, v4 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v6, 12, v6 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v7, 12, v7 +; GFX9-DL-NEXT: s_lshr_b32 s5, s0, 20 +; GFX9-DL-NEXT: s_lshr_b32 s9, s1, 20 +; GFX9-DL-NEXT: v_mul_i32_i24_e32 v5, s14, v5 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v8, 12, s5 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v9, 12, s9 +; GFX9-DL-NEXT: s_bfe_i32 s17, s1, 0x40010 +; GFX9-DL-NEXT: v_and_b32_e32 v6, s2, v6 +; GFX9-DL-NEXT: v_and_b32_e32 v7, s2, v7 +; GFX9-DL-NEXT: s_lshr_b32 s8, s1, 28 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v8, 12, v8 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v9, 12, v9 +; GFX9-DL-NEXT: s_lshr_b32 s4, s0, 28 +; GFX9-DL-NEXT: s_bfe_i32 s16, s0, 0x40010 +; GFX9-DL-NEXT: v_mov_b32_e32 v13, s17 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v10, 12, s4 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v11, 12, s8 +; GFX9-DL-NEXT: s_bfe_i32 s1, s1, 0x40018 +; GFX9-DL-NEXT: v_and_b32_e32 v8, s2, v8 +; GFX9-DL-NEXT: v_and_b32_e32 v9, s2, v9 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v10, 12, v10 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v11, 12, v11 +; GFX9-DL-NEXT: s_bfe_i32 s0, s0, 0x40018 +; GFX9-DL-NEXT: v_and_b32_e32 v10, s2, v10 +; GFX9-DL-NEXT: v_and_b32_e32 v11, s2, v11 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s12, v12, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, v3, v4, v2 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, v6, v7, v2 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s16, v13, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, v8, v9, v2 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s1 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s0, v3, v2 +; GFX9-DL-NEXT: v_mad_u32_u24 v2, v10, v11, v2 +; GFX9-DL-NEXT: global_store_byte v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm + <8 x i4> addrspace(1)* %src2, + i8 addrspace(1)* nocapture %dst) { +entry: + %vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %src1 + %vec2 = load <8 x i4>, <8 x i4> addrspace(1)* %src2 + + %v1e0 = extractelement <8 x i4> %vec1, i64 0 + %cv1e0 = sext i4 %v1e0 to i8 + %v2e0 = extractelement <8 x i4> %vec2, i64 0 + %cv2e0 = sext i4 %v2e0 to i8 + %mul0 = mul nuw nsw i8 %cv1e0, %cv2e0 + + %v1e1 = extractelement <8 x i4> %vec1, i64 1 + %cv1e1 = sext i4 %v1e1 to i8 + %v2e1 = extractelement <8 x i4> %vec2, i64 1 + %cv2e1 = sext i4 %v2e1 to i8 + %mul1 = mul nuw nsw i8 %cv1e1, %cv2e1 + + %v1e2 = extractelement <8 x i4> %vec1, i64 2 + %cv1e2 = sext i4 %v1e2 to i8 + %v2e2 = extractelement <8 x i4> %vec2, i64 2 + %cv2e2 = sext i4 %v2e2 to i8 + %mul2 = mul nuw nsw i8 %cv1e2, %cv2e2 + + %v1e3 = extractelement <8 x i4> %vec1, i64 3 + %cv1e3 = sext i4 %v1e3 to i8 + %v2e3 = extractelement <8 x i4> %vec2, i64 3 + %cv2e3 = sext i4 %v2e3 to i8 + %mul3 = mul nuw nsw i8 %cv1e3, %cv2e3 + + %v1e4 = extractelement <8 x i4> %vec1, i64 4 + %cv1e4 = sext i4 %v1e4 to i8 + %v2e4 = extractelement <8 x i4> %vec2, i64 4 + %cv2e4 = sext i4 %v2e4 to i8 + %mul4 = mul nuw nsw i8 %cv1e4, %cv2e4 + + %v1e5 = extractelement <8 x i4> %vec1, i64 5 + %cv1e5 = sext i4 %v1e5 to i8 + %v2e5 = extractelement <8 x i4> %vec2, i64 5 + %cv2e5 = sext i4 %v2e5 to i8 + %mul5 = mul nuw nsw i8 %cv1e5, %cv2e5 + + %v1e6 = extractelement <8 x i4> %vec1, i64 6 + %cv1e6 = sext i4 %v1e6 to i8 + %v2e6 = extractelement <8 x i4> %vec2, i64 6 + %cv2e6 = sext i4 %v2e6 to i8 + %mul6 = mul nuw nsw i8 %cv1e6, %cv2e6 + + %v1e7 = extractelement <8 x i4> %vec1, i64 7 + %cv1e7 = sext i4 %v1e7 to i8 + %v2e7 = extractelement <8 x i4> %vec2, i64 7 + %cv2e7 = sext i4 %v2e7 to i8 + %mul7 = mul nuw nsw i8 %cv1e7, %cv2e7 + + %acc = load i8, i8 addrspace(1)* %dst, align 4 + %add1 = add i8 %mul0, %acc + %add2 = add i8 %add1, %mul1 + %add3 = add i8 %add2, %mul2 + %add4 = add i8 %add3, %mul3 + %add5 = add i8 %add4, %mul4 + %add6 = add i8 %add5, %mul5 + %add7 = add i8 %add6, %mul6 + %add8 = add i8 %add7, %mul7 + + store i8 %add8, i8 addrspace(1)* %dst, align 4 + ret void +} + +; Make sure the pattern is not recognized if there are multiple uses of the +; intermediate multiplications. +define amdgpu_kernel void @idot8_multiuses_mul1(<8 x i4> addrspace(1)* %src1, +; GFX7-LABEL: idot8_multiuses_mul1: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s7, 0xf000 +; GFX7-NEXT: s_mov_b32 s6, -1 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s0, s[8:9], 0x0 +; GFX7-NEXT: s_load_dword s1, s[10:11], 0x0 +; GFX7-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_bfe_i32 s8, s0, 0x40000 +; GFX7-NEXT: s_bfe_i32 s9, s1, 0x40000 +; GFX7-NEXT: v_mov_b32_e32 v0, s9 +; GFX7-NEXT: v_mov_b32_e32 v1, s2 +; GFX7-NEXT: v_mad_i32_i24 v1, s8, v0, v1 +; GFX7-NEXT: s_bfe_i32 s11, s1, 0x40004 +; GFX7-NEXT: s_bfe_i32 s10, s0, 0x40004 +; GFX7-NEXT: s_bfe_i32 s13, s1, 0x40008 +; GFX7-NEXT: v_mad_i32_i24 v0, s8, v0, v1 +; GFX7-NEXT: v_mov_b32_e32 v2, s11 +; GFX7-NEXT: v_mad_i32_i24 v0, s10, v2, v0 +; GFX7-NEXT: s_bfe_i32 s12, s0, 0x40008 +; GFX7-NEXT: v_mov_b32_e32 v2, s13 +; GFX7-NEXT: s_bfe_i32 s15, s1, 0x4000c +; GFX7-NEXT: v_mad_i32_i24 v0, s12, v2, v0 +; GFX7-NEXT: s_bfe_i32 s14, s0, 0x4000c +; GFX7-NEXT: v_mov_b32_e32 v2, s15 +; GFX7-NEXT: s_bfe_i32 s17, s1, 0x40010 +; GFX7-NEXT: v_mad_i32_i24 v0, s14, v2, v0 +; GFX7-NEXT: s_bfe_i32 s16, s0, 0x40010 +; GFX7-NEXT: v_mov_b32_e32 v2, s17 +; GFX7-NEXT: s_bfe_i32 s19, s1, 0x40014 +; GFX7-NEXT: s_bfe_i32 s21, s1, 0x40018 +; GFX7-NEXT: v_mad_i32_i24 v0, s16, v2, v0 +; GFX7-NEXT: s_bfe_i32 s18, s0, 0x40014 +; GFX7-NEXT: v_mov_b32_e32 v2, s19 +; GFX7-NEXT: s_bfe_i32 s20, s0, 0x40018 +; GFX7-NEXT: v_mad_i32_i24 v0, s18, v2, v0 +; GFX7-NEXT: v_mov_b32_e32 v2, s21 +; GFX7-NEXT: s_ashr_i32 s1, s1, 28 +; GFX7-NEXT: v_mad_i32_i24 v0, s20, v2, v0 +; GFX7-NEXT: s_ashr_i32 s0, s0, 28 +; GFX7-NEXT: v_mov_b32_e32 v2, s1 +; GFX7-NEXT: v_mad_i32_i24 v0, s0, v2, v0 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GFX7-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: idot8_multiuses_mul1: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX8-NEXT: s_load_dword s5, s[0:1], 0x0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_bfe_i32 s0, s2, 0x40000 +; GFX8-NEXT: s_bfe_i32 s1, s4, 0x40000 +; GFX8-NEXT: v_mov_b32_e32 v2, s1 +; GFX8-NEXT: v_mov_b32_e32 v3, s5 +; GFX8-NEXT: v_mad_i32_i24 v3, s0, v2, v3 +; GFX8-NEXT: s_bfe_i32 s7, s4, 0x40004 +; GFX8-NEXT: s_bfe_i32 s6, s2, 0x40004 +; GFX8-NEXT: s_bfe_i32 s9, s4, 0x40008 +; GFX8-NEXT: v_mad_i32_i24 v2, s0, v2, v3 +; GFX8-NEXT: v_mov_b32_e32 v4, s7 +; GFX8-NEXT: v_mad_i32_i24 v2, s6, v4, v2 +; GFX8-NEXT: s_bfe_i32 s8, s2, 0x40008 +; GFX8-NEXT: v_mov_b32_e32 v4, s9 +; GFX8-NEXT: s_bfe_i32 s11, s4, 0x4000c +; GFX8-NEXT: v_mad_i32_i24 v2, s8, v4, v2 +; GFX8-NEXT: s_bfe_i32 s10, s2, 0x4000c +; GFX8-NEXT: v_mov_b32_e32 v4, s11 +; GFX8-NEXT: s_bfe_i32 s13, s4, 0x40010 +; GFX8-NEXT: v_mad_i32_i24 v2, s10, v4, v2 +; GFX8-NEXT: s_bfe_i32 s12, s2, 0x40010 +; GFX8-NEXT: v_mov_b32_e32 v4, s13 +; GFX8-NEXT: s_bfe_i32 s15, s4, 0x40014 +; GFX8-NEXT: s_bfe_i32 s17, s4, 0x40018 +; GFX8-NEXT: v_mad_i32_i24 v2, s12, v4, v2 +; GFX8-NEXT: s_bfe_i32 s14, s2, 0x40014 +; GFX8-NEXT: v_mov_b32_e32 v4, s15 +; GFX8-NEXT: s_bfe_i32 s16, s2, 0x40018 +; GFX8-NEXT: v_mad_i32_i24 v2, s14, v4, v2 +; GFX8-NEXT: v_mov_b32_e32 v4, s17 +; GFX8-NEXT: s_ashr_i32 s4, s4, 28 +; GFX8-NEXT: v_mad_i32_i24 v2, s16, v4, v2 +; GFX8-NEXT: s_ashr_i32 s2, s2, 28 +; GFX8-NEXT: v_mov_b32_e32 v4, s4 +; GFX8-NEXT: v_mad_i32_i24 v2, s2, v4, v2 +; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: idot8_multiuses_mul1: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-NEXT: s_load_dword s5, s[0:1], 0x0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_bfe_i32 s0, s2, 0x40000 +; GFX9-NEXT: s_bfe_i32 s1, s4, 0x40000 +; GFX9-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-NEXT: v_mad_i32_i24 v3, s0, v2, v3 +; GFX9-NEXT: s_bfe_i32 s7, s4, 0x40004 +; GFX9-NEXT: s_bfe_i32 s6, s2, 0x40004 +; GFX9-NEXT: s_bfe_i32 s9, s4, 0x40008 +; GFX9-NEXT: v_mad_i32_i24 v2, s0, v2, v3 +; GFX9-NEXT: v_mov_b32_e32 v4, s7 +; GFX9-NEXT: v_mad_i32_i24 v2, s6, v4, v2 +; GFX9-NEXT: s_bfe_i32 s8, s2, 0x40008 +; GFX9-NEXT: v_mov_b32_e32 v4, s9 +; GFX9-NEXT: s_bfe_i32 s11, s4, 0x4000c +; GFX9-NEXT: v_mad_i32_i24 v2, s8, v4, v2 +; GFX9-NEXT: s_bfe_i32 s10, s2, 0x4000c +; GFX9-NEXT: v_mov_b32_e32 v4, s11 +; GFX9-NEXT: s_bfe_i32 s13, s4, 0x40010 +; GFX9-NEXT: v_mad_i32_i24 v2, s10, v4, v2 +; GFX9-NEXT: s_bfe_i32 s12, s2, 0x40010 +; GFX9-NEXT: v_mov_b32_e32 v4, s13 +; GFX9-NEXT: s_bfe_i32 s15, s4, 0x40014 +; GFX9-NEXT: s_bfe_i32 s17, s4, 0x40018 +; GFX9-NEXT: v_mad_i32_i24 v2, s12, v4, v2 +; GFX9-NEXT: s_bfe_i32 s14, s2, 0x40014 +; GFX9-NEXT: v_mov_b32_e32 v4, s15 +; GFX9-NEXT: s_bfe_i32 s16, s2, 0x40018 +; GFX9-NEXT: v_mad_i32_i24 v2, s14, v4, v2 +; GFX9-NEXT: v_mov_b32_e32 v4, s17 +; GFX9-NEXT: s_ashr_i32 s4, s4, 28 +; GFX9-NEXT: v_mad_i32_i24 v2, s16, v4, v2 +; GFX9-NEXT: s_ashr_i32 s2, s2, 28 +; GFX9-NEXT: v_mov_b32_e32 v4, s4 +; GFX9-NEXT: v_mad_i32_i24 v2, s2, v4, v2 +; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 +; GFX9-NEXT: global_store_dword v[0:1], v2, off +; GFX9-NEXT: s_endpgm +; +; GFX9-DL-LABEL: idot8_multiuses_mul1: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-DL-NEXT: s_load_dword s5, s[0:1], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_bfe_i32 s0, s2, 0x40000 +; GFX9-DL-NEXT: s_bfe_i32 s1, s4, 0x40000 +; GFX9-DL-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-DL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-DL-NEXT: v_mad_i32_i24 v3, s0, v2, v3 +; GFX9-DL-NEXT: s_bfe_i32 s7, s4, 0x40004 +; GFX9-DL-NEXT: s_bfe_i32 s6, s2, 0x40004 +; GFX9-DL-NEXT: s_bfe_i32 s9, s4, 0x40008 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s0, v2, v3 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s7 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s6, v4, v2 +; GFX9-DL-NEXT: s_bfe_i32 s8, s2, 0x40008 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s9 +; GFX9-DL-NEXT: s_bfe_i32 s11, s4, 0x4000c +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s8, v4, v2 +; GFX9-DL-NEXT: s_bfe_i32 s10, s2, 0x4000c +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s11 +; GFX9-DL-NEXT: s_bfe_i32 s13, s4, 0x40010 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s10, v4, v2 +; GFX9-DL-NEXT: s_bfe_i32 s12, s2, 0x40010 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s13 +; GFX9-DL-NEXT: s_bfe_i32 s15, s4, 0x40014 +; GFX9-DL-NEXT: s_bfe_i32 s17, s4, 0x40018 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s12, v4, v2 +; GFX9-DL-NEXT: s_bfe_i32 s14, s2, 0x40014 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s15 +; GFX9-DL-NEXT: s_bfe_i32 s16, s2, 0x40018 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s14, v4, v2 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s17 +; GFX9-DL-NEXT: s_ashr_i32 s4, s4, 28 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s16, v4, v2 +; GFX9-DL-NEXT: s_ashr_i32 s2, s2, 28 +; GFX9-DL-NEXT: v_mov_b32_e32 v4, s4 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s2, v4, v2 +; GFX9-DL-NEXT: v_add_u32_e32 v2, v3, v2 +; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm + <8 x i4> addrspace(1)* %src2, + i32 addrspace(1)* nocapture %dst) { +entry: + %vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %src1 + %vec2 = load <8 x i4>, <8 x i4> addrspace(1)* %src2 + + %v1e0 = extractelement <8 x i4> %vec1, i64 0 + %cv1e0 = sext i4 %v1e0 to i32 + %v2e0 = extractelement <8 x i4> %vec2, i64 0 + %cv2e0 = sext i4 %v2e0 to i32 + %mul0 = mul nuw nsw i32 %cv1e0, %cv2e0 + + %v1e1 = extractelement <8 x i4> %vec1, i64 1 + %cv1e1 = sext i4 %v1e1 to i32 + %v2e1 = extractelement <8 x i4> %vec2, i64 1 + %cv2e1 = sext i4 %v2e1 to i32 + %mul1 = mul nuw nsw i32 %cv1e1, %cv2e1 + + %v1e2 = extractelement <8 x i4> %vec1, i64 2 + %cv1e2 = sext i4 %v1e2 to i32 + %v2e2 = extractelement <8 x i4> %vec2, i64 2 + %cv2e2 = sext i4 %v2e2 to i32 + %mul2 = mul nuw nsw i32 %cv1e2, %cv2e2 + + %v1e3 = extractelement <8 x i4> %vec1, i64 3 + %cv1e3 = sext i4 %v1e3 to i32 + %v2e3 = extractelement <8 x i4> %vec2, i64 3 + %cv2e3 = sext i4 %v2e3 to i32 + %mul3 = mul nuw nsw i32 %cv1e3, %cv2e3 + + %v1e4 = extractelement <8 x i4> %vec1, i64 4 + %cv1e4 = sext i4 %v1e4 to i32 + %v2e4 = extractelement <8 x i4> %vec2, i64 4 + %cv2e4 = sext i4 %v2e4 to i32 + %mul4 = mul nuw nsw i32 %cv1e4, %cv2e4 + + %v1e5 = extractelement <8 x i4> %vec1, i64 5 + %cv1e5 = sext i4 %v1e5 to i32 + %v2e5 = extractelement <8 x i4> %vec2, i64 5 + %cv2e5 = sext i4 %v2e5 to i32 + %mul5 = mul nuw nsw i32 %cv1e5, %cv2e5 + + %v1e6 = extractelement <8 x i4> %vec1, i64 6 + %cv1e6 = sext i4 %v1e6 to i32 + %v2e6 = extractelement <8 x i4> %vec2, i64 6 + %cv2e6 = sext i4 %v2e6 to i32 + %mul6 = mul nuw nsw i32 %cv1e6, %cv2e6 + + %v1e7 = extractelement <8 x i4> %vec1, i64 7 + %cv1e7 = sext i4 %v1e7 to i32 + %v2e7 = extractelement <8 x i4> %vec2, i64 7 + %cv2e7 = sext i4 %v2e7 to i32 + %mul7 = mul nuw nsw i32 %cv1e7, %cv2e7 + + %acc = load i32, i32 addrspace(1)* %dst, align 4 + %add = add i32 %mul0, %acc + %add1 = add i32 %mul0, %add + %add2 = add i32 %add1, %mul1 + %add3 = add i32 %add2, %mul2 + %add4 = add i32 %add3, %mul3 + %add5 = add i32 %add4, %mul4 + %add6 = add i32 %add5, %mul5 + %add7 = add i32 %add6, %mul6 + %add8 = add i32 %add7, %mul7 + + %res = add i32 %add, %add8 + store i32 %res, i32 addrspace(1)* %dst, align 4 + ret void +} + +; TODO: Support this pattern. +define amdgpu_kernel void @idot8_acc32_vecMul(<8 x i4> addrspace(1)* %src1, +; GFX7-LABEL: idot8_acc32_vecMul: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s0, 0 +; GFX7-NEXT: s_mov_b32 s12, s0 +; GFX7-NEXT: s_mov_b32 s14, s0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s1, s[8:9], 0x0 +; GFX7-NEXT: s_load_dword s2, s[10:11], 0x0 +; GFX7-NEXT: s_load_dword s38, s[4:5], 0x0 +; GFX7-NEXT: s_mov_b32 s16, s0 +; GFX7-NEXT: s_mov_b32 s18, s0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_lshl_b32 s13, s1, 4 +; GFX7-NEXT: s_lshl_b32 s15, s1, 12 +; GFX7-NEXT: s_lshl_b32 s17, s1, 16 +; GFX7-NEXT: s_lshl_b32 s19, s1, 20 +; GFX7-NEXT: s_ashr_i64 s[10:11], s[12:13], 60 +; GFX7-NEXT: s_lshl_b32 s13, s1, 8 +; GFX7-NEXT: s_ashr_i64 s[8:9], s[0:1], 60 +; GFX7-NEXT: s_lshl_b32 s21, s1, 24 +; GFX7-NEXT: s_lshl_b32 s1, s1, 28 +; GFX7-NEXT: s_ashr_i64 s[22:23], s[0:1], 60 +; GFX7-NEXT: s_mov_b32 s1, s2 +; GFX7-NEXT: s_ashr_i64 s[24:25], s[0:1], 60 +; GFX7-NEXT: s_lshl_b32 s1, s2, 4 +; GFX7-NEXT: s_ashr_i64 s[26:27], s[0:1], 60 +; GFX7-NEXT: s_lshl_b32 s1, s2, 8 +; GFX7-NEXT: s_ashr_i64 s[28:29], s[0:1], 60 +; GFX7-NEXT: s_lshl_b32 s1, s2, 12 +; GFX7-NEXT: s_ashr_i64 s[30:31], s[0:1], 60 +; GFX7-NEXT: s_lshl_b32 s1, s2, 16 +; GFX7-NEXT: s_ashr_i64 s[32:33], s[0:1], 60 +; GFX7-NEXT: s_lshl_b32 s1, s2, 20 +; GFX7-NEXT: s_ashr_i64 s[34:35], s[0:1], 60 +; GFX7-NEXT: s_lshl_b32 s1, s2, 24 +; GFX7-NEXT: s_ashr_i64 s[36:37], s[0:1], 60 +; GFX7-NEXT: s_lshl_b32 s1, s2, 28 +; GFX7-NEXT: s_mov_b32 s20, s0 +; GFX7-NEXT: s_ashr_i64 s[0:1], s[0:1], 60 +; GFX7-NEXT: v_mov_b32_e32 v0, s0 +; GFX7-NEXT: v_mov_b32_e32 v1, s38 +; GFX7-NEXT: v_mad_i32_i24 v0, s22, v0, v1 +; GFX7-NEXT: s_ashr_i64 s[20:21], s[20:21], 60 +; GFX7-NEXT: v_mov_b32_e32 v1, s36 +; GFX7-NEXT: v_mad_i32_i24 v0, s20, v1, v0 +; GFX7-NEXT: s_ashr_i64 s[18:19], s[18:19], 60 +; GFX7-NEXT: v_mov_b32_e32 v1, s34 +; GFX7-NEXT: v_mad_i32_i24 v0, s18, v1, v0 +; GFX7-NEXT: s_ashr_i64 s[16:17], s[16:17], 60 +; GFX7-NEXT: v_mov_b32_e32 v1, s32 +; GFX7-NEXT: v_mad_i32_i24 v0, s16, v1, v0 +; GFX7-NEXT: s_ashr_i64 s[14:15], s[14:15], 60 +; GFX7-NEXT: v_mov_b32_e32 v1, s30 +; GFX7-NEXT: v_mad_i32_i24 v0, s14, v1, v0 +; GFX7-NEXT: s_ashr_i64 s[12:13], s[12:13], 60 +; GFX7-NEXT: v_mov_b32_e32 v1, s28 +; GFX7-NEXT: v_mad_i32_i24 v0, s12, v1, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, s26 +; GFX7-NEXT: v_mad_i32_i24 v0, s10, v1, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, s24 +; GFX7-NEXT: s_mov_b32 s7, 0xf000 +; GFX7-NEXT: s_mov_b32 s6, -1 +; GFX7-NEXT: v_mad_i32_i24 v0, s8, v1, v0 +; GFX7-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: idot8_acc32_vecMul: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_mov_b32 s8, 0 +; GFX8-NEXT: s_mov_b32 s10, s8 +; GFX8-NEXT: s_mov_b32 s12, s8 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_load_dword s9, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s2, s[6:7], 0x0 +; GFX8-NEXT: s_load_dword s36, s[0:1], 0x0 +; GFX8-NEXT: s_mov_b32 s14, s8 +; GFX8-NEXT: s_mov_b32 s16, s8 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_lshl_b32 s11, s9, 4 +; GFX8-NEXT: s_lshl_b32 s13, s9, 8 +; GFX8-NEXT: s_lshl_b32 s15, s9, 16 +; GFX8-NEXT: s_lshl_b32 s17, s9, 20 +; GFX8-NEXT: s_ashr_i64 s[6:7], s[10:11], 60 +; GFX8-NEXT: s_ashr_i64 s[10:11], s[12:13], 60 +; GFX8-NEXT: s_lshl_b32 s13, s9, 12 +; GFX8-NEXT: s_ashr_i64 s[4:5], s[8:9], 60 +; GFX8-NEXT: s_lshl_b32 s19, s9, 24 +; GFX8-NEXT: s_lshl_b32 s9, s9, 28 +; GFX8-NEXT: s_ashr_i64 s[20:21], s[8:9], 60 +; GFX8-NEXT: s_mov_b32 s9, s2 +; GFX8-NEXT: s_ashr_i64 s[22:23], s[8:9], 60 +; GFX8-NEXT: s_lshl_b32 s9, s2, 4 +; GFX8-NEXT: s_ashr_i64 s[24:25], s[8:9], 60 +; GFX8-NEXT: s_lshl_b32 s9, s2, 8 +; GFX8-NEXT: s_ashr_i64 s[26:27], s[8:9], 60 +; GFX8-NEXT: s_lshl_b32 s9, s2, 12 +; GFX8-NEXT: s_ashr_i64 s[28:29], s[8:9], 60 +; GFX8-NEXT: s_lshl_b32 s9, s2, 16 +; GFX8-NEXT: s_ashr_i64 s[30:31], s[8:9], 60 +; GFX8-NEXT: s_lshl_b32 s9, s2, 20 +; GFX8-NEXT: s_ashr_i64 s[32:33], s[8:9], 60 +; GFX8-NEXT: s_lshl_b32 s9, s2, 24 +; GFX8-NEXT: s_ashr_i64 s[34:35], s[8:9], 60 +; GFX8-NEXT: s_lshl_b32 s9, s2, 28 +; GFX8-NEXT: s_mov_b32 s18, s8 +; GFX8-NEXT: s_ashr_i64 s[8:9], s[8:9], 60 +; GFX8-NEXT: v_mov_b32_e32 v0, s8 +; GFX8-NEXT: v_mov_b32_e32 v1, s36 +; GFX8-NEXT: v_mad_i32_i24 v0, s20, v0, v1 +; GFX8-NEXT: s_ashr_i64 s[18:19], s[18:19], 60 +; GFX8-NEXT: v_mov_b32_e32 v1, s34 +; GFX8-NEXT: v_mad_i32_i24 v0, s18, v1, v0 +; GFX8-NEXT: s_ashr_i64 s[16:17], s[16:17], 60 +; GFX8-NEXT: v_mov_b32_e32 v1, s32 +; GFX8-NEXT: v_mad_i32_i24 v0, s16, v1, v0 +; GFX8-NEXT: s_ashr_i64 s[14:15], s[14:15], 60 +; GFX8-NEXT: v_mov_b32_e32 v1, s30 +; GFX8-NEXT: v_mad_i32_i24 v0, s14, v1, v0 +; GFX8-NEXT: s_ashr_i64 s[12:13], s[12:13], 60 +; GFX8-NEXT: v_mov_b32_e32 v1, s28 +; GFX8-NEXT: v_mad_i32_i24 v0, s12, v1, v0 +; GFX8-NEXT: v_mov_b32_e32 v1, s26 +; GFX8-NEXT: v_mad_i32_i24 v0, s10, v1, v0 +; GFX8-NEXT: v_mov_b32_e32 v1, s24 +; GFX8-NEXT: v_mad_i32_i24 v0, s6, v1, v0 +; GFX8-NEXT: v_mov_b32_e32 v1, s22 +; GFX8-NEXT: v_mad_i32_i24 v2, s4, v1, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: idot8_acc32_vecMul: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NEXT: s_mov_b32 s8, 0 +; GFX9-NEXT: s_mov_b32 s10, s8 +; GFX9-NEXT: s_mov_b32 s12, s8 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dword s9, s[4:5], 0x0 +; GFX9-NEXT: s_load_dword s2, s[6:7], 0x0 +; GFX9-NEXT: s_load_dword s36, s[0:1], 0x0 +; GFX9-NEXT: s_mov_b32 s14, s8 +; GFX9-NEXT: s_mov_b32 s16, s8 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_lshl_b32 s11, s9, 4 +; GFX9-NEXT: s_lshl_b32 s13, s9, 8 +; GFX9-NEXT: s_lshl_b32 s15, s9, 16 +; GFX9-NEXT: s_lshl_b32 s17, s9, 20 +; GFX9-NEXT: s_ashr_i64 s[6:7], s[10:11], 60 +; GFX9-NEXT: s_ashr_i64 s[10:11], s[12:13], 60 +; GFX9-NEXT: s_lshl_b32 s13, s9, 12 +; GFX9-NEXT: s_ashr_i64 s[4:5], s[8:9], 60 +; GFX9-NEXT: s_lshl_b32 s19, s9, 24 +; GFX9-NEXT: s_lshl_b32 s9, s9, 28 +; GFX9-NEXT: s_ashr_i64 s[20:21], s[8:9], 60 +; GFX9-NEXT: s_mov_b32 s9, s2 +; GFX9-NEXT: s_ashr_i64 s[22:23], s[8:9], 60 +; GFX9-NEXT: s_lshl_b32 s9, s2, 4 +; GFX9-NEXT: s_ashr_i64 s[24:25], s[8:9], 60 +; GFX9-NEXT: s_lshl_b32 s9, s2, 8 +; GFX9-NEXT: s_ashr_i64 s[26:27], s[8:9], 60 +; GFX9-NEXT: s_lshl_b32 s9, s2, 12 +; GFX9-NEXT: s_ashr_i64 s[28:29], s[8:9], 60 +; GFX9-NEXT: s_lshl_b32 s9, s2, 16 +; GFX9-NEXT: s_ashr_i64 s[30:31], s[8:9], 60 +; GFX9-NEXT: s_lshl_b32 s9, s2, 20 +; GFX9-NEXT: s_ashr_i64 s[32:33], s[8:9], 60 +; GFX9-NEXT: s_lshl_b32 s9, s2, 24 +; GFX9-NEXT: s_ashr_i64 s[34:35], s[8:9], 60 +; GFX9-NEXT: s_lshl_b32 s9, s2, 28 +; GFX9-NEXT: s_mov_b32 s18, s8 +; GFX9-NEXT: s_ashr_i64 s[8:9], s[8:9], 60 +; GFX9-NEXT: v_mov_b32_e32 v0, s8 +; GFX9-NEXT: v_mov_b32_e32 v1, s36 +; GFX9-NEXT: v_mad_i32_i24 v0, s20, v0, v1 +; GFX9-NEXT: s_ashr_i64 s[18:19], s[18:19], 60 +; GFX9-NEXT: v_mov_b32_e32 v1, s34 +; GFX9-NEXT: v_mad_i32_i24 v0, s18, v1, v0 +; GFX9-NEXT: s_ashr_i64 s[16:17], s[16:17], 60 +; GFX9-NEXT: v_mov_b32_e32 v1, s32 +; GFX9-NEXT: v_mad_i32_i24 v0, s16, v1, v0 +; GFX9-NEXT: s_ashr_i64 s[14:15], s[14:15], 60 +; GFX9-NEXT: v_mov_b32_e32 v1, s30 +; GFX9-NEXT: v_mad_i32_i24 v0, s14, v1, v0 +; GFX9-NEXT: s_ashr_i64 s[12:13], s[12:13], 60 +; GFX9-NEXT: v_mov_b32_e32 v1, s28 +; GFX9-NEXT: v_mad_i32_i24 v0, s12, v1, v0 +; GFX9-NEXT: v_mov_b32_e32 v1, s26 +; GFX9-NEXT: v_mad_i32_i24 v0, s10, v1, v0 +; GFX9-NEXT: v_mov_b32_e32 v1, s24 +; GFX9-NEXT: v_mad_i32_i24 v0, s6, v1, v0 +; GFX9-NEXT: v_mov_b32_e32 v1, s22 +; GFX9-NEXT: v_mad_i32_i24 v2, s4, v1, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dword v[0:1], v2, off +; GFX9-NEXT: s_endpgm +; +; GFX9-DL-LABEL: idot8_acc32_vecMul: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_mov_b32 s8, 0 +; GFX9-DL-NEXT: s_mov_b32 s10, s8 +; GFX9-DL-NEXT: s_mov_b32 s12, s8 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s9, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s2, s[6:7], 0x0 +; GFX9-DL-NEXT: s_load_dword s36, s[0:1], 0x0 +; GFX9-DL-NEXT: s_mov_b32 s14, s8 +; GFX9-DL-NEXT: s_mov_b32 s16, s8 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_lshl_b32 s11, s9, 4 +; GFX9-DL-NEXT: s_lshl_b32 s13, s9, 8 +; GFX9-DL-NEXT: s_lshl_b32 s15, s9, 16 +; GFX9-DL-NEXT: s_lshl_b32 s17, s9, 20 +; GFX9-DL-NEXT: s_ashr_i64 s[6:7], s[10:11], 60 +; GFX9-DL-NEXT: s_ashr_i64 s[10:11], s[12:13], 60 +; GFX9-DL-NEXT: s_lshl_b32 s13, s9, 12 +; GFX9-DL-NEXT: s_ashr_i64 s[4:5], s[8:9], 60 +; GFX9-DL-NEXT: s_lshl_b32 s19, s9, 24 +; GFX9-DL-NEXT: s_lshl_b32 s9, s9, 28 +; GFX9-DL-NEXT: s_ashr_i64 s[20:21], s[8:9], 60 +; GFX9-DL-NEXT: s_mov_b32 s9, s2 +; GFX9-DL-NEXT: s_ashr_i64 s[22:23], s[8:9], 60 +; GFX9-DL-NEXT: s_lshl_b32 s9, s2, 4 +; GFX9-DL-NEXT: s_ashr_i64 s[24:25], s[8:9], 60 +; GFX9-DL-NEXT: s_lshl_b32 s9, s2, 8 +; GFX9-DL-NEXT: s_ashr_i64 s[26:27], s[8:9], 60 +; GFX9-DL-NEXT: s_lshl_b32 s9, s2, 12 +; GFX9-DL-NEXT: s_ashr_i64 s[28:29], s[8:9], 60 +; GFX9-DL-NEXT: s_lshl_b32 s9, s2, 16 +; GFX9-DL-NEXT: s_ashr_i64 s[30:31], s[8:9], 60 +; GFX9-DL-NEXT: s_lshl_b32 s9, s2, 20 +; GFX9-DL-NEXT: s_ashr_i64 s[32:33], s[8:9], 60 +; GFX9-DL-NEXT: s_lshl_b32 s9, s2, 24 +; GFX9-DL-NEXT: s_ashr_i64 s[34:35], s[8:9], 60 +; GFX9-DL-NEXT: s_lshl_b32 s9, s2, 28 +; GFX9-DL-NEXT: s_mov_b32 s18, s8 +; GFX9-DL-NEXT: s_ashr_i64 s[8:9], s[8:9], 60 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s8 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s36 +; GFX9-DL-NEXT: v_mad_i32_i24 v0, s20, v0, v1 +; GFX9-DL-NEXT: s_ashr_i64 s[18:19], s[18:19], 60 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s34 +; GFX9-DL-NEXT: v_mad_i32_i24 v0, s18, v1, v0 +; GFX9-DL-NEXT: s_ashr_i64 s[16:17], s[16:17], 60 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s32 +; GFX9-DL-NEXT: v_mad_i32_i24 v0, s16, v1, v0 +; GFX9-DL-NEXT: s_ashr_i64 s[14:15], s[14:15], 60 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s30 +; GFX9-DL-NEXT: v_mad_i32_i24 v0, s14, v1, v0 +; GFX9-DL-NEXT: s_ashr_i64 s[12:13], s[12:13], 60 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s28 +; GFX9-DL-NEXT: v_mad_i32_i24 v0, s12, v1, v0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s26 +; GFX9-DL-NEXT: v_mad_i32_i24 v0, s10, v1, v0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s24 +; GFX9-DL-NEXT: v_mad_i32_i24 v0, s6, v1, v0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s22 +; GFX9-DL-NEXT: v_mad_i32_i24 v2, s4, v1, v0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_store_dword v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm + <8 x i4> addrspace(1)* %src2, + i32 addrspace(1)* nocapture %dst) { +entry: + %vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %src1 + %vec2 = load <8 x i4>, <8 x i4> addrspace(1)* %src2 + + %cvec1 = sext <8 x i4> %vec1 to <8 x i32> + %cvec2 = sext <8 x i4> %vec2 to <8 x i32> + + %mul = mul <8 x i32> %cvec1, %cvec2 + %mul0 = extractelement <8 x i32> %mul, i64 0 + %mul1 = extractelement <8 x i32> %mul, i64 1 + %mul2 = extractelement <8 x i32> %mul, i64 2 + %mul3 = extractelement <8 x i32> %mul, i64 3 + %mul4 = extractelement <8 x i32> %mul, i64 4 + %mul5 = extractelement <8 x i32> %mul, i64 5 + %mul6 = extractelement <8 x i32> %mul, i64 6 + %mul7 = extractelement <8 x i32> %mul, i64 7 + + %acc = load i32, i32 addrspace(1)* %dst, align 4 + %add1 = add i32 %mul0, %acc + %add2 = add i32 %add1, %mul1 + %add3 = add i32 %add2, %mul2 + %add4 = add i32 %add3, %mul3 + %add5 = add i32 %add4, %mul4 + %add6 = add i32 %add5, %mul5 + %add7 = add i32 %add6, %mul6 + %add8 = add i32 %add7, %mul7 + + store i32 %add8, i32 addrspace(1)* %dst, align 4 + ret void +} + +; TODO: Support this pattern. +define amdgpu_kernel void @idot8_acc16_vecMul(<8 x i4> addrspace(1)* %src1, +; GFX7-LABEL: idot8_acc16_vecMul: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s7, 0xf000 +; GFX7-NEXT: s_mov_b32 s6, -1 +; GFX7-NEXT: s_mov_b32 s0, 0xffff +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s1, s[8:9], 0x0 +; GFX7-NEXT: buffer_load_ushort v0, off, s[4:7], 0 +; GFX7-NEXT: s_load_dword s2, s[10:11], 0x0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_bfe_i32 s8, s1, 0x40010 +; GFX7-NEXT: s_bfe_i32 s9, s1, 0x40014 +; GFX7-NEXT: s_bfe_i32 s15, s2, 0x40010 +; GFX7-NEXT: s_bfe_i32 s16, s2, 0x40014 +; GFX7-NEXT: s_bfe_i32 s17, s2, 0x40018 +; GFX7-NEXT: s_ashr_i32 s18, s2, 28 +; GFX7-NEXT: s_bfe_i32 s19, s2, 0x40000 +; GFX7-NEXT: s_bfe_i32 s20, s2, 0x40004 +; GFX7-NEXT: s_bfe_i32 s21, s2, 0x40008 +; GFX7-NEXT: s_bfe_i32 s2, s2, 0x4000c +; GFX7-NEXT: s_bfe_i32 s10, s1, 0x40018 +; GFX7-NEXT: s_ashr_i32 s11, s1, 28 +; GFX7-NEXT: s_bfe_i32 s12, s1, 0x40000 +; GFX7-NEXT: v_mov_b32_e32 v4, s19 +; GFX7-NEXT: s_bfe_i32 s13, s1, 0x40004 +; GFX7-NEXT: v_mov_b32_e32 v3, s20 +; GFX7-NEXT: s_bfe_i32 s14, s1, 0x40008 +; GFX7-NEXT: v_mov_b32_e32 v2, s21 +; GFX7-NEXT: s_bfe_i32 s1, s1, 0x4000c +; GFX7-NEXT: v_mov_b32_e32 v1, s2 +; GFX7-NEXT: v_mov_b32_e32 v5, s18 +; GFX7-NEXT: v_mov_b32_e32 v6, s17 +; GFX7-NEXT: v_mul_i32_i24_e32 v1, s1, v1 +; GFX7-NEXT: v_mul_i32_i24_e32 v2, s14, v2 +; GFX7-NEXT: v_mul_i32_i24_e32 v3, s13, v3 +; GFX7-NEXT: v_mul_i32_i24_e32 v4, s12, v4 +; GFX7-NEXT: v_mul_i32_i24_e32 v5, s11, v5 +; GFX7-NEXT: v_mul_i32_i24_e32 v6, s10, v6 +; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX7-NEXT: v_and_b32_e32 v2, s0, v2 +; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GFX7-NEXT: v_and_b32_e32 v4, s0, v4 +; GFX7-NEXT: v_or_b32_e32 v1, v2, v1 +; GFX7-NEXT: v_or_b32_e32 v2, v4, v3 +; GFX7-NEXT: v_lshlrev_b32_e32 v5, 16, v5 +; GFX7-NEXT: v_and_b32_e32 v6, s0, v6 +; GFX7-NEXT: v_mov_b32_e32 v7, s16 +; GFX7-NEXT: v_mov_b32_e32 v8, s15 +; GFX7-NEXT: v_or_b32_e32 v3, v6, v5 +; GFX7-NEXT: v_alignbit_b32 v5, v1, v2, 16 +; GFX7-NEXT: v_mul_i32_i24_e32 v7, s9, v7 +; GFX7-NEXT: v_mul_i32_i24_e32 v8, s8, v8 +; GFX7-NEXT: v_lshlrev_b32_e32 v7, 16, v7 +; GFX7-NEXT: v_and_b32_e32 v8, s0, v8 +; GFX7-NEXT: v_lshrrev_b32_e32 v6, 16, v1 +; GFX7-NEXT: v_or_b32_e32 v4, v8, v7 +; GFX7-NEXT: v_lshrrev_b32_e32 v7, 16, v4 +; GFX7-NEXT: v_lshrrev_b32_e32 v8, 16, v3 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v5, v0 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v6, v0 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v4, v0 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v7, v0 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v3, v0 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v8, v0 +; GFX7-NEXT: buffer_store_short v0, off, s[4:7], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: idot8_acc16_vecMul: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ushort v2, v[0:1] +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_lshlrev_b16_e64 v3, 12, s2 +; GFX8-NEXT: v_lshlrev_b16_e64 v4, 12, s4 +; GFX8-NEXT: s_lshr_b32 s0, s2, 4 +; GFX8-NEXT: s_lshr_b32 s1, s2, 8 +; GFX8-NEXT: s_lshr_b32 s5, s4, 4 +; GFX8-NEXT: s_lshr_b32 s6, s4, 8 +; GFX8-NEXT: v_lshlrev_b16_e64 v5, 12, s1 +; GFX8-NEXT: v_lshlrev_b16_e64 v6, 12, s0 +; GFX8-NEXT: v_lshlrev_b16_e64 v7, 12, s6 +; GFX8-NEXT: v_lshlrev_b16_e64 v8, 12, s5 +; GFX8-NEXT: v_ashrrev_i16_e32 v3, 12, v3 +; GFX8-NEXT: v_ashrrev_i16_e32 v4, 12, v4 +; GFX8-NEXT: s_lshr_b32 s0, s2, 12 +; GFX8-NEXT: s_lshr_b32 s1, s4, 12 +; GFX8-NEXT: v_ashrrev_i16_e32 v6, 12, v6 +; GFX8-NEXT: v_ashrrev_i16_e32 v5, 12, v5 +; GFX8-NEXT: v_ashrrev_i16_e32 v7, 12, v7 +; GFX8-NEXT: v_ashrrev_i16_e32 v8, 12, v8 +; GFX8-NEXT: v_lshlrev_b16_e64 v9, 12, s0 +; GFX8-NEXT: v_lshlrev_b16_e64 v10, 12, s1 +; GFX8-NEXT: s_lshr_b32 s5, s2, 16 +; GFX8-NEXT: s_lshr_b32 s6, s4, 16 +; GFX8-NEXT: v_mul_u32_u24_e32 v5, v5, v7 +; GFX8-NEXT: v_lshlrev_b16_e64 v11, 12, s5 +; GFX8-NEXT: v_lshlrev_b16_e64 v12, 12, s6 +; GFX8-NEXT: s_lshr_b32 s0, s2, 20 +; GFX8-NEXT: s_lshr_b32 s1, s4, 20 +; GFX8-NEXT: v_ashrrev_i16_e32 v9, 12, v9 +; GFX8-NEXT: v_ashrrev_i16_e32 v10, 12, v10 +; GFX8-NEXT: v_lshlrev_b16_e64 v13, 12, s0 +; GFX8-NEXT: v_lshlrev_b16_e64 v14, 12, s1 +; GFX8-NEXT: s_lshr_b32 s5, s2, 24 +; GFX8-NEXT: s_lshr_b32 s6, s4, 24 +; GFX8-NEXT: v_ashrrev_i16_e32 v11, 12, v11 +; GFX8-NEXT: v_ashrrev_i16_e32 v12, 12, v12 +; GFX8-NEXT: v_lshlrev_b16_e64 v15, 12, s5 +; GFX8-NEXT: v_lshlrev_b16_e64 v17, 12, s6 +; GFX8-NEXT: s_lshr_b32 s0, s2, 28 +; GFX8-NEXT: s_lshr_b32 s1, s4, 28 +; GFX8-NEXT: v_ashrrev_i16_e32 v13, 12, v13 +; GFX8-NEXT: v_ashrrev_i16_e32 v14, 12, v14 +; GFX8-NEXT: v_lshlrev_b16_e64 v16, 12, s0 +; GFX8-NEXT: v_lshlrev_b16_e64 v18, 12, s1 +; GFX8-NEXT: v_ashrrev_i16_e32 v15, 12, v15 +; GFX8-NEXT: v_ashrrev_i16_e32 v17, 12, v17 +; GFX8-NEXT: v_ashrrev_i16_e32 v16, 12, v16 +; GFX8-NEXT: v_ashrrev_i16_e32 v18, 12, v18 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_mad_u32_u24 v2, v3, v4, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, v6, v8, v2 +; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0 +; GFX8-NEXT: v_mad_u32_u24 v2, v9, v10, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, v11, v12, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, v13, v14, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, v15, v17, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, v16, v18, v2 +; GFX8-NEXT: flat_store_short v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: idot8_acc16_vecMul: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_load_ushort v2, v[0:1], off +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_and_b32 s0, s2, 15 +; GFX9-NEXT: s_bfe_u32 s1, s2, 0x40004 +; GFX9-NEXT: s_and_b32 s5, s4, 15 +; GFX9-NEXT: s_bfe_u32 s6, s4, 0x40004 +; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1 +; GFX9-NEXT: s_pack_ll_b32_b16 s1, s5, s6 +; GFX9-NEXT: s_bfe_u32 s5, s2, 0x40008 +; GFX9-NEXT: s_bfe_u32 s6, s2, 0x4000c +; GFX9-NEXT: v_pk_lshlrev_b16 v3, 12, s0 op_sel_hi:[0,1] +; GFX9-NEXT: s_pack_ll_b32_b16 s0, s5, s6 +; GFX9-NEXT: s_bfe_u32 s9, s2, 0x40010 +; GFX9-NEXT: s_bfe_u32 s10, s2, 0x40014 +; GFX9-NEXT: v_pk_lshlrev_b16 v4, 12, s0 op_sel_hi:[0,1] +; GFX9-NEXT: s_bfe_u32 s13, s2, 0x40018 +; GFX9-NEXT: s_pack_ll_b32_b16 s0, s9, s10 +; GFX9-NEXT: s_lshr_b32 s2, s2, 28 +; GFX9-NEXT: v_pk_lshlrev_b16 v5, 12, s0 op_sel_hi:[0,1] +; GFX9-NEXT: v_pk_lshlrev_b16 v7, 12, s1 op_sel_hi:[0,1] +; GFX9-NEXT: s_pack_ll_b32_b16 s0, s13, s2 +; GFX9-NEXT: s_bfe_u32 s7, s4, 0x40008 +; GFX9-NEXT: s_bfe_u32 s8, s4, 0x4000c +; GFX9-NEXT: v_pk_lshlrev_b16 v6, 12, s0 op_sel_hi:[0,1] +; GFX9-NEXT: s_pack_ll_b32_b16 s0, s7, s8 +; GFX9-NEXT: v_pk_ashrrev_i16 v3, 12, v3 op_sel_hi:[0,1] +; GFX9-NEXT: v_pk_ashrrev_i16 v7, 12, v7 op_sel_hi:[0,1] +; GFX9-NEXT: v_pk_lshlrev_b16 v8, 12, s0 op_sel_hi:[0,1] +; GFX9-NEXT: v_pk_mul_lo_u16 v3, v3, v7 +; GFX9-NEXT: s_bfe_u32 s11, s4, 0x40010 +; GFX9-NEXT: s_bfe_u32 s12, s4, 0x40014 +; GFX9-NEXT: s_pack_ll_b32_b16 s0, s11, s12 +; GFX9-NEXT: v_pk_ashrrev_i16 v4, 12, v4 op_sel_hi:[0,1] +; GFX9-NEXT: v_pk_ashrrev_i16 v8, 12, v8 op_sel_hi:[0,1] +; GFX9-NEXT: v_pk_lshlrev_b16 v9, 12, s0 op_sel_hi:[0,1] +; GFX9-NEXT: s_bfe_u32 s14, s4, 0x40018 +; GFX9-NEXT: s_lshr_b32 s4, s4, 28 +; GFX9-NEXT: v_pk_mul_lo_u16 v4, v4, v8 +; GFX9-NEXT: s_pack_ll_b32_b16 s0, s14, s4 +; GFX9-NEXT: v_pk_ashrrev_i16 v5, 12, v5 op_sel_hi:[0,1] +; GFX9-NEXT: v_pk_ashrrev_i16 v9, 12, v9 op_sel_hi:[0,1] +; GFX9-NEXT: v_pk_lshlrev_b16 v10, 12, s0 op_sel_hi:[0,1] +; GFX9-NEXT: v_pk_mul_lo_u16 v5, v5, v9 +; GFX9-NEXT: v_pk_ashrrev_i16 v6, 12, v6 op_sel_hi:[0,1] +; GFX9-NEXT: v_pk_ashrrev_i16 v10, 12, v10 op_sel_hi:[0,1] +; GFX9-NEXT: v_pk_mul_lo_u16 v6, v6, v10 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 +; GFX9-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0 +; GFX9-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_add_u32_e32 v2, v2, v5 +; GFX9-NEXT: v_add_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_add_u32_e32 v2, v2, v6 +; GFX9-NEXT: v_add_u32_sdwa v2, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: global_store_short v[0:1], v2, off +; GFX9-NEXT: s_endpgm +; +; GFX9-DL-LABEL: idot8_acc16_vecMul: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_load_ushort v2, v[0:1], off +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_and_b32 s0, s2, 15 +; GFX9-DL-NEXT: s_bfe_u32 s1, s2, 0x40004 +; GFX9-DL-NEXT: s_and_b32 s5, s4, 15 +; GFX9-DL-NEXT: s_bfe_u32 s6, s4, 0x40004 +; GFX9-DL-NEXT: s_pack_ll_b32_b16 s0, s0, s1 +; GFX9-DL-NEXT: s_pack_ll_b32_b16 s1, s5, s6 +; GFX9-DL-NEXT: s_bfe_u32 s5, s2, 0x40008 +; GFX9-DL-NEXT: s_bfe_u32 s6, s2, 0x4000c +; GFX9-DL-NEXT: v_pk_lshlrev_b16 v3, 12, s0 op_sel_hi:[0,1] +; GFX9-DL-NEXT: s_pack_ll_b32_b16 s0, s5, s6 +; GFX9-DL-NEXT: s_bfe_u32 s9, s2, 0x40010 +; GFX9-DL-NEXT: s_bfe_u32 s10, s2, 0x40014 +; GFX9-DL-NEXT: v_pk_lshlrev_b16 v4, 12, s0 op_sel_hi:[0,1] +; GFX9-DL-NEXT: s_bfe_u32 s13, s2, 0x40018 +; GFX9-DL-NEXT: s_pack_ll_b32_b16 s0, s9, s10 +; GFX9-DL-NEXT: s_lshr_b32 s2, s2, 28 +; GFX9-DL-NEXT: v_pk_lshlrev_b16 v5, 12, s0 op_sel_hi:[0,1] +; GFX9-DL-NEXT: v_pk_lshlrev_b16 v7, 12, s1 op_sel_hi:[0,1] +; GFX9-DL-NEXT: s_pack_ll_b32_b16 s0, s13, s2 +; GFX9-DL-NEXT: s_bfe_u32 s7, s4, 0x40008 +; GFX9-DL-NEXT: s_bfe_u32 s8, s4, 0x4000c +; GFX9-DL-NEXT: v_pk_lshlrev_b16 v6, 12, s0 op_sel_hi:[0,1] +; GFX9-DL-NEXT: s_pack_ll_b32_b16 s0, s7, s8 +; GFX9-DL-NEXT: v_pk_ashrrev_i16 v3, 12, v3 op_sel_hi:[0,1] +; GFX9-DL-NEXT: v_pk_ashrrev_i16 v7, 12, v7 op_sel_hi:[0,1] +; GFX9-DL-NEXT: v_pk_lshlrev_b16 v8, 12, s0 op_sel_hi:[0,1] +; GFX9-DL-NEXT: v_pk_mul_lo_u16 v3, v3, v7 +; GFX9-DL-NEXT: s_bfe_u32 s11, s4, 0x40010 +; GFX9-DL-NEXT: s_bfe_u32 s12, s4, 0x40014 +; GFX9-DL-NEXT: s_pack_ll_b32_b16 s0, s11, s12 +; GFX9-DL-NEXT: v_pk_ashrrev_i16 v4, 12, v4 op_sel_hi:[0,1] +; GFX9-DL-NEXT: v_pk_ashrrev_i16 v8, 12, v8 op_sel_hi:[0,1] +; GFX9-DL-NEXT: v_pk_lshlrev_b16 v9, 12, s0 op_sel_hi:[0,1] +; GFX9-DL-NEXT: s_bfe_u32 s14, s4, 0x40018 +; GFX9-DL-NEXT: s_lshr_b32 s4, s4, 28 +; GFX9-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v8 +; GFX9-DL-NEXT: s_pack_ll_b32_b16 s0, s14, s4 +; GFX9-DL-NEXT: v_pk_ashrrev_i16 v5, 12, v5 op_sel_hi:[0,1] +; GFX9-DL-NEXT: v_pk_ashrrev_i16 v9, 12, v9 op_sel_hi:[0,1] +; GFX9-DL-NEXT: v_pk_lshlrev_b16 v10, 12, s0 op_sel_hi:[0,1] +; GFX9-DL-NEXT: v_pk_mul_lo_u16 v5, v5, v9 +; GFX9-DL-NEXT: v_pk_ashrrev_i16 v6, 12, v6 op_sel_hi:[0,1] +; GFX9-DL-NEXT: v_pk_ashrrev_i16 v10, 12, v10 op_sel_hi:[0,1] +; GFX9-DL-NEXT: v_pk_mul_lo_u16 v6, v6, v10 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_add_u32_e32 v2, v3, v2 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v5 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v6 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-DL-NEXT: global_store_short v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm + <8 x i4> addrspace(1)* %src2, + i16 addrspace(1)* nocapture %dst) { +entry: + %vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %src1 + %vec2 = load <8 x i4>, <8 x i4> addrspace(1)* %src2 + + %cvec1 = sext <8 x i4> %vec1 to <8 x i16> + %cvec2 = sext <8 x i4> %vec2 to <8 x i16> + + %mul = mul <8 x i16> %cvec1, %cvec2 + %mul0 = extractelement <8 x i16> %mul, i64 0 + %mul1 = extractelement <8 x i16> %mul, i64 1 + %mul2 = extractelement <8 x i16> %mul, i64 2 + %mul3 = extractelement <8 x i16> %mul, i64 3 + %mul4 = extractelement <8 x i16> %mul, i64 4 + %mul5 = extractelement <8 x i16> %mul, i64 5 + %mul6 = extractelement <8 x i16> %mul, i64 6 + %mul7 = extractelement <8 x i16> %mul, i64 7 + + %acc = load i16, i16 addrspace(1)* %dst, align 4 + %add1 = add i16 %mul0, %acc + %add2 = add i16 %add1, %mul1 + %add3 = add i16 %add2, %mul2 + %add4 = add i16 %add3, %mul3 + %add5 = add i16 %add4, %mul4 + %add6 = add i16 %add5, %mul5 + %add7 = add i16 %add6, %mul6 + %add8 = add i16 %add7, %mul7 + + store i16 %add8, i16 addrspace(1)* %dst, align 4 + ret void +} + +; TODO: Support this pattern. +define amdgpu_kernel void @idot8_acc8_vecMul(<8 x i4> addrspace(1)* %src1, +; GFX7-LABEL: idot8_acc8_vecMul: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s7, 0xf000 +; GFX7-NEXT: s_mov_b32 s6, -1 +; GFX7-NEXT: s_movk_i32 s0, 0xff +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_load_dword s2, s[8:9], 0x0 +; GFX7-NEXT: buffer_load_ubyte v0, off, s[4:7], 0 +; GFX7-NEXT: s_load_dword s8, s[10:11], 0x0 +; GFX7-NEXT: s_mov_b32 s1, 0xffff +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_bfe_i32 s9, s2, 0x40000 +; GFX7-NEXT: s_bfe_i32 s10, s2, 0x40004 +; GFX7-NEXT: s_bfe_i32 s16, s8, 0x40000 +; GFX7-NEXT: s_bfe_i32 s17, s8, 0x40004 +; GFX7-NEXT: s_bfe_i32 s18, s8, 0x40008 +; GFX7-NEXT: s_bfe_i32 s19, s8, 0x4000c +; GFX7-NEXT: s_bfe_i32 s20, s8, 0x40010 +; GFX7-NEXT: s_bfe_i32 s21, s8, 0x40014 +; GFX7-NEXT: s_bfe_i32 s22, s8, 0x40018 +; GFX7-NEXT: s_ashr_i32 s8, s8, 28 +; GFX7-NEXT: v_mov_b32_e32 v7, s17 +; GFX7-NEXT: v_mov_b32_e32 v8, s16 +; GFX7-NEXT: s_bfe_i32 s11, s2, 0x40008 +; GFX7-NEXT: v_mov_b32_e32 v6, s18 +; GFX7-NEXT: s_bfe_i32 s12, s2, 0x4000c +; GFX7-NEXT: v_mov_b32_e32 v5, s19 +; GFX7-NEXT: s_bfe_i32 s13, s2, 0x40010 +; GFX7-NEXT: v_mov_b32_e32 v4, s20 +; GFX7-NEXT: s_bfe_i32 s14, s2, 0x40014 +; GFX7-NEXT: v_mov_b32_e32 v3, s21 +; GFX7-NEXT: s_bfe_i32 s15, s2, 0x40018 +; GFX7-NEXT: v_mov_b32_e32 v2, s22 +; GFX7-NEXT: s_ashr_i32 s2, s2, 28 +; GFX7-NEXT: v_mov_b32_e32 v1, s8 +; GFX7-NEXT: v_mul_i32_i24_e32 v1, s2, v1 +; GFX7-NEXT: v_mul_i32_i24_e32 v2, s15, v2 +; GFX7-NEXT: v_mul_i32_i24_e32 v3, s14, v3 +; GFX7-NEXT: v_mul_i32_i24_e32 v4, s13, v4 +; GFX7-NEXT: v_mul_i32_i24_e32 v5, s12, v5 +; GFX7-NEXT: v_mul_i32_i24_e32 v6, s11, v6 +; GFX7-NEXT: v_mul_i32_i24_e32 v7, s10, v7 +; GFX7-NEXT: v_mul_i32_i24_e32 v8, s9, v8 +; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v1 +; GFX7-NEXT: v_and_b32_e32 v2, s0, v2 +; GFX7-NEXT: v_lshlrev_b32_e32 v3, 8, v3 +; GFX7-NEXT: v_and_b32_e32 v4, s0, v4 +; GFX7-NEXT: v_lshlrev_b32_e32 v5, 8, v5 +; GFX7-NEXT: v_and_b32_e32 v6, s0, v6 +; GFX7-NEXT: v_lshlrev_b32_e32 v7, 8, v7 +; GFX7-NEXT: v_and_b32_e32 v8, s0, v8 +; GFX7-NEXT: v_or_b32_e32 v1, v2, v1 +; GFX7-NEXT: v_or_b32_e32 v2, v4, v3 +; GFX7-NEXT: v_or_b32_e32 v3, v6, v5 +; GFX7-NEXT: v_or_b32_e32 v4, v8, v7 +; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX7-NEXT: v_and_b32_e32 v2, s1, v2 +; GFX7-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GFX7-NEXT: v_and_b32_e32 v4, s1, v4 +; GFX7-NEXT: v_or_b32_e32 v1, v2, v1 +; GFX7-NEXT: v_or_b32_e32 v2, v4, v3 +; GFX7-NEXT: v_alignbit_b32 v3, v1, v2, 8 +; GFX7-NEXT: v_alignbit_b32 v4, v1, v2, 16 +; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v2 +; GFX7-NEXT: v_lshrrev_b32_e32 v6, 8, v1 +; GFX7-NEXT: v_lshrrev_b32_e32 v7, 16, v1 +; GFX7-NEXT: v_lshrrev_b32_e32 v8, 24, v1 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v3, v0 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v4, v0 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v5, v0 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v6, v0 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v7, v0 +; GFX7-NEXT: v_add_i32_e32 v0, vcc, v8, v0 +; GFX7-NEXT: buffer_store_byte v0, off, s[4:7], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: idot8_acc8_vecMul: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX8-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_load_ubyte v2, v[0:1] +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_lshr_b32 s0, s2, 4 +; GFX8-NEXT: s_lshr_b32 s1, s2, 12 +; GFX8-NEXT: s_lshr_b32 s5, s2, 8 +; GFX8-NEXT: s_lshr_b32 s6, s4, 4 +; GFX8-NEXT: s_lshr_b32 s7, s4, 12 +; GFX8-NEXT: s_lshr_b32 s8, s4, 8 +; GFX8-NEXT: v_lshlrev_b16_e64 v3, 12, s5 +; GFX8-NEXT: v_lshlrev_b16_e64 v4, 12, s1 +; GFX8-NEXT: v_lshlrev_b16_e64 v5, 12, s0 +; GFX8-NEXT: v_lshlrev_b16_e64 v7, 12, s8 +; GFX8-NEXT: v_lshlrev_b16_e64 v8, 12, s7 +; GFX8-NEXT: v_lshlrev_b16_e64 v9, 12, s6 +; GFX8-NEXT: v_lshlrev_b16_e64 v6, 12, s2 +; GFX8-NEXT: v_lshlrev_b16_e64 v10, 12, s4 +; GFX8-NEXT: v_ashrrev_i16_e32 v3, 12, v3 +; GFX8-NEXT: v_ashrrev_i16_e32 v7, 12, v7 +; GFX8-NEXT: v_ashrrev_i16_e32 v4, 12, v4 +; GFX8-NEXT: v_ashrrev_i16_e32 v8, 12, v8 +; GFX8-NEXT: v_ashrrev_i16_e32 v5, 12, v5 +; GFX8-NEXT: v_ashrrev_i16_e32 v9, 12, v9 +; GFX8-NEXT: v_ashrrev_i16_e32 v6, 12, v6 +; GFX8-NEXT: v_ashrrev_i16_e32 v10, 12, v10 +; GFX8-NEXT: v_mul_u32_u24_sdwa v3, v3, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX8-NEXT: v_mul_u32_u24_sdwa v4, v4, v8 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX8-NEXT: v_mul_u32_u24_sdwa v5, v5, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX8-NEXT: v_mul_u32_u24_sdwa v6, v6, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX8-NEXT: s_lshr_b32 s0, s2, 20 +; GFX8-NEXT: s_lshr_b32 s1, s2, 16 +; GFX8-NEXT: s_lshr_b32 s5, s2, 28 +; GFX8-NEXT: s_lshr_b32 s2, s2, 24 +; GFX8-NEXT: s_lshr_b32 s6, s4, 20 +; GFX8-NEXT: s_lshr_b32 s7, s4, 16 +; GFX8-NEXT: s_lshr_b32 s8, s4, 28 +; GFX8-NEXT: s_lshr_b32 s4, s4, 24 +; GFX8-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_lshlrev_b16_e64 v7, 12, s2 +; GFX8-NEXT: v_lshlrev_b16_e64 v8, 12, s5 +; GFX8-NEXT: v_lshlrev_b16_e64 v9, 12, s1 +; GFX8-NEXT: v_lshlrev_b16_e64 v10, 12, s0 +; GFX8-NEXT: v_lshlrev_b16_e64 v11, 12, s4 +; GFX8-NEXT: v_lshlrev_b16_e64 v12, 12, s8 +; GFX8-NEXT: v_lshlrev_b16_e64 v13, 12, s7 +; GFX8-NEXT: v_lshlrev_b16_e64 v14, 12, s6 +; GFX8-NEXT: v_ashrrev_i16_e32 v7, 12, v7 +; GFX8-NEXT: v_ashrrev_i16_e32 v11, 12, v11 +; GFX8-NEXT: v_ashrrev_i16_e32 v8, 12, v8 +; GFX8-NEXT: v_ashrrev_i16_e32 v12, 12, v12 +; GFX8-NEXT: v_ashrrev_i16_e32 v9, 12, v9 +; GFX8-NEXT: v_ashrrev_i16_e32 v13, 12, v13 +; GFX8-NEXT: v_ashrrev_i16_e32 v10, 12, v10 +; GFX8-NEXT: v_ashrrev_i16_e32 v14, 12, v14 +; GFX8-NEXT: v_lshrrev_b32_e32 v5, 8, v3 +; GFX8-NEXT: v_mul_u32_u24_sdwa v7, v7, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX8-NEXT: v_mul_u32_u24_sdwa v8, v8, v12 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX8-NEXT: v_mul_u32_u24_sdwa v9, v9, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX8-NEXT: v_mul_u32_u24_sdwa v10, v10, v14 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0 +; GFX8-NEXT: v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX8-NEXT: v_or_b32_sdwa v4, v9, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX8-NEXT: v_lshrrev_b32_e32 v6, 8, v4 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3 +; GFX8-NEXT: v_add_u32_e32 v2, vcc, v5, v2 +; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_2 +; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 +; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4 +; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v6 +; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX8-NEXT: v_add_u32_sdwa v2, vcc, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 +; GFX8-NEXT: flat_store_byte v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: idot8_acc8_vecMul: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_load_ubyte v2, v[0:1], off +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_lshr_b32 s0, s2, 4 +; GFX9-NEXT: s_lshr_b32 s1, s2, 12 +; GFX9-NEXT: s_lshr_b32 s5, s2, 8 +; GFX9-NEXT: s_lshr_b32 s6, s4, 4 +; GFX9-NEXT: s_lshr_b32 s7, s4, 12 +; GFX9-NEXT: s_lshr_b32 s8, s4, 8 +; GFX9-NEXT: v_lshlrev_b16_e64 v3, 12, s5 +; GFX9-NEXT: v_lshlrev_b16_e64 v4, 12, s1 +; GFX9-NEXT: v_lshlrev_b16_e64 v5, 12, s0 +; GFX9-NEXT: v_lshlrev_b16_e64 v7, 12, s8 +; GFX9-NEXT: v_lshlrev_b16_e64 v8, 12, s7 +; GFX9-NEXT: v_lshlrev_b16_e64 v9, 12, s6 +; GFX9-NEXT: v_lshlrev_b16_e64 v6, 12, s2 +; GFX9-NEXT: v_lshlrev_b16_e64 v10, 12, s4 +; GFX9-NEXT: v_ashrrev_i16_e32 v3, 12, v3 +; GFX9-NEXT: v_ashrrev_i16_e32 v7, 12, v7 +; GFX9-NEXT: v_ashrrev_i16_e32 v4, 12, v4 +; GFX9-NEXT: v_ashrrev_i16_e32 v8, 12, v8 +; GFX9-NEXT: v_ashrrev_i16_e32 v5, 12, v5 +; GFX9-NEXT: v_ashrrev_i16_e32 v9, 12, v9 +; GFX9-NEXT: v_ashrrev_i16_e32 v6, 12, v6 +; GFX9-NEXT: v_ashrrev_i16_e32 v10, 12, v10 +; GFX9-NEXT: v_mul_lo_u16_e32 v6, v6, v10 +; GFX9-NEXT: v_mul_lo_u16_sdwa v5, v5, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9-NEXT: v_mul_lo_u16_sdwa v4, v4, v8 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9-NEXT: v_mul_lo_u16_e32 v3, v3, v7 +; GFX9-NEXT: s_lshr_b32 s0, s2, 20 +; GFX9-NEXT: s_lshr_b32 s1, s2, 16 +; GFX9-NEXT: s_lshr_b32 s5, s2, 28 +; GFX9-NEXT: s_lshr_b32 s2, s2, 24 +; GFX9-NEXT: s_lshr_b32 s6, s4, 20 +; GFX9-NEXT: s_lshr_b32 s7, s4, 16 +; GFX9-NEXT: s_lshr_b32 s8, s4, 28 +; GFX9-NEXT: s_lshr_b32 s4, s4, 24 +; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: v_lshlrev_b16_e64 v9, 12, s2 +; GFX9-NEXT: v_lshlrev_b16_e64 v10, 12, s5 +; GFX9-NEXT: v_lshlrev_b16_e64 v11, 12, s1 +; GFX9-NEXT: v_lshlrev_b16_e64 v12, 12, s0 +; GFX9-NEXT: v_lshlrev_b16_e64 v13, 12, s4 +; GFX9-NEXT: v_lshlrev_b16_e64 v14, 12, s8 +; GFX9-NEXT: v_lshlrev_b16_e64 v15, 12, s7 +; GFX9-NEXT: v_lshlrev_b16_e64 v16, 12, s6 +; GFX9-NEXT: v_ashrrev_i16_e32 v9, 12, v9 +; GFX9-NEXT: v_ashrrev_i16_e32 v13, 12, v13 +; GFX9-NEXT: v_ashrrev_i16_e32 v10, 12, v10 +; GFX9-NEXT: v_ashrrev_i16_e32 v14, 12, v14 +; GFX9-NEXT: v_ashrrev_i16_e32 v11, 12, v11 +; GFX9-NEXT: v_ashrrev_i16_e32 v15, 12, v15 +; GFX9-NEXT: v_ashrrev_i16_e32 v12, 12, v12 +; GFX9-NEXT: v_ashrrev_i16_e32 v16, 12, v16 +; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v3 +; GFX9-NEXT: v_mul_lo_u16_sdwa v12, v12, v16 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9-NEXT: v_mul_lo_u16_e32 v11, v11, v15 +; GFX9-NEXT: v_mul_lo_u16_sdwa v10, v10, v14 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9-NEXT: v_mul_lo_u16_e32 v9, v9, v13 +; GFX9-NEXT: v_or_b32_sdwa v7, v11, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v8, v9, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-NEXT: v_or_b32_sdwa v4, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 +; GFX9-NEXT: v_add_u32_e32 v2, v2, v5 +; GFX9-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_2 +; GFX9-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 +; GFX9-NEXT: v_add_u32_e32 v2, v2, v4 +; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v4 +; GFX9-NEXT: v_add_u32_e32 v2, v2, v3 +; GFX9-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 +; GFX9-NEXT: global_store_byte v[0:1], v2, off +; GFX9-NEXT: s_endpgm +; +; GFX9-DL-LABEL: idot8_acc8_vecMul: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_load_dword s2, s[4:5], 0x0 +; GFX9-DL-NEXT: s_load_dword s4, s[6:7], 0x0 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-DL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-DL-NEXT: global_load_ubyte v2, v[0:1], off +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: s_lshr_b32 s0, s2, 4 +; GFX9-DL-NEXT: s_lshr_b32 s1, s2, 12 +; GFX9-DL-NEXT: s_lshr_b32 s5, s2, 8 +; GFX9-DL-NEXT: s_lshr_b32 s6, s4, 4 +; GFX9-DL-NEXT: s_lshr_b32 s7, s4, 12 +; GFX9-DL-NEXT: s_lshr_b32 s8, s4, 8 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v3, 12, s5 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v4, 12, s1 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v5, 12, s0 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v7, 12, s8 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v8, 12, s7 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v9, 12, s6 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v6, 12, s2 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v10, 12, s4 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v3, 12, v3 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v7, 12, v7 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v4, 12, v4 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v8, 12, v8 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v5, 12, v5 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v9, 12, v9 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v6, 12, v6 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v10, 12, v10 +; GFX9-DL-NEXT: v_mul_lo_u16_e32 v6, v6, v10 +; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v5, v5, v9 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v4, v4, v8 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9-DL-NEXT: v_mul_lo_u16_e32 v3, v3, v7 +; GFX9-DL-NEXT: s_lshr_b32 s0, s2, 20 +; GFX9-DL-NEXT: s_lshr_b32 s1, s2, 16 +; GFX9-DL-NEXT: s_lshr_b32 s5, s2, 28 +; GFX9-DL-NEXT: s_lshr_b32 s2, s2, 24 +; GFX9-DL-NEXT: s_lshr_b32 s6, s4, 20 +; GFX9-DL-NEXT: s_lshr_b32 s7, s4, 16 +; GFX9-DL-NEXT: s_lshr_b32 s8, s4, 28 +; GFX9-DL-NEXT: s_lshr_b32 s4, s4, 24 +; GFX9-DL-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-DL-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-DL-NEXT: v_or_b32_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v9, 12, s2 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v10, 12, s5 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v11, 12, s1 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v12, 12, s0 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v13, 12, s4 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v14, 12, s8 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v15, 12, s7 +; GFX9-DL-NEXT: v_lshlrev_b16_e64 v16, 12, s6 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v9, 12, v9 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v13, 12, v13 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v10, 12, v10 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v14, 12, v14 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v11, 12, v11 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v15, 12, v15 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v12, 12, v12 +; GFX9-DL-NEXT: v_ashrrev_i16_e32 v16, 12, v16 +; GFX9-DL-NEXT: v_lshrrev_b32_e32 v5, 8, v3 +; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v12, v12, v16 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9-DL-NEXT: v_mul_lo_u16_e32 v11, v11, v15 +; GFX9-DL-NEXT: v_mul_lo_u16_sdwa v10, v10, v14 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD +; GFX9-DL-NEXT: v_mul_lo_u16_e32 v9, v9, v13 +; GFX9-DL-NEXT: v_or_b32_sdwa v7, v11, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-DL-NEXT: v_or_b32_sdwa v8, v9, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD +; GFX9-DL-NEXT: v_or_b32_sdwa v4, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_add_u32_e32 v2, v3, v2 +; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v5 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_2 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 +; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v4 +; GFX9-DL-NEXT: v_lshrrev_b32_e32 v3, 8, v4 +; GFX9-DL-NEXT: v_add_u32_e32 v2, v2, v3 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 +; GFX9-DL-NEXT: v_add_u32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3 +; GFX9-DL-NEXT: global_store_byte v[0:1], v2, off +; GFX9-DL-NEXT: s_endpgm + <8 x i4> addrspace(1)* %src2, + i8 addrspace(1)* nocapture %dst) { +entry: + %vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %src1 + %vec2 = load <8 x i4>, <8 x i4> addrspace(1)* %src2 + + %cvec1 = sext <8 x i4> %vec1 to <8 x i8> + %cvec2 = sext <8 x i4> %vec2 to <8 x i8> + + %mul = mul <8 x i8> %cvec1, %cvec2 + %mul0 = extractelement <8 x i8> %mul, i64 0 + %mul1 = extractelement <8 x i8> %mul, i64 1 + %mul2 = extractelement <8 x i8> %mul, i64 2 + %mul3 = extractelement <8 x i8> %mul, i64 3 + %mul4 = extractelement <8 x i8> %mul, i64 4 + %mul5 = extractelement <8 x i8> %mul, i64 5 + %mul6 = extractelement <8 x i8> %mul, i64 6 + %mul7 = extractelement <8 x i8> %mul, i64 7 + + %acc = load i8, i8 addrspace(1)* %dst, align 4 + %add1 = add i8 %mul0, %acc + %add2 = add i8 %add1, %mul1 + %add3 = add i8 %add2, %mul2 + %add4 = add i8 %add3, %mul3 + %add5 = add i8 %add4, %mul4 + %add6 = add i8 %add5, %mul5 + %add7 = add i8 %add6, %mul6 + %add8 = add i8 %add7, %mul7 + + store i8 %add8, i8 addrspace(1)* %dst, align 4 + ret void +}