Index: include/llvm/ADT/Triple.h =================================================================== --- include/llvm/ADT/Triple.h +++ include/llvm/ADT/Triple.h @@ -101,6 +101,7 @@ enum SubArchType { NoSubArch, + ARMSubArch_v8_5a, ARMSubArch_v8_4a, ARMSubArch_v8_3a, ARMSubArch_v8_2a, Index: include/llvm/Support/AArch64TargetParser.def =================================================================== --- include/llvm/Support/AArch64TargetParser.def +++ include/llvm/Support/AArch64TargetParser.def @@ -40,6 +40,11 @@ (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD)) +AARCH64_ARCH("armv8.5-a", ARMV8_5A, "8.5-A", "v8.5a", + ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, + (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP | + AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | + AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD)) #undef AARCH64_ARCH #ifndef AARCH64_ARCH_EXT_NAME Index: include/llvm/Support/ARMTargetParser.def =================================================================== --- include/llvm/Support/ARMTargetParser.def +++ include/llvm/Support/ARMTargetParser.def @@ -106,6 +106,11 @@ (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | ARM::AEK_DOTPROD)) +ARM_ARCH("armv8.5-a", ARMV8_5A, "8.5-A", "v8.5a", + ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, + (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | + ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | + ARM::AEK_DOTPROD)) ARM_ARCH("armv8-r", ARMV8R, "8-R", "v8r", ARMBuildAttrs::CPUArch::v8_R, FK_NEON_FP_ARMV8, (ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | Index: lib/Support/TargetParser.cpp =================================================================== --- lib/Support/TargetParser.cpp +++ lib/Support/TargetParser.cpp @@ -502,6 +502,8 @@ Features.push_back("+v8.3a"); if (AK == AArch64::ArchKind::ARMV8_4A) Features.push_back("+v8.4a"); + if (AK == AArch64::ArchKind::ARMV8_5A) + Features.push_back("+v8.5a"); return AK != AArch64::ArchKind::INVALID; } @@ -608,6 +610,7 @@ .Case("v8.2a", "v8.2-a") .Case("v8.3a", "v8.3-a") .Case("v8.4a", "v8.4-a") + .Case("v8.5a", "v8.5-a") .Case("v8r", "v8-r") .Case("v8m.base", "v8-m.base") .Case("v8m.main", "v8-m.main") @@ -776,6 +779,7 @@ case ARM::ArchKind::ARMV8_2A: case ARM::ArchKind::ARMV8_3A: case ARM::ArchKind::ARMV8_4A: + case ARM::ArchKind::ARMV8_5A: return ARM::ProfileKind::A; case ARM::ArchKind::ARMV2: case ARM::ArchKind::ARMV2A: @@ -839,6 +843,7 @@ case ARM::ArchKind::ARMV8_2A: case ARM::ArchKind::ARMV8_3A: case ARM::ArchKind::ARMV8_4A: + case ARM::ArchKind::ARMV8_5A: case ARM::ArchKind::ARMV8R: case ARM::ArchKind::ARMV8MBaseline: case ARM::ArchKind::ARMV8MMainline: Index: lib/Support/Triple.cpp =================================================================== --- lib/Support/Triple.cpp +++ lib/Support/Triple.cpp @@ -596,6 +596,8 @@ return Triple::ARMSubArch_v8_3a; case ARM::ArchKind::ARMV8_4A: return Triple::ARMSubArch_v8_4a; + case ARM::ArchKind::ARMV8_5A: + return Triple::ARMSubArch_v8_5a; case ARM::ArchKind::ARMV8R: return Triple::ARMSubArch_v8r; case ARM::ArchKind::ARMV8MBaseline: Index: lib/Target/AArch64/AArch64.td =================================================================== --- lib/Target/AArch64/AArch64.td +++ lib/Target/AArch64/AArch64.td @@ -220,6 +220,9 @@ def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd]>; +def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true", + "Support ARM v8.5a instructions", [HasV8_4aOps]>; + //===----------------------------------------------------------------------===// // Register File Description //===----------------------------------------------------------------------===// Index: lib/Target/AArch64/AArch64InstrInfo.td =================================================================== --- lib/Target/AArch64/AArch64InstrInfo.td +++ lib/Target/AArch64/AArch64InstrInfo.td @@ -22,6 +22,8 @@ AssemblerPredicate<"HasV8_3aOps", "armv8.3a">; def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">, AssemblerPredicate<"HasV8_4aOps", "armv8.4a">; +def HasV8_5a : Predicate<"Subtarget->hasV8_5aOps()">, + AssemblerPredicate<"HasV8_5aOps", "armv8.5a">; def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">; def HasNEON : Predicate<"Subtarget->hasNEON()">, Index: lib/Target/AArch64/AArch64Subtarget.h =================================================================== --- lib/Target/AArch64/AArch64Subtarget.h +++ lib/Target/AArch64/AArch64Subtarget.h @@ -67,6 +67,7 @@ bool HasV8_2aOps = false; bool HasV8_3aOps = false; bool HasV8_4aOps = false; + bool HasV8_5aOps = false; bool HasFPARMv8 = false; bool HasNEON = false; @@ -213,6 +214,7 @@ bool hasV8_2aOps() const { return HasV8_2aOps; } bool hasV8_3aOps() const { return HasV8_3aOps; } bool hasV8_4aOps() const { return HasV8_4aOps; } + bool hasV8_5aOps() const { return HasV8_5aOps; } bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; } Index: lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp =================================================================== --- lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -4945,6 +4945,7 @@ RequestedExtensions.push_back("aes"); break; case AArch64::ArchKind::ARMV8_4A: + case AArch64::ArchKind::ARMV8_5A: RequestedExtensions.push_back("sm4"); RequestedExtensions.push_back("sha3"); RequestedExtensions.push_back("sha2"); @@ -4963,6 +4964,7 @@ RequestedExtensions.push_back("noaes"); break; case AArch64::ArchKind::ARMV8_4A: + case AArch64::ArchKind::ARMV8_5A: RequestedExtensions.push_back("nosm4"); RequestedExtensions.push_back("nosha3"); RequestedExtensions.push_back("nosha2"); Index: lib/Target/ARM/ARM.td =================================================================== --- lib/Target/ARM/ARM.td +++ lib/Target/ARM/ARM.td @@ -452,6 +452,10 @@ "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd]>; +def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true", + "Support Armv8.5-A instructions", + [HasV8_4aOps]>; + //===----------------------------------------------------------------------===// // ARM Processor subtarget features. // @@ -686,6 +690,20 @@ FeatureRAS, FeatureDotProd]>; +def ARMv85a : Architecture<"armv8.5-a", "ARMv85a", [HasV8_5aOps, + FeatureAClass, + FeatureDB, + FeatureFPARMv8, + FeatureNEON, + FeatureDSP, + FeatureTrustZone, + FeatureMP, + FeatureVirtualization, + FeatureCrypto, + FeatureCRC, + FeatureRAS, + FeatureDotProd]>; + def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, FeatureRClass, FeatureDB, Index: lib/Target/ARM/ARMInstrInfo.td =================================================================== --- lib/Target/ARM/ARMInstrInfo.td +++ lib/Target/ARM/ARMInstrInfo.td @@ -255,6 +255,8 @@ AssemblerPredicate<"HasV8_3aOps", "armv8.3a">; def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">, AssemblerPredicate<"HasV8_4aOps", "armv8.4a">; +def HasV8_5a : Predicate<"Subtarget->hasV8_5aOps()">, + AssemblerPredicate<"HasV8_5aOps", "armv8.5a">; def NoVFP : Predicate<"!Subtarget->hasVFP2()">; def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate<"FeatureVFP2", "VFP2">; Index: lib/Target/ARM/ARMSubtarget.h =================================================================== --- lib/Target/ARM/ARMSubtarget.h +++ lib/Target/ARM/ARMSubtarget.h @@ -106,6 +106,7 @@ ARMv82a, ARMv83a, ARMv84a, + ARMv85a, ARMv8a, ARMv8mBaseline, ARMv8mMainline, @@ -153,6 +154,7 @@ bool HasV8_2aOps = false; bool HasV8_3aOps = false; bool HasV8_4aOps = false; + bool HasV8_5aOps = false; bool HasV8MBaselineOps = false; bool HasV8MMainlineOps = false; @@ -538,6 +540,7 @@ bool hasV8_2aOps() const { return HasV8_2aOps; } bool hasV8_3aOps() const { return HasV8_3aOps; } bool hasV8_4aOps() const { return HasV8_4aOps; } + bool hasV8_5aOps() const { return HasV8_5aOps; } bool hasV8MBaselineOps() const { return HasV8MBaselineOps; } bool hasV8MMainlineOps() const { return HasV8MMainlineOps; } Index: lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp +++ lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp @@ -861,6 +861,7 @@ case ARM::ArchKind::ARMV8_2A: case ARM::ArchKind::ARMV8_3A: case ARM::ArchKind::ARMV8_4A: + case ARM::ArchKind::ARMV8_5A: setAttributeItem(CPU_arch_profile, ApplicationProfile, false); setAttributeItem(ARM_ISA_use, Allowed, false); setAttributeItem(THUMB_ISA_use, AllowThumb32, false); Index: unittests/Support/TargetParserTest.cpp =================================================================== --- unittests/Support/TargetParserTest.cpp +++ unittests/Support/TargetParserTest.cpp @@ -17,18 +17,19 @@ namespace { const char *ARMArch[] = { - "armv2", "armv2a", "armv3", "armv3m", "armv4", - "armv4t", "armv5", "armv5t", "armv5e", "armv5te", - "armv5tej", "armv6", "armv6j", "armv6k", "armv6hl", - "armv6t2", "armv6kz", "armv6z", "armv6zk", "armv6-m", - "armv6m", "armv6sm", "armv6s-m", "armv7-a", "armv7", - "armv7a", "armv7ve", "armv7hl", "armv7l", "armv7-r", - "armv7r", "armv7-m", "armv7m", "armv7k", "armv7s", - "armv7e-m", "armv7em", "armv8-a", "armv8", "armv8a", - "armv8l", "armv8.1-a", "armv8.1a", "armv8.2-a", "armv8.2a", - "armv8.3-a", "armv8.3a", "armv8-r", "armv8r", "armv8-m.base", - "armv8m.base", "armv8-m.main", "armv8m.main", "iwmmxt", "iwmmxt2", - "xscale"}; + "armv2", "armv2a", "armv3", "armv3m", "armv4", + "armv4t", "armv5", "armv5t", "armv5e", "armv5te", + "armv5tej", "armv6", "armv6j", "armv6k", "armv6hl", + "armv6t2", "armv6kz", "armv6z", "armv6zk", "armv6-m", + "armv6m", "armv6sm", "armv6s-m", "armv7-a", "armv7", + "armv7a", "armv7ve", "armv7hl", "armv7l", "armv7-r", + "armv7r", "armv7-m", "armv7m", "armv7k", "armv7s", + "armv7e-m", "armv7em", "armv8-a", "armv8", "armv8a", + "armv8l", "armv8.1-a", "armv8.1a", "armv8.2-a", "armv8.2a", + "armv8.3-a", "armv8.3a", "armv8.5-a", "armv8.5a", "armv8-r", + "armv8r", "armv8-m.base", "armv8m.base", "armv8-m.main", "armv8m.main", + "iwmmxt", "iwmmxt2", "xscale" +}; bool testARMCPU(StringRef CPUName, StringRef ExpectedArch, StringRef ExpectedFPU, unsigned ExpectedFlags, @@ -384,6 +385,9 @@ testARMArch("armv8.3-a", "generic", "v8.3a", ARMBuildAttrs::CPUArch::v8_A)); EXPECT_TRUE( + testARMArch("armv8.5-a", "generic", "v8.5a", + ARMBuildAttrs::CPUArch::v8_A)); + EXPECT_TRUE( testARMArch("armv8-r", "cortex-r52", "v8r", ARMBuildAttrs::CPUArch::v8_R)); EXPECT_TRUE( @@ -601,7 +605,9 @@ "v6kz", "v6z", "v6zk", "v6-m", "v6m", "v6sm", "v6s-m", "v7-a", "v7", "v7a", "v7ve", "v7hl", "v7l", "v7-r", "v7r", "v7-m", "v7m", "v7k", "v7s", "v7e-m", "v7em", "v8-a", "v8", "v8a", - "v8l", "v8.1-a", "v8.1a", "v8.2-a", "v8.2a", "v8.3-a", "v8.3a", "v8-r"}; + "v8l", "v8.1-a", "v8.1a", "v8.2-a", "v8.2a", "v8.3-a", "v8.3a", "v8.5-a", + "v8.5a", "v8-r" + }; for (unsigned i = 0; i < array_lengthof(Arch); i++) { std::string arm_1 = "armeb" + (std::string)(Arch[i]); @@ -659,6 +665,7 @@ case ARM::ArchKind::ARMV8_1A: case ARM::ArchKind::ARMV8_2A: case ARM::ArchKind::ARMV8_3A: + case ARM::ArchKind::ARMV8_5A: EXPECT_EQ(ARM::ProfileKind::A, ARM::parseArchProfile(ARMArch[i])); break; default: @@ -820,6 +827,8 @@ ARMBuildAttrs::CPUArch::v8_A)); EXPECT_TRUE(testAArch64Arch("armv8.3-a", "generic", "v8.3a", ARMBuildAttrs::CPUArch::v8_A)); + EXPECT_TRUE(testAArch64Arch("armv8.5-a", "generic", "v8.5a", + ARMBuildAttrs::CPUArch::v8_A)); } bool testAArch64Extension(StringRef CPUName, AArch64::ArchKind AK,