Index: lib/Target/PowerPC/PPCReduceCRLogicals.cpp =================================================================== --- lib/Target/PowerPC/PPCReduceCRLogicals.cpp +++ lib/Target/PowerPC/PPCReduceCRLogicals.cpp @@ -381,10 +381,10 @@ const MachineBranchProbabilityInfo *MBPI; // A vector to contain all the CR logical operations - std::vector AllCRLogicalOps; + SmallVector AllCRLogicalOps; void initialize(MachineFunction &MFParm); void collectCRLogicals(); - bool handleCROp(CRLogicalOpInfo &CRI); + bool handleCROp(unsigned Idx); bool splitBlockOnBinaryCROp(CRLogicalOpInfo &CRI); static bool isCRLogical(MachineInstr &MI) { unsigned Opc = MI.getOpcode(); @@ -398,7 +398,7 @@ // Not using a range-based for loop here as the vector may grow while being // operated on. for (unsigned i = 0; i < AllCRLogicalOps.size(); i++) - Changed |= handleCROp(AllCRLogicalOps[i]); + Changed |= handleCROp(i); return Changed; } @@ -578,10 +578,11 @@ /// a unary CR logical might be used to change the condition code on a /// comparison feeding it. A nullary CR logical might simply be removable /// if the user of the bit it [un]sets can be transformed. -bool PPCReduceCRLogicals::handleCROp(CRLogicalOpInfo &CRI) { +bool PPCReduceCRLogicals::handleCROp(unsigned Idx) { // We can definitely split a block on the inputs to a binary CR operation // whose defs and (single) use are within the same block. bool Changed = false; + CRLogicalOpInfo CRI = AllCRLogicalOps[Idx]; if (CRI.IsBinary && CRI.ContainedInBlock && CRI.SingleUse && CRI.FeedsBR && CRI.DefsSingleUse) { Changed = splitBlockOnBinaryCROp(CRI); Index: lib/Target/PowerPC/PPCTargetMachine.cpp =================================================================== --- lib/Target/PowerPC/PPCTargetMachine.cpp +++ lib/Target/PowerPC/PPCTargetMachine.cpp @@ -93,7 +93,7 @@ static cl::opt ReduceCRLogical("ppc-reduce-cr-logicals", cl::desc("Expand eligible cr-logical binary ops to branches"), - cl::init(false), cl::Hidden); + cl::init(true), cl::Hidden); extern "C" void LLVMInitializePowerPCTarget() { // Register the targets RegisterTargetMachine A(getThePPC32Target()); Index: test/CodeGen/PowerPC/2008-10-28-f128-i32.ll =================================================================== --- test/CodeGen/PowerPC/2008-10-28-f128-i32.ll +++ test/CodeGen/PowerPC/2008-10-28-f128-i32.ll @@ -36,7 +36,7 @@ ; CHECK-NEXT: # %bb.1: # %bb5 ; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: li 4, 0 -; CHECK-NEXT: b .LBB0_16 +; CHECK-NEXT: b .LBB0_17 ; CHECK-NEXT: .LBB0_2: # %bb1 ; CHECK-NEXT: lfd 0, 400(1) ; CHECK-NEXT: lis 3, 15856 @@ -166,13 +166,11 @@ ; CHECK-NEXT: bl __gcc_qsub@PLT ; CHECK-NEXT: stfd 2, 176(1) ; CHECK-NEXT: stfd 1, 168(1) -; CHECK-NEXT: fcmpu 0, 2, 27 +; CHECK-NEXT: fcmpu 1, 2, 27 ; CHECK-NEXT: lwz 3, 180(1) -; CHECK-NEXT: fcmpu 1, 1, 27 -; CHECK-NEXT: crandc 20, 6, 0 -; CHECK-NEXT: cror 21, 5, 7 +; CHECK-NEXT: fcmpu 0, 1, 27 +; CHECK-NEXT: crandc 20, 2, 4 ; CHECK-NEXT: stw 3, 268(1) -; CHECK-NEXT: cror 20, 21, 20 ; CHECK-NEXT: lwz 3, 176(1) ; CHECK-NEXT: stw 3, 264(1) ; CHECK-NEXT: lwz 3, 172(1) @@ -181,8 +179,11 @@ ; CHECK-NEXT: lwz 3, 168(1) ; CHECK-NEXT: stw 3, 272(1) ; CHECK-NEXT: lfd 31, 272(1) -; CHECK-NEXT: bc 12, 20, .LBB0_13 -; CHECK-NEXT: # %bb.10: # %bb2 +; CHECK-NEXT: bc 12, 20, .LBB0_14 +; CHECK-NEXT: # %bb.10: # %bb1 +; CHECK-NEXT: cror 20, 1, 3 +; CHECK-NEXT: bc 12, 20, .LBB0_14 +; CHECK-NEXT: # %bb.11: # %bb2 ; CHECK-NEXT: fneg 28, 31 ; CHECK-NEXT: stfd 28, 48(1) ; CHECK-NEXT: lis 3, 16864 @@ -231,15 +232,15 @@ ; CHECK-NEXT: crandc 20, 6, 1 ; CHECK-NEXT: cror 20, 4, 20 ; CHECK-NEXT: addis 3, 3, -32768 -; CHECK-NEXT: bc 12, 20, .LBB0_12 -; CHECK-NEXT: # %bb.11: # %bb2 +; CHECK-NEXT: bc 12, 20, .LBB0_13 +; CHECK-NEXT: # %bb.12: # %bb2 ; CHECK-NEXT: ori 3, 4, 0 -; CHECK-NEXT: b .LBB0_12 -; CHECK-NEXT: .LBB0_12: # %bb2 +; CHECK-NEXT: b .LBB0_13 +; CHECK-NEXT: .LBB0_13: # %bb2 ; CHECK-NEXT: subfic 4, 3, 0 ; CHECK-NEXT: subfe 3, 29, 30 -; CHECK-NEXT: b .LBB0_16 -; CHECK-NEXT: .LBB0_13: # %bb3 +; CHECK-NEXT: b .LBB0_17 +; CHECK-NEXT: .LBB0_14: # %bb3 ; CHECK-NEXT: stfd 31, 112(1) ; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: stw 3, 148(1) @@ -286,13 +287,13 @@ ; CHECK-NEXT: crandc 20, 6, 0 ; CHECK-NEXT: cror 20, 5, 20 ; CHECK-NEXT: addis 3, 3, -32768 -; CHECK-NEXT: bc 12, 20, .LBB0_14 -; CHECK-NEXT: b .LBB0_15 -; CHECK-NEXT: .LBB0_14: # %bb3 -; CHECK-NEXT: addi 4, 3, 0 +; CHECK-NEXT: bc 12, 20, .LBB0_15 +; CHECK-NEXT: b .LBB0_16 ; CHECK-NEXT: .LBB0_15: # %bb3 +; CHECK-NEXT: addi 4, 3, 0 +; CHECK-NEXT: .LBB0_16: # %bb3 ; CHECK-NEXT: mr 3, 30 -; CHECK-NEXT: .LBB0_16: # %bb5 +; CHECK-NEXT: .LBB0_17: # %bb5 ; CHECK-NEXT: lfd 31, 456(1) # 8-byte Folded Reload ; CHECK-NEXT: lfd 30, 448(1) # 8-byte Folded Reload ; CHECK-NEXT: lfd 29, 440(1) # 8-byte Folded Reload Index: test/CodeGen/PowerPC/brcond.ll =================================================================== --- test/CodeGen/PowerPC/brcond.ll +++ test/CodeGen/PowerPC/brcond.ll @@ -1,5 +1,7 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \ +; RUN: -ppc-reduce-cr-logicals=false < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \ +; RUN: -ppc-reduce-cr-logicals=false < %s | FileCheck %s define signext i32 @testi32slt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { ; CHECK-LABEL: testi32slt Index: test/CodeGen/PowerPC/pr42492.ll =================================================================== --- test/CodeGen/PowerPC/pr42492.ll +++ test/CodeGen/PowerPC/pr42492.ll @@ -4,13 +4,27 @@ define void @f(i8*, i8*, i64*) { ; Check we don't assert and this is not a Hardware Loop ; CHECK-LABEL: f: -; CHECK: .LBB0_2: # -; CHECK-NEXT: cmplwi -; CHECK-NEXT: cmpd -; CHECK-NEXT: sldi -; CHECK-NEXT: cror -; CHECK-NEXT: addi -; CHECK-NEXT: bc +; CHECK: # %bb.0: +; CHECK-NEXT: cmpld 3, 4 +; CHECK-NEXT: beqlr 0 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: ld 6, 8(5) +; CHECK-NEXT: not 3, 3 +; CHECK-NEXT: add 3, 3, 4 +; CHECK-NEXT: li 4, 0 +; CHECK-NEXT: .p2align 5 +; CHECK-NEXT: .LBB0_2: # +; CHECK-NEXT: sldi 6, 6, 4 +; CHECK-NEXT: cmplwi 4, 14 +; CHECK-NEXT: addi 7, 4, 1 +; CHECK-NEXT: bc 12, 1, .LBB0_4 +; CHECK-NEXT: # %bb.3: # +; CHECK-NEXT: cmpd 3, 4 +; CHECK-NEXT: mr 4, 7 +; CHECK-NEXT: bc 4, 2, .LBB0_2 +; CHECK-NEXT: .LBB0_4: +; CHECK-NEXT: std 6, 8(5) +; CHECK-NEXT: blr %4 = icmp eq i8* %0, %1 br i1 %4, label %9, label %5 Index: test/CodeGen/PowerPC/tocSaveInPrologue.ll =================================================================== --- test/CodeGen/PowerPC/tocSaveInPrologue.ll +++ test/CodeGen/PowerPC/tocSaveInPrologue.ll @@ -16,16 +16,17 @@ ; CHECK-NEXT: std r0, 16(r1) ; CHECK-NEXT: stdu r1, -64(r1) ; CHECK-NEXT: mr r29, r5 -; CHECK-NEXT: cmpwi cr1, r4, 11 ; CHECK-NEXT: mr r30, r3 ; CHECK-NEXT: extsw r28, r4 ; CHECK-NEXT: std r2, 24(r1) ; CHECK-NEXT: cmpwi r29, 1 -; CHECK-NEXT: cror 4*cr5+lt, lt, 4*cr1+lt -; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_2 +; CHECK-NEXT: bc 12, lt, .LBB0_3 +; CHECK-NEXT: # %bb.1: # %entry +; CHECK-NEXT: cmpwi cr0, r4, 11 +; CHECK-NEXT: bc 12, lt, .LBB0_3 ; CHECK-NEXT: .p2align 5 -; CHECK-NEXT: .LBB0_1: # %for.body.us -; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB0_2: # %for.body.us +; CHECK-NEXT: # ; CHECK-NEXT: mtctr r30 ; CHECK-NEXT: mr r3, r28 ; CHECK-NEXT: mr r12, r30 @@ -33,8 +34,8 @@ ; CHECK-NEXT: ld 2, 24(r1) ; CHECK-NEXT: addi r29, r29, -1 ; CHECK-NEXT: cmplwi r29, 0 -; CHECK-NEXT: bne cr0, .LBB0_1 -; CHECK-NEXT: .LBB0_2: # %for.cond.cleanup +; CHECK-NEXT: bne cr0, .LBB0_2 +; CHECK-NEXT: .LBB0_3: # %for.cond.cleanup ; CHECK-NEXT: mtctr r30 ; CHECK-NEXT: mr r3, r28 ; CHECK-NEXT: mr r12, r30 Index: test/CodeGen/PowerPC/vec-min-max.ll =================================================================== --- test/CodeGen/PowerPC/vec-min-max.ll +++ test/CodeGen/PowerPC/vec-min-max.ll @@ -240,22 +240,23 @@ define i128 @invalidv1i128(<2 x i128> %v1, <2 x i128> %v2) { ; CHECK-LABEL: invalidv1i128: ; CHECK: # %bb.0: +; CHECK-NEXT: mfvsrd 3, 36 ; CHECK-NEXT: xxswapd 0, 36 -; CHECK-NEXT: mfvsrd 4, 36 -; CHECK-NEXT: mfvsrd 5, 34 +; CHECK-NEXT: mfvsrd 4, 34 +; CHECK-NEXT: xxswapd 1, 34 +; CHECK-NEXT: cmpld 4, 3 +; CHECK-NEXT: cmpd 1, 4, 3 ; CHECK-NEXT: mfvsrd 3, 0 -; CHECK-NEXT: xxswapd 0, 34 -; CHECK-NEXT: cmpld 5, 4 -; CHECK-NEXT: cmpd 1, 5, 4 ; CHECK-NEXT: crandc 20, 4, 2 -; CHECK-NEXT: mfvsrd 6, 0 -; CHECK-NEXT: cmpld 1, 6, 3 -; CHECK-NEXT: crand 21, 2, 4 -; CHECK-NEXT: cror 20, 21, 20 -; CHECK-NEXT: bc 12, 20, .LBB12_2 +; CHECK-NEXT: mfvsrd 4, 1 +; CHECK-NEXT: cmpld 1, 4, 3 +; CHECK-NEXT: bc 12, 20, .LBB12_3 ; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: crand 20, 2, 4 +; CHECK-NEXT: bc 12, 20, .LBB12_3 +; CHECK-NEXT: # %bb.2: ; CHECK-NEXT: vmr 2, 4 -; CHECK-NEXT: .LBB12_2: +; CHECK-NEXT: .LBB12_3: ; CHECK-NEXT: xxswapd 0, 34 ; CHECK-NEXT: mfvsrd 4, 34 ; CHECK-NEXT: mfvsrd 3, 0